1//===------ llvm/MC/MCInstrDesc.cpp- Instruction Descriptors --------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines methods on the MCOperandInfo and MCInstrDesc classes, which 10// are used to describe target instructions and their operands. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/MC/MCInstrDesc.h" 15#include "llvm/MC/MCInst.h" 16#include "llvm/MC/MCRegisterInfo.h" 17 18using namespace llvm; 19 20bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI, 21 const MCRegisterInfo &RI) const { 22 if (isBranch() || isCall() || isReturn() || isIndirectBranch()) 23 return true; 24 unsigned PC = RI.getProgramCounter(); 25 if (PC == 0) 26 return false; 27 if (hasDefOfPhysReg(MI, PC, RI)) 28 return true; 29 return false; 30} 31 32bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg, 33 const MCRegisterInfo *MRI) const { 34 for (MCPhysReg ImpDef : implicit_defs()) 35 if (ImpDef == Reg || (MRI && MRI->isSubRegister(Reg, ImpDef))) 36 return true; 37 return false; 38} 39 40bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg, 41 const MCRegisterInfo &RI) const { 42 for (int i = 0, e = NumDefs; i != e; ++i) 43 if (MI.getOperand(i).isReg() && 44 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) 45 return true; 46 if (variadicOpsAreDefs()) 47 for (int i = NumOperands - 1, e = MI.getNumOperands(); i != e; ++i) 48 if (MI.getOperand(i).isReg() && 49 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) 50 return true; 51 return hasImplicitDefOfPhysReg(Reg, &RI); 52} 53