1/* 2 * Driver for Cirrus Logic CS4281 based PCI soundcard 3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>, 4 * 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 22#include <sound/driver.h> 23#include <asm/io.h> 24#include <linux/delay.h> 25#include <linux/interrupt.h> 26#include <linux/init.h> 27#include <linux/pci.h> 28#include <linux/slab.h> 29#include <linux/gameport.h> 30#include <linux/moduleparam.h> 31#include <sound/core.h> 32#include <sound/control.h> 33#include <sound/pcm.h> 34#include <sound/rawmidi.h> 35#include <sound/ac97_codec.h> 36#include <sound/tlv.h> 37#include <sound/opl3.h> 38#include <sound/initval.h> 39 40 41MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>"); 42MODULE_DESCRIPTION("Cirrus Logic CS4281"); 43MODULE_LICENSE("GPL"); 44MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}"); 45 46static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 47static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 48static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 49static int dual_codec[SNDRV_CARDS]; /* dual codec */ 50 51module_param_array(index, int, NULL, 0444); 52MODULE_PARM_DESC(index, "Index value for CS4281 soundcard."); 53module_param_array(id, charp, NULL, 0444); 54MODULE_PARM_DESC(id, "ID string for CS4281 soundcard."); 55module_param_array(enable, bool, NULL, 0444); 56MODULE_PARM_DESC(enable, "Enable CS4281 soundcard."); 57module_param_array(dual_codec, bool, NULL, 0444); 58MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled)."); 59 60/* 61 * Direct registers 62 */ 63 64#define CS4281_BA0_SIZE 0x1000 65#define CS4281_BA1_SIZE 0x10000 66 67/* 68 * BA0 registers 69 */ 70#define BA0_HISR 0x0000 /* Host Interrupt Status Register */ 71#define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */ 72#define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */ 73#define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */ 74#define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */ 75#define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */ 76#define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */ 77#define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */ 78#define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */ 79#define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */ 80#define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */ 81#define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */ 82#define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */ 83 84#define BA0_HICR 0x0008 /* Host Interrupt Control Register */ 85#define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */ 86#define BA0_HICR_IEV (1<<0) /* INTENA Value */ 87#define BA0_HICR_EOI (3<<0) /* End of Interrupt command */ 88 89#define BA0_HIMR 0x000c /* Host Interrupt Mask Register */ 90 /* Use same contants as for BA0_HISR */ 91 92#define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */ 93 94#define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */ 95#define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */ 96#define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */ 97#define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */ 98 99#define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */ 100#define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */ 101#define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */ 102#define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */ 103#define BA0_HDSR_DRUN (1<<15) /* DMA Running */ 104#define BA0_HDSR_RQ (1<<7) /* Pending Request */ 105 106#define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */ 107#define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */ 108#define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */ 109#define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */ 110#define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */ 111#define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */ 112#define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */ 113#define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */ 114#define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */ 115#define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */ 116#define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */ 117#define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */ 118#define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */ 119#define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */ 120#define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */ 121#define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */ 122#define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */ 123#define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */ 124#define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */ 125#define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */ 126#define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */ 127#define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */ 128#define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */ 129#define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */ 130 131#define BA0_DMR_DMA (1<<29) /* Enable DMA mode */ 132#define BA0_DMR_POLL (1<<28) /* Enable poll mode */ 133#define BA0_DMR_TBC (1<<25) /* Transfer By Channel */ 134#define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */ 135#define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */ 136#define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */ 137#define BA0_DMR_USIGN (1<<19) /* Unsigned */ 138#define BA0_DMR_BEND (1<<18) /* Big Endian */ 139#define BA0_DMR_MONO (1<<17) /* Mono */ 140#define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */ 141#define BA0_DMR_TYPE_DEMAND (0<<6) 142#define BA0_DMR_TYPE_SINGLE (1<<6) 143#define BA0_DMR_TYPE_BLOCK (2<<6) 144#define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */ 145#define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */ 146#define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */ 147#define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */ 148#define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */ 149#define BA0_DMR_TR_READ (2<<2) /* Read Transfer */ 150 151#define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */ 152#define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */ 153#define BA0_DCR_MSK (1<<0) /* DMA Mask bit */ 154 155#define BA0_FCR0 0x0180 /* FIFO Control 0 */ 156#define BA0_FCR1 0x0184 /* FIFO Control 1 */ 157#define BA0_FCR2 0x0188 /* FIFO Control 2 */ 158#define BA0_FCR3 0x018c /* FIFO Control 3 */ 159 160#define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */ 161#define BA0_FCR_DACZ (1<<30) /* DAC Zero */ 162#define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */ 163#define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */ 164#define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */ 165#define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */ 166#define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */ 167 168#define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */ 169#define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */ 170#define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */ 171#define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */ 172 173#define BA0_FCHS 0x020c /* FIFO Channel Status */ 174#define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */ 175#define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */ 176#define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */ 177#define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */ 178#define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */ 179#define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */ 180#define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */ 181#define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */ 182 183#define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */ 184#define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */ 185#define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */ 186#define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */ 187 188#define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */ 189#define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */ 190#define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */ 191#define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */ 192#define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */ 193#define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */ 194#define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */ 195#define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */ 196 197#define BA0_PMCS 0x0344 /* Power Management Control/Status */ 198#define BA0_CWPR 0x03e0 /* Configuration Write Protect */ 199 200#define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */ 201#define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */ 202 203#define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */ 204 205#define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */ 206#define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */ 207#define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */ 208#define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */ 209#define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */ 210#define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */ 211#define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */ 212#define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */ 213#define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */ 214#define BA0_SPMC_RSTN (1<<0) /* Reset Not! */ 215 216#define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */ 217#define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */ 218#define BA0_IISR 0x03f4 /* ISA Interrupt Select */ 219#define BA0_TMS 0x03f8 /* Test Register */ 220#define BA0_SSVID 0x03fc /* Subsystem ID register */ 221 222#define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */ 223#define BA0_CLKCR1_CLKON (1<<25) /* Read Only */ 224#define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */ 225#define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */ 226#define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */ 227#define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */ 228#define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */ 229 230#define BA0_FRR 0x0410 /* Feature Reporting Register */ 231#define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */ 232 233#define BA0_SERMC 0x0420 /* Serial Port Master Control */ 234#define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */ 235#define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */ 236#define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */ 237#define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */ 238#define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */ 239#define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */ 240#define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */ 241#define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */ 242#define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */ 243#define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */ 244#define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */ 245#define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */ 246 247#define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */ 248#define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */ 249#define BA0_SERC1_AC97 (1<<1) 250#define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */ 251 252#define BA0_SERC2 0x042c /* Serial Port Configuration 2 */ 253#define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */ 254#define BA0_SERC2_AC97 (1<<1) 255#define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */ 256 257#define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */ 258 259#define BA0_ACCTL 0x0460 /* AC'97 Control */ 260#define BA0_ACCTL_TC (1<<6) /* Target Codec */ 261#define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */ 262#define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */ 263#define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */ 264#define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */ 265 266#define BA0_ACSTS 0x0464 /* AC'97 Status */ 267#define BA0_ACSTS_VSTS (1<<1) /* Valid Status */ 268#define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */ 269 270#define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */ 271#define BA0_ACOSV_SLV(x) (1<<((x)-3)) 272 273#define BA0_ACCAD 0x046c /* AC'97 Command Address */ 274#define BA0_ACCDA 0x0470 /* AC'97 Command Data */ 275 276#define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */ 277#define BA0_ACISV_SLV(x) (1<<((x)-3)) 278 279#define BA0_ACSAD 0x0478 /* AC'97 Status Address */ 280#define BA0_ACSDA 0x047c /* AC'97 Status Data */ 281#define BA0_JSPT 0x0480 /* Joystick poll/trigger */ 282#define BA0_JSCTL 0x0484 /* Joystick control */ 283#define BA0_JSC1 0x0488 /* Joystick control */ 284#define BA0_JSC2 0x048c /* Joystick control */ 285#define BA0_JSIO 0x04a0 286 287#define BA0_MIDCR 0x0490 /* MIDI Control */ 288#define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */ 289#define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */ 290#define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */ 291#define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */ 292#define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */ 293#define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */ 294 295#define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */ 296 297#define BA0_MIDSR 0x0494 /* MIDI Status (ro) */ 298#define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */ 299#define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */ 300#define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */ 301#define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */ 302 303#define BA0_MIDWP 0x0498 /* MIDI Write */ 304#define BA0_MIDRP 0x049c /* MIDI Read (ro) */ 305 306#define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */ 307#define BA0_AODSD1_NDS(x) (1<<((x)-3)) 308 309#define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */ 310#define BA0_AODSD2_NDS(x) (1<<((x)-3)) 311 312#define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */ 313#define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */ 314#define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */ 315#define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */ 316#define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */ 317#define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */ 318#define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */ 319#define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */ 320#define BA0_FMDP 0x0734 /* FM Data Port */ 321#define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */ 322#define BA0_B1DP 0x073c /* FM Bank 1 Data Port */ 323 324#define BA0_SSPM 0x0740 /* Sound System Power Management */ 325#define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */ 326#define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */ 327#define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */ 328#define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */ 329#define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */ 330#define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */ 331 332#define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */ 333#define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */ 334 335#define BA0_SSCR 0x074c /* Sound System Control Register */ 336#define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */ 337#define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */ 338#define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */ 339#define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */ 340#define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */ 341#define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */ 342#define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */ 343#define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */ 344#define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */ 345 346#define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */ 347#define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */ 348#define BA0_SRCSA 0x075c /* SRC Slot Assignments */ 349#define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */ 350#define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */ 351#define BA0_PASR 0x0768 /* playback sample rate */ 352#define BA0_CASR 0x076C /* capture sample rate */ 353 354/* Source Slot Numbers - Playback */ 355#define SRCSLOT_LEFT_PCM_PLAYBACK 0 356#define SRCSLOT_RIGHT_PCM_PLAYBACK 1 357#define SRCSLOT_PHONE_LINE_1_DAC 2 358#define SRCSLOT_CENTER_PCM_PLAYBACK 3 359#define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4 360#define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5 361#define SRCSLOT_LFE_PCM_PLAYBACK 6 362#define SRCSLOT_PHONE_LINE_2_DAC 7 363#define SRCSLOT_HEADSET_DAC 8 364#define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */ 365#define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */ 366 367/* Source Slot Numbers - Capture */ 368#define SRCSLOT_LEFT_PCM_RECORD 10 369#define SRCSLOT_RIGHT_PCM_RECORD 11 370#define SRCSLOT_PHONE_LINE_1_ADC 12 371#define SRCSLOT_MIC_ADC 13 372#define SRCSLOT_PHONE_LINE_2_ADC 17 373#define SRCSLOT_HEADSET_ADC 18 374#define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20 375#define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21 376#define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22 377#define SRCSLOT_SECONDARY_MIC_ADC 23 378#define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27 379#define SRCSLOT_SECONDARY_HEADSET_ADC 28 380 381/* Source Slot Numbers - Others */ 382#define SRCSLOT_POWER_DOWN 31 383 384/* MIDI modes */ 385#define CS4281_MODE_OUTPUT (1<<0) 386#define CS4281_MODE_INPUT (1<<1) 387 388/* joystick bits */ 389/* Bits for JSPT */ 390#define JSPT_CAX 0x00000001 391#define JSPT_CAY 0x00000002 392#define JSPT_CBX 0x00000004 393#define JSPT_CBY 0x00000008 394#define JSPT_BA1 0x00000010 395#define JSPT_BA2 0x00000020 396#define JSPT_BB1 0x00000040 397#define JSPT_BB2 0x00000080 398 399/* Bits for JSCTL */ 400#define JSCTL_SP_MASK 0x00000003 401#define JSCTL_SP_SLOW 0x00000000 402#define JSCTL_SP_MEDIUM_SLOW 0x00000001 403#define JSCTL_SP_MEDIUM_FAST 0x00000002 404#define JSCTL_SP_FAST 0x00000003 405#define JSCTL_ARE 0x00000004 406 407/* Data register pairs masks */ 408#define JSC1_Y1V_MASK 0x0000FFFF 409#define JSC1_X1V_MASK 0xFFFF0000 410#define JSC1_Y1V_SHIFT 0 411#define JSC1_X1V_SHIFT 16 412#define JSC2_Y2V_MASK 0x0000FFFF 413#define JSC2_X2V_MASK 0xFFFF0000 414#define JSC2_Y2V_SHIFT 0 415#define JSC2_X2V_SHIFT 16 416 417/* JS GPIO */ 418#define JSIO_DAX 0x00000001 419#define JSIO_DAY 0x00000002 420#define JSIO_DBX 0x00000004 421#define JSIO_DBY 0x00000008 422#define JSIO_AXOE 0x00000010 423#define JSIO_AYOE 0x00000020 424#define JSIO_BXOE 0x00000040 425#define JSIO_BYOE 0x00000080 426 427/* 428 * 429 */ 430 431struct cs4281_dma { 432 struct snd_pcm_substream *substream; 433 unsigned int regDBA; /* offset to DBA register */ 434 unsigned int regDCA; /* offset to DCA register */ 435 unsigned int regDBC; /* offset to DBC register */ 436 unsigned int regDCC; /* offset to DCC register */ 437 unsigned int regDMR; /* offset to DMR register */ 438 unsigned int regDCR; /* offset to DCR register */ 439 unsigned int regHDSR; /* offset to HDSR register */ 440 unsigned int regFCR; /* offset to FCR register */ 441 unsigned int regFSIC; /* offset to FSIC register */ 442 unsigned int valDMR; /* DMA mode */ 443 unsigned int valDCR; /* DMA command */ 444 unsigned int valFCR; /* FIFO control */ 445 unsigned int fifo_offset; /* FIFO offset within BA1 */ 446 unsigned char left_slot; /* FIFO left slot */ 447 unsigned char right_slot; /* FIFO right slot */ 448 int frag; /* period number */ 449}; 450 451#define SUSPEND_REGISTERS 20 452 453struct cs4281 { 454 int irq; 455 456 void __iomem *ba0; /* virtual (accessible) address */ 457 void __iomem *ba1; /* virtual (accessible) address */ 458 unsigned long ba0_addr; 459 unsigned long ba1_addr; 460 461 int dual_codec; 462 463 struct snd_ac97_bus *ac97_bus; 464 struct snd_ac97 *ac97; 465 struct snd_ac97 *ac97_secondary; 466 467 struct pci_dev *pci; 468 struct snd_card *card; 469 struct snd_pcm *pcm; 470 struct snd_rawmidi *rmidi; 471 struct snd_rawmidi_substream *midi_input; 472 struct snd_rawmidi_substream *midi_output; 473 474 struct cs4281_dma dma[4]; 475 476 unsigned char src_left_play_slot; 477 unsigned char src_right_play_slot; 478 unsigned char src_left_rec_slot; 479 unsigned char src_right_rec_slot; 480 481 unsigned int spurious_dhtc_irq; 482 unsigned int spurious_dtc_irq; 483 484 spinlock_t reg_lock; 485 unsigned int midcr; 486 unsigned int uartm; 487 488 struct gameport *gameport; 489 490#ifdef CONFIG_PM 491 u32 suspend_regs[SUSPEND_REGISTERS]; 492#endif 493 494}; 495 496static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id); 497 498static struct pci_device_id snd_cs4281_ids[] = { 499 { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CS4281 */ 500 { 0, } 501}; 502 503MODULE_DEVICE_TABLE(pci, snd_cs4281_ids); 504 505/* 506 * constants 507 */ 508 509#define CS4281_FIFO_SIZE 32 510 511/* 512 * common I/O routines 513 */ 514 515static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset, 516 unsigned int val) 517{ 518 writel(val, chip->ba0 + offset); 519} 520 521static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset) 522{ 523 return readl(chip->ba0 + offset); 524} 525 526static void snd_cs4281_ac97_write(struct snd_ac97 *ac97, 527 unsigned short reg, unsigned short val) 528{ 529 /* 530 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 531 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 532 * 3. Write ACCTL = Control Register = 460h for initiating the write 533 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h 534 * 5. if DCV not cleared, break and return error 535 */ 536 struct cs4281 *chip = ac97->private_data; 537 int count; 538 539 /* 540 * Setup the AC97 control registers on the CS461x to send the 541 * appropriate command to the AC97 to perform the read. 542 * ACCAD = Command Address Register = 46Ch 543 * ACCDA = Command Data Register = 470h 544 * ACCTL = Control Register = 460h 545 * set DCV - will clear when process completed 546 * reset CRW - Write command 547 * set VFRM - valid frame enabled 548 * set ESYN - ASYNC generation enabled 549 * set RSTN - ARST# inactive, AC97 codec not reset 550 */ 551 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); 552 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val); 553 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM | 554 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0)); 555 for (count = 0; count < 2000; count++) { 556 /* 557 * First, we want to wait for a short time. 558 */ 559 udelay(10); 560 /* 561 * Now, check to see if the write has completed. 562 * ACCTL = 460h, DCV should be reset by now and 460h = 07h 563 */ 564 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) { 565 return; 566 } 567 } 568 snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val); 569} 570 571static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97, 572 unsigned short reg) 573{ 574 struct cs4281 *chip = ac97->private_data; 575 int count; 576 unsigned short result; 577 // some gcc versions 578 volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num; 579 580 /* 581 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 582 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 583 * 3. Write ACCTL = Control Register = 460h for initiating the write 584 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h 585 * 5. if DCV not cleared, break and return error 586 * 6. Read ACSTS = Status Register = 464h, check VSTS bit 587 */ 588 589 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); 590 591 /* 592 * Setup the AC97 control registers on the CS461x to send the 593 * appropriate command to the AC97 to perform the read. 594 * ACCAD = Command Address Register = 46Ch 595 * ACCDA = Command Data Register = 470h 596 * ACCTL = Control Register = 460h 597 * set DCV - will clear when process completed 598 * set CRW - Read command 599 * set VFRM - valid frame enabled 600 * set ESYN - ASYNC generation enabled 601 * set RSTN - ARST# inactive, AC97 codec not reset 602 */ 603 604 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); 605 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0); 606 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW | 607 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN | 608 (ac97_num ? BA0_ACCTL_TC : 0)); 609 610 611 /* 612 * Wait for the read to occur. 613 */ 614 for (count = 0; count < 500; count++) { 615 /* 616 * First, we want to wait for a short time. 617 */ 618 udelay(10); 619 /* 620 * Now, check to see if the read has completed. 621 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 622 */ 623 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) 624 goto __ok1; 625 } 626 627 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); 628 result = 0xffff; 629 goto __end; 630 631 __ok1: 632 /* 633 * Wait for the valid status bit to go active. 634 */ 635 for (count = 0; count < 100; count++) { 636 /* 637 * Read the AC97 status register. 638 * ACSTS = Status Register = 464h 639 * VSTS - Valid Status 640 */ 641 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS) 642 goto __ok2; 643 udelay(10); 644 } 645 646 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg); 647 result = 0xffff; 648 goto __end; 649 650 __ok2: 651 /* 652 * Read the data returned from the AC97 register. 653 * ACSDA = Status Data Register = 474h 654 */ 655 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); 656 657 __end: 658 return result; 659} 660 661/* 662 * PCM part 663 */ 664 665static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd) 666{ 667 struct cs4281_dma *dma = substream->runtime->private_data; 668 struct cs4281 *chip = snd_pcm_substream_chip(substream); 669 670 spin_lock(&chip->reg_lock); 671 switch (cmd) { 672 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 673 dma->valDCR |= BA0_DCR_MSK; 674 dma->valFCR |= BA0_FCR_FEN; 675 break; 676 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 677 dma->valDCR &= ~BA0_DCR_MSK; 678 dma->valFCR &= ~BA0_FCR_FEN; 679 break; 680 case SNDRV_PCM_TRIGGER_START: 681 case SNDRV_PCM_TRIGGER_RESUME: 682 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA); 683 dma->valDMR |= BA0_DMR_DMA; 684 dma->valDCR &= ~BA0_DCR_MSK; 685 dma->valFCR |= BA0_FCR_FEN; 686 break; 687 case SNDRV_PCM_TRIGGER_STOP: 688 case SNDRV_PCM_TRIGGER_SUSPEND: 689 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL); 690 dma->valDCR |= BA0_DCR_MSK; 691 dma->valFCR &= ~BA0_FCR_FEN; 692 /* Leave wave playback FIFO enabled for FM */ 693 if (dma->regFCR != BA0_FCR0) 694 dma->valFCR &= ~BA0_FCR_FEN; 695 break; 696 default: 697 spin_unlock(&chip->reg_lock); 698 return -EINVAL; 699 } 700 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR); 701 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR); 702 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR); 703 spin_unlock(&chip->reg_lock); 704 return 0; 705} 706 707static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate) 708{ 709 unsigned int val = ~0; 710 711 if (real_rate) 712 *real_rate = rate; 713 /* special "hardcoded" rates */ 714 switch (rate) { 715 case 8000: return 5; 716 case 11025: return 4; 717 case 16000: return 3; 718 case 22050: return 2; 719 case 44100: return 1; 720 case 48000: return 0; 721 default: 722 goto __variable; 723 } 724 __variable: 725 val = 1536000 / rate; 726 if (real_rate) 727 *real_rate = 1536000 / val; 728 return val; 729} 730 731static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma, 732 struct snd_pcm_runtime *runtime, 733 int capture, int src) 734{ 735 int rec_mono; 736 737 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO | 738 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ); 739 if (runtime->channels == 1) 740 dma->valDMR |= BA0_DMR_MONO; 741 if (snd_pcm_format_unsigned(runtime->format) > 0) 742 dma->valDMR |= BA0_DMR_USIGN; 743 if (snd_pcm_format_big_endian(runtime->format) > 0) 744 dma->valDMR |= BA0_DMR_BEND; 745 switch (snd_pcm_format_width(runtime->format)) { 746 case 8: dma->valDMR |= BA0_DMR_SIZE8; 747 if (runtime->channels == 1) 748 dma->valDMR |= BA0_DMR_SWAPC; 749 break; 750 case 32: dma->valDMR |= BA0_DMR_SIZE20; break; 751 } 752 dma->frag = 0; 753 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK; 754 if (runtime->buffer_size != runtime->period_size) 755 dma->valDCR |= BA0_DCR_HTCIE; 756 /* Initialize DMA */ 757 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr); 758 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1); 759 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO; 760 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | 761 (chip->src_right_play_slot << 8) | 762 (chip->src_left_rec_slot << 16) | 763 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24)); 764 if (!src) 765 goto __skip_src; 766 if (!capture) { 767 if (dma->left_slot == chip->src_left_play_slot) { 768 unsigned int val = snd_cs4281_rate(runtime->rate, NULL); 769 snd_assert(dma->right_slot == chip->src_right_play_slot, ); 770 snd_cs4281_pokeBA0(chip, BA0_DACSR, val); 771 } 772 } else { 773 if (dma->left_slot == chip->src_left_rec_slot) { 774 unsigned int val = snd_cs4281_rate(runtime->rate, NULL); 775 snd_assert(dma->right_slot == chip->src_right_rec_slot, ); 776 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val); 777 } 778 } 779 __skip_src: 780 /* Deactivate wave playback FIFO before changing slot assignments */ 781 if (dma->regFCR == BA0_FCR0) 782 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN); 783 /* Initialize FIFO */ 784 dma->valFCR = BA0_FCR_LS(dma->left_slot) | 785 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) | 786 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 787 BA0_FCR_OF(dma->fifo_offset); 788 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0)); 789 /* Activate FIFO again for FM playback */ 790 if (dma->regFCR == BA0_FCR0) 791 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN); 792 /* Clear FIFO Status and Interrupt Control Register */ 793 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0); 794} 795 796static int snd_cs4281_hw_params(struct snd_pcm_substream *substream, 797 struct snd_pcm_hw_params *hw_params) 798{ 799 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 800} 801 802static int snd_cs4281_hw_free(struct snd_pcm_substream *substream) 803{ 804 return snd_pcm_lib_free_pages(substream); 805} 806 807static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream) 808{ 809 struct snd_pcm_runtime *runtime = substream->runtime; 810 struct cs4281_dma *dma = runtime->private_data; 811 struct cs4281 *chip = snd_pcm_substream_chip(substream); 812 813 spin_lock_irq(&chip->reg_lock); 814 snd_cs4281_mode(chip, dma, runtime, 0, 1); 815 spin_unlock_irq(&chip->reg_lock); 816 return 0; 817} 818 819static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream) 820{ 821 struct snd_pcm_runtime *runtime = substream->runtime; 822 struct cs4281_dma *dma = runtime->private_data; 823 struct cs4281 *chip = snd_pcm_substream_chip(substream); 824 825 spin_lock_irq(&chip->reg_lock); 826 snd_cs4281_mode(chip, dma, runtime, 1, 1); 827 spin_unlock_irq(&chip->reg_lock); 828 return 0; 829} 830 831static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream) 832{ 833 struct snd_pcm_runtime *runtime = substream->runtime; 834 struct cs4281_dma *dma = runtime->private_data; 835 struct cs4281 *chip = snd_pcm_substream_chip(substream); 836 837 // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies); 838 return runtime->buffer_size - 839 snd_cs4281_peekBA0(chip, dma->regDCC) - 1; 840} 841 842static struct snd_pcm_hardware snd_cs4281_playback = 843{ 844 .info = (SNDRV_PCM_INFO_MMAP | 845 SNDRV_PCM_INFO_INTERLEAVED | 846 SNDRV_PCM_INFO_MMAP_VALID | 847 SNDRV_PCM_INFO_PAUSE | 848 SNDRV_PCM_INFO_RESUME | 849 SNDRV_PCM_INFO_SYNC_START), 850 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | 851 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | 852 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | 853 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | 854 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, 855 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 856 .rate_min = 4000, 857 .rate_max = 48000, 858 .channels_min = 1, 859 .channels_max = 2, 860 .buffer_bytes_max = (512*1024), 861 .period_bytes_min = 64, 862 .period_bytes_max = (512*1024), 863 .periods_min = 1, 864 .periods_max = 2, 865 .fifo_size = CS4281_FIFO_SIZE, 866}; 867 868static struct snd_pcm_hardware snd_cs4281_capture = 869{ 870 .info = (SNDRV_PCM_INFO_MMAP | 871 SNDRV_PCM_INFO_INTERLEAVED | 872 SNDRV_PCM_INFO_MMAP_VALID | 873 SNDRV_PCM_INFO_PAUSE | 874 SNDRV_PCM_INFO_RESUME | 875 SNDRV_PCM_INFO_SYNC_START), 876 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | 877 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | 878 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | 879 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | 880 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, 881 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 882 .rate_min = 4000, 883 .rate_max = 48000, 884 .channels_min = 1, 885 .channels_max = 2, 886 .buffer_bytes_max = (512*1024), 887 .period_bytes_min = 64, 888 .period_bytes_max = (512*1024), 889 .periods_min = 1, 890 .periods_max = 2, 891 .fifo_size = CS4281_FIFO_SIZE, 892}; 893 894static int snd_cs4281_playback_open(struct snd_pcm_substream *substream) 895{ 896 struct cs4281 *chip = snd_pcm_substream_chip(substream); 897 struct snd_pcm_runtime *runtime = substream->runtime; 898 struct cs4281_dma *dma; 899 900 dma = &chip->dma[0]; 901 dma->substream = substream; 902 dma->left_slot = 0; 903 dma->right_slot = 1; 904 runtime->private_data = dma; 905 runtime->hw = snd_cs4281_playback; 906 snd_pcm_set_sync(substream); 907 /* should be detected from the AC'97 layer, but it seems 908 that although CS4297A rev B reports 18-bit ADC resolution, 909 samples are 20-bit */ 910 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 911 return 0; 912} 913 914static int snd_cs4281_capture_open(struct snd_pcm_substream *substream) 915{ 916 struct cs4281 *chip = snd_pcm_substream_chip(substream); 917 struct snd_pcm_runtime *runtime = substream->runtime; 918 struct cs4281_dma *dma; 919 920 dma = &chip->dma[1]; 921 dma->substream = substream; 922 dma->left_slot = 10; 923 dma->right_slot = 11; 924 runtime->private_data = dma; 925 runtime->hw = snd_cs4281_capture; 926 snd_pcm_set_sync(substream); 927 /* should be detected from the AC'97 layer, but it seems 928 that although CS4297A rev B reports 18-bit ADC resolution, 929 samples are 20-bit */ 930 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 931 return 0; 932} 933 934static int snd_cs4281_playback_close(struct snd_pcm_substream *substream) 935{ 936 struct cs4281_dma *dma = substream->runtime->private_data; 937 938 dma->substream = NULL; 939 return 0; 940} 941 942static int snd_cs4281_capture_close(struct snd_pcm_substream *substream) 943{ 944 struct cs4281_dma *dma = substream->runtime->private_data; 945 946 dma->substream = NULL; 947 return 0; 948} 949 950static struct snd_pcm_ops snd_cs4281_playback_ops = { 951 .open = snd_cs4281_playback_open, 952 .close = snd_cs4281_playback_close, 953 .ioctl = snd_pcm_lib_ioctl, 954 .hw_params = snd_cs4281_hw_params, 955 .hw_free = snd_cs4281_hw_free, 956 .prepare = snd_cs4281_playback_prepare, 957 .trigger = snd_cs4281_trigger, 958 .pointer = snd_cs4281_pointer, 959}; 960 961static struct snd_pcm_ops snd_cs4281_capture_ops = { 962 .open = snd_cs4281_capture_open, 963 .close = snd_cs4281_capture_close, 964 .ioctl = snd_pcm_lib_ioctl, 965 .hw_params = snd_cs4281_hw_params, 966 .hw_free = snd_cs4281_hw_free, 967 .prepare = snd_cs4281_capture_prepare, 968 .trigger = snd_cs4281_trigger, 969 .pointer = snd_cs4281_pointer, 970}; 971 972static int __devinit snd_cs4281_pcm(struct cs4281 * chip, int device, 973 struct snd_pcm ** rpcm) 974{ 975 struct snd_pcm *pcm; 976 int err; 977 978 if (rpcm) 979 *rpcm = NULL; 980 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm); 981 if (err < 0) 982 return err; 983 984 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops); 985 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops); 986 987 pcm->private_data = chip; 988 pcm->info_flags = 0; 989 strcpy(pcm->name, "CS4281"); 990 chip->pcm = pcm; 991 992 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 993 snd_dma_pci_data(chip->pci), 64*1024, 512*1024); 994 995 if (rpcm) 996 *rpcm = pcm; 997 return 0; 998} 999 1000/* 1001 * Mixer section 1002 */ 1003 1004#define CS_VOL_MASK 0x1f 1005 1006static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol, 1007 struct snd_ctl_elem_info *uinfo) 1008{ 1009 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1010 uinfo->count = 2; 1011 uinfo->value.integer.min = 0; 1012 uinfo->value.integer.max = CS_VOL_MASK; 1013 return 0; 1014} 1015 1016static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol, 1017 struct snd_ctl_elem_value *ucontrol) 1018{ 1019 struct cs4281 *chip = snd_kcontrol_chip(kcontrol); 1020 int regL = (kcontrol->private_value >> 16) & 0xffff; 1021 int regR = kcontrol->private_value & 0xffff; 1022 int volL, volR; 1023 1024 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); 1025 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); 1026 1027 ucontrol->value.integer.value[0] = volL; 1028 ucontrol->value.integer.value[1] = volR; 1029 return 0; 1030} 1031 1032static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol, 1033 struct snd_ctl_elem_value *ucontrol) 1034{ 1035 struct cs4281 *chip = snd_kcontrol_chip(kcontrol); 1036 int change = 0; 1037 int regL = (kcontrol->private_value >> 16) & 0xffff; 1038 int regR = kcontrol->private_value & 0xffff; 1039 int volL, volR; 1040 1041 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); 1042 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); 1043 1044 if (ucontrol->value.integer.value[0] != volL) { 1045 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK); 1046 snd_cs4281_pokeBA0(chip, regL, volL); 1047 change = 1; 1048 } 1049 if (ucontrol->value.integer.value[1] != volR) { 1050 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK); 1051 snd_cs4281_pokeBA0(chip, regR, volR); 1052 change = 1; 1053 } 1054 return change; 1055} 1056 1057static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0); 1058 1059static struct snd_kcontrol_new snd_cs4281_fm_vol = 1060{ 1061 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1062 .name = "Synth Playback Volume", 1063 .info = snd_cs4281_info_volume, 1064 .get = snd_cs4281_get_volume, 1065 .put = snd_cs4281_put_volume, 1066 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC), 1067 .tlv = { .p = db_scale_dsp }, 1068}; 1069 1070static struct snd_kcontrol_new snd_cs4281_pcm_vol = 1071{ 1072 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1073 .name = "PCM Stream Playback Volume", 1074 .info = snd_cs4281_info_volume, 1075 .get = snd_cs4281_get_volume, 1076 .put = snd_cs4281_put_volume, 1077 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC), 1078 .tlv = { .p = db_scale_dsp }, 1079}; 1080 1081static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1082{ 1083 struct cs4281 *chip = bus->private_data; 1084 chip->ac97_bus = NULL; 1085} 1086 1087static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97) 1088{ 1089 struct cs4281 *chip = ac97->private_data; 1090 if (ac97->num) 1091 chip->ac97_secondary = NULL; 1092 else 1093 chip->ac97 = NULL; 1094} 1095 1096static int __devinit snd_cs4281_mixer(struct cs4281 * chip) 1097{ 1098 struct snd_card *card = chip->card; 1099 struct snd_ac97_template ac97; 1100 int err; 1101 static struct snd_ac97_bus_ops ops = { 1102 .write = snd_cs4281_ac97_write, 1103 .read = snd_cs4281_ac97_read, 1104 }; 1105 1106 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0) 1107 return err; 1108 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus; 1109 1110 memset(&ac97, 0, sizeof(ac97)); 1111 ac97.private_data = chip; 1112 ac97.private_free = snd_cs4281_mixer_free_ac97; 1113 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0) 1114 return err; 1115 if (chip->dual_codec) { 1116 ac97.num = 1; 1117 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0) 1118 return err; 1119 } 1120 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0) 1121 return err; 1122 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0) 1123 return err; 1124 return 0; 1125} 1126 1127 1128/* 1129 * proc interface 1130 */ 1131 1132static void snd_cs4281_proc_read(struct snd_info_entry *entry, 1133 struct snd_info_buffer *buffer) 1134{ 1135 struct cs4281 *chip = entry->private_data; 1136 1137 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n"); 1138 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq); 1139 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq); 1140} 1141 1142static long snd_cs4281_BA0_read(struct snd_info_entry *entry, 1143 void *file_private_data, 1144 struct file *file, char __user *buf, 1145 unsigned long count, unsigned long pos) 1146{ 1147 long size; 1148 struct cs4281 *chip = entry->private_data; 1149 1150 size = count; 1151 if (pos + size > CS4281_BA0_SIZE) 1152 size = (long)CS4281_BA0_SIZE - pos; 1153 if (size > 0) { 1154 if (copy_to_user_fromio(buf, chip->ba0 + pos, size)) 1155 return -EFAULT; 1156 } 1157 return size; 1158} 1159 1160static long snd_cs4281_BA1_read(struct snd_info_entry *entry, 1161 void *file_private_data, 1162 struct file *file, char __user *buf, 1163 unsigned long count, unsigned long pos) 1164{ 1165 long size; 1166 struct cs4281 *chip = entry->private_data; 1167 1168 size = count; 1169 if (pos + size > CS4281_BA1_SIZE) 1170 size = (long)CS4281_BA1_SIZE - pos; 1171 if (size > 0) { 1172 if (copy_to_user_fromio(buf, chip->ba1 + pos, size)) 1173 return -EFAULT; 1174 } 1175 return size; 1176} 1177 1178static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = { 1179 .read = snd_cs4281_BA0_read, 1180}; 1181 1182static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = { 1183 .read = snd_cs4281_BA1_read, 1184}; 1185 1186static void __devinit snd_cs4281_proc_init(struct cs4281 * chip) 1187{ 1188 struct snd_info_entry *entry; 1189 1190 if (! snd_card_proc_new(chip->card, "cs4281", &entry)) 1191 snd_info_set_text_ops(entry, chip, snd_cs4281_proc_read); 1192 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) { 1193 entry->content = SNDRV_INFO_CONTENT_DATA; 1194 entry->private_data = chip; 1195 entry->c.ops = &snd_cs4281_proc_ops_BA0; 1196 entry->size = CS4281_BA0_SIZE; 1197 } 1198 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) { 1199 entry->content = SNDRV_INFO_CONTENT_DATA; 1200 entry->private_data = chip; 1201 entry->c.ops = &snd_cs4281_proc_ops_BA1; 1202 entry->size = CS4281_BA1_SIZE; 1203 } 1204} 1205 1206/* 1207 * joystick support 1208 */ 1209 1210#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 1211 1212static void snd_cs4281_gameport_trigger(struct gameport *gameport) 1213{ 1214 struct cs4281 *chip = gameport_get_port_data(gameport); 1215 1216 snd_assert(chip, return); 1217 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff); 1218} 1219 1220static unsigned char snd_cs4281_gameport_read(struct gameport *gameport) 1221{ 1222 struct cs4281 *chip = gameport_get_port_data(gameport); 1223 1224 snd_assert(chip, return 0); 1225 return snd_cs4281_peekBA0(chip, BA0_JSPT); 1226} 1227 1228#ifdef COOKED_MODE 1229static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, 1230 int *axes, int *buttons) 1231{ 1232 struct cs4281 *chip = gameport_get_port_data(gameport); 1233 unsigned js1, js2, jst; 1234 1235 snd_assert(chip, return 0); 1236 1237 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1); 1238 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2); 1239 jst = snd_cs4281_peekBA0(chip, BA0_JSPT); 1240 1241 *buttons = (~jst >> 4) & 0x0F; 1242 1243 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; 1244 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; 1245 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; 1246 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; 1247 1248 for (jst = 0; jst < 4; ++jst) 1249 if (axes[jst] == 0xFFFF) axes[jst] = -1; 1250 return 0; 1251} 1252#else 1253#define snd_cs4281_gameport_cooked_read NULL 1254#endif 1255 1256static int snd_cs4281_gameport_open(struct gameport *gameport, int mode) 1257{ 1258 switch (mode) { 1259#ifdef COOKED_MODE 1260 case GAMEPORT_MODE_COOKED: 1261 return 0; 1262#endif 1263 case GAMEPORT_MODE_RAW: 1264 return 0; 1265 default: 1266 return -1; 1267 } 1268 return 0; 1269} 1270 1271static int __devinit snd_cs4281_create_gameport(struct cs4281 *chip) 1272{ 1273 struct gameport *gp; 1274 1275 chip->gameport = gp = gameport_allocate_port(); 1276 if (!gp) { 1277 printk(KERN_ERR "cs4281: cannot allocate memory for gameport\n"); 1278 return -ENOMEM; 1279 } 1280 1281 gameport_set_name(gp, "CS4281 Gameport"); 1282 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 1283 gameport_set_dev_parent(gp, &chip->pci->dev); 1284 gp->open = snd_cs4281_gameport_open; 1285 gp->read = snd_cs4281_gameport_read; 1286 gp->trigger = snd_cs4281_gameport_trigger; 1287 gp->cooked_read = snd_cs4281_gameport_cooked_read; 1288 gameport_set_port_data(gp, chip); 1289 1290 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ? 1291 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); 1292 1293 gameport_register_port(gp); 1294 1295 return 0; 1296} 1297 1298static void snd_cs4281_free_gameport(struct cs4281 *chip) 1299{ 1300 if (chip->gameport) { 1301 gameport_unregister_port(chip->gameport); 1302 chip->gameport = NULL; 1303 } 1304} 1305#else 1306static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; } 1307static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { } 1308#endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */ 1309 1310static int snd_cs4281_free(struct cs4281 *chip) 1311{ 1312 snd_cs4281_free_gameport(chip); 1313 1314 if (chip->irq >= 0) 1315 synchronize_irq(chip->irq); 1316 1317 /* Mask interrupts */ 1318 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff); 1319 /* Stop the DLL Clock logic. */ 1320 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 1321 /* Sound System Power Management - Turn Everything OFF */ 1322 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); 1323 /* PCI interface - D3 state */ 1324 pci_set_power_state(chip->pci, 3); 1325 1326 if (chip->irq >= 0) 1327 free_irq(chip->irq, chip); 1328 if (chip->ba0) 1329 iounmap(chip->ba0); 1330 if (chip->ba1) 1331 iounmap(chip->ba1); 1332 pci_release_regions(chip->pci); 1333 pci_disable_device(chip->pci); 1334 1335 kfree(chip); 1336 return 0; 1337} 1338 1339static int snd_cs4281_dev_free(struct snd_device *device) 1340{ 1341 struct cs4281 *chip = device->device_data; 1342 return snd_cs4281_free(chip); 1343} 1344 1345static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */ 1346 1347static int __devinit snd_cs4281_create(struct snd_card *card, 1348 struct pci_dev *pci, 1349 struct cs4281 ** rchip, 1350 int dual_codec) 1351{ 1352 struct cs4281 *chip; 1353 unsigned int tmp; 1354 int err; 1355 static struct snd_device_ops ops = { 1356 .dev_free = snd_cs4281_dev_free, 1357 }; 1358 1359 *rchip = NULL; 1360 if ((err = pci_enable_device(pci)) < 0) 1361 return err; 1362 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1363 if (chip == NULL) { 1364 pci_disable_device(pci); 1365 return -ENOMEM; 1366 } 1367 spin_lock_init(&chip->reg_lock); 1368 chip->card = card; 1369 chip->pci = pci; 1370 chip->irq = -1; 1371 pci_set_master(pci); 1372 if (dual_codec < 0 || dual_codec > 3) { 1373 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec); 1374 dual_codec = 0; 1375 } 1376 chip->dual_codec = dual_codec; 1377 1378 if ((err = pci_request_regions(pci, "CS4281")) < 0) { 1379 kfree(chip); 1380 pci_disable_device(pci); 1381 return err; 1382 } 1383 chip->ba0_addr = pci_resource_start(pci, 0); 1384 chip->ba1_addr = pci_resource_start(pci, 1); 1385 1386 chip->ba0 = ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0)); 1387 chip->ba1 = ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1)); 1388 if (!chip->ba0 || !chip->ba1) { 1389 snd_cs4281_free(chip); 1390 return -ENOMEM; 1391 } 1392 1393 if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED, 1394 "CS4281", chip)) { 1395 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 1396 snd_cs4281_free(chip); 1397 return -ENOMEM; 1398 } 1399 chip->irq = pci->irq; 1400 1401 tmp = snd_cs4281_chip_init(chip); 1402 if (tmp) { 1403 snd_cs4281_free(chip); 1404 return tmp; 1405 } 1406 1407 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1408 snd_cs4281_free(chip); 1409 return err; 1410 } 1411 1412 snd_cs4281_proc_init(chip); 1413 1414 snd_card_set_dev(card, &pci->dev); 1415 1416 *rchip = chip; 1417 return 0; 1418} 1419 1420static int snd_cs4281_chip_init(struct cs4281 *chip) 1421{ 1422 unsigned int tmp; 1423 unsigned long end_time; 1424 int retry_count = 2; 1425 1426 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */ 1427 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC); 1428 if (tmp & BA0_EPPMC_FPDN) 1429 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN); 1430 1431 __retry: 1432 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); 1433 if (tmp != BA0_CFLR_DEFAULT) { 1434 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT); 1435 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); 1436 if (tmp != BA0_CFLR_DEFAULT) { 1437 snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp); 1438 return -EIO; 1439 } 1440 } 1441 1442 /* Set the 'Configuration Write Protect' register 1443 * to 4281h. Allows vendor-defined configuration 1444 * space between 0e4h and 0ffh to be written. */ 1445 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281); 1446 1447 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) { 1448 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp); 1449 return -EIO; 1450 } 1451 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) { 1452 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp); 1453 return -EIO; 1454 } 1455 1456 /* Sound System Power Management */ 1457 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN | 1458 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN | 1459 BA0_SSPM_ACLEN | BA0_SSPM_FMEN); 1460 1461 /* Serial Port Power Management */ 1462 /* Blast the clock control register to zero so that the 1463 * PLL starts out in a known state, and blast the master serial 1464 * port control register to zero so that the serial ports also 1465 * start out in a known state. */ 1466 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 1467 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); 1468 1469 /* Make ESYN go to zero to turn off 1470 * the Sync pulse on the AC97 link. */ 1471 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0); 1472 udelay(50); 1473 1474 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 1475 * spec) and then drive it high. This is done for non AC97 modes since 1476 * there might be logic external to the CS4281 that uses the ARST# line 1477 * for a reset. */ 1478 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); 1479 udelay(50); 1480 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN); 1481 msleep(50); 1482 1483 if (chip->dual_codec) 1484 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E); 1485 1486 /* 1487 * Set the serial port timing configuration. 1488 */ 1489 snd_cs4281_pokeBA0(chip, BA0_SERMC, 1490 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) | 1491 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE); 1492 1493 /* 1494 * Start the DLL Clock logic. 1495 */ 1496 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP); 1497 msleep(50); 1498 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP); 1499 1500 /* 1501 * Wait for the DLL ready signal from the clock logic. 1502 */ 1503 end_time = jiffies + HZ; 1504 do { 1505 /* 1506 * Read the AC97 status register to see if we've seen a CODEC 1507 * signal from the AC97 codec. 1508 */ 1509 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY) 1510 goto __ok0; 1511 schedule_timeout_uninterruptible(1); 1512 } while (time_after_eq(end_time, jiffies)); 1513 1514 snd_printk(KERN_ERR "DLLRDY not seen\n"); 1515 return -EIO; 1516 1517 __ok0: 1518 1519 /* 1520 * The first thing we do here is to enable sync generation. As soon 1521 * as we start receiving bit clock, we'll start producing the SYNC 1522 * signal. 1523 */ 1524 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN); 1525 1526 /* 1527 * Wait for the codec ready signal from the AC97 codec. 1528 */ 1529 end_time = jiffies + HZ; 1530 do { 1531 /* 1532 * Read the AC97 status register to see if we've seen a CODEC 1533 * signal from the AC97 codec. 1534 */ 1535 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY) 1536 goto __ok1; 1537 schedule_timeout_uninterruptible(1); 1538 } while (time_after_eq(end_time, jiffies)); 1539 1540 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS)); 1541 return -EIO; 1542 1543 __ok1: 1544 if (chip->dual_codec) { 1545 end_time = jiffies + HZ; 1546 do { 1547 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY) 1548 goto __codec2_ok; 1549 schedule_timeout_uninterruptible(1); 1550 } while (time_after_eq(end_time, jiffies)); 1551 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n"); 1552 chip->dual_codec = 0; 1553 __codec2_ok: ; 1554 } 1555 1556 /* 1557 * Assert the valid frame signal so that we can start sending commands 1558 * to the AC97 codec. 1559 */ 1560 1561 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN); 1562 1563 /* 1564 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 1565 * the codec is pumping ADC data across the AC-link. 1566 */ 1567 1568 end_time = jiffies + HZ; 1569 do { 1570 /* 1571 * Read the input slot valid register and see if input slots 3 1572 * 4 are valid yet. 1573 */ 1574 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) 1575 goto __ok2; 1576 schedule_timeout_uninterruptible(1); 1577 } while (time_after_eq(end_time, jiffies)); 1578 1579 if (--retry_count > 0) 1580 goto __retry; 1581 snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n"); 1582 return -EIO; 1583 1584 __ok2: 1585 1586 /* 1587 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 1588 * commense the transfer of digital audio data to the AC97 codec. 1589 */ 1590 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4)); 1591 1592 /* 1593 * Initialize DMA structures 1594 */ 1595 for (tmp = 0; tmp < 4; tmp++) { 1596 struct cs4281_dma *dma = &chip->dma[tmp]; 1597 dma->regDBA = BA0_DBA0 + (tmp * 0x10); 1598 dma->regDCA = BA0_DCA0 + (tmp * 0x10); 1599 dma->regDBC = BA0_DBC0 + (tmp * 0x10); 1600 dma->regDCC = BA0_DCC0 + (tmp * 0x10); 1601 dma->regDMR = BA0_DMR0 + (tmp * 8); 1602 dma->regDCR = BA0_DCR0 + (tmp * 8); 1603 dma->regHDSR = BA0_HDSR0 + (tmp * 4); 1604 dma->regFCR = BA0_FCR0 + (tmp * 4); 1605 dma->regFSIC = BA0_FSIC0 + (tmp * 4); 1606 dma->fifo_offset = tmp * CS4281_FIFO_SIZE; 1607 snd_cs4281_pokeBA0(chip, dma->regFCR, 1608 BA0_FCR_LS(31) | 1609 BA0_FCR_RS(31) | 1610 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 1611 BA0_FCR_OF(dma->fifo_offset)); 1612 } 1613 1614 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */ 1615 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */ 1616 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */ 1617 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */ 1618 1619 /* Activate wave playback FIFO for FM playback */ 1620 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) | 1621 BA0_FCR_RS(1) | 1622 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 1623 BA0_FCR_OF(chip->dma[0].fifo_offset); 1624 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR); 1625 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | 1626 (chip->src_right_play_slot << 8) | 1627 (chip->src_left_rec_slot << 16) | 1628 (chip->src_right_rec_slot << 24)); 1629 1630 /* Initialize digital volume */ 1631 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0); 1632 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0); 1633 1634 /* Enable IRQs */ 1635 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1636 /* Unmask interrupts */ 1637 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~( 1638 BA0_HISR_MIDI | 1639 BA0_HISR_DMAI | 1640 BA0_HISR_DMA(0) | 1641 BA0_HISR_DMA(1) | 1642 BA0_HISR_DMA(2) | 1643 BA0_HISR_DMA(3))); 1644 synchronize_irq(chip->irq); 1645 1646 return 0; 1647} 1648 1649/* 1650 * MIDI section 1651 */ 1652 1653static void snd_cs4281_midi_reset(struct cs4281 *chip) 1654{ 1655 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST); 1656 udelay(100); 1657 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1658} 1659 1660static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream) 1661{ 1662 struct cs4281 *chip = substream->rmidi->private_data; 1663 1664 spin_lock_irq(&chip->reg_lock); 1665 chip->midcr |= BA0_MIDCR_RXE; 1666 chip->midi_input = substream; 1667 if (!(chip->uartm & CS4281_MODE_OUTPUT)) { 1668 snd_cs4281_midi_reset(chip); 1669 } else { 1670 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1671 } 1672 spin_unlock_irq(&chip->reg_lock); 1673 return 0; 1674} 1675 1676static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream) 1677{ 1678 struct cs4281 *chip = substream->rmidi->private_data; 1679 1680 spin_lock_irq(&chip->reg_lock); 1681 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE); 1682 chip->midi_input = NULL; 1683 if (!(chip->uartm & CS4281_MODE_OUTPUT)) { 1684 snd_cs4281_midi_reset(chip); 1685 } else { 1686 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1687 } 1688 chip->uartm &= ~CS4281_MODE_INPUT; 1689 spin_unlock_irq(&chip->reg_lock); 1690 return 0; 1691} 1692 1693static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream) 1694{ 1695 struct cs4281 *chip = substream->rmidi->private_data; 1696 1697 spin_lock_irq(&chip->reg_lock); 1698 chip->uartm |= CS4281_MODE_OUTPUT; 1699 chip->midcr |= BA0_MIDCR_TXE; 1700 chip->midi_output = substream; 1701 if (!(chip->uartm & CS4281_MODE_INPUT)) { 1702 snd_cs4281_midi_reset(chip); 1703 } else { 1704 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1705 } 1706 spin_unlock_irq(&chip->reg_lock); 1707 return 0; 1708} 1709 1710static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream) 1711{ 1712 struct cs4281 *chip = substream->rmidi->private_data; 1713 1714 spin_lock_irq(&chip->reg_lock); 1715 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE); 1716 chip->midi_output = NULL; 1717 if (!(chip->uartm & CS4281_MODE_INPUT)) { 1718 snd_cs4281_midi_reset(chip); 1719 } else { 1720 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1721 } 1722 chip->uartm &= ~CS4281_MODE_OUTPUT; 1723 spin_unlock_irq(&chip->reg_lock); 1724 return 0; 1725} 1726 1727static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1728{ 1729 unsigned long flags; 1730 struct cs4281 *chip = substream->rmidi->private_data; 1731 1732 spin_lock_irqsave(&chip->reg_lock, flags); 1733 if (up) { 1734 if ((chip->midcr & BA0_MIDCR_RIE) == 0) { 1735 chip->midcr |= BA0_MIDCR_RIE; 1736 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1737 } 1738 } else { 1739 if (chip->midcr & BA0_MIDCR_RIE) { 1740 chip->midcr &= ~BA0_MIDCR_RIE; 1741 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1742 } 1743 } 1744 spin_unlock_irqrestore(&chip->reg_lock, flags); 1745} 1746 1747static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1748{ 1749 unsigned long flags; 1750 struct cs4281 *chip = substream->rmidi->private_data; 1751 unsigned char byte; 1752 1753 spin_lock_irqsave(&chip->reg_lock, flags); 1754 if (up) { 1755 if ((chip->midcr & BA0_MIDCR_TIE) == 0) { 1756 chip->midcr |= BA0_MIDCR_TIE; 1757 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 1758 while ((chip->midcr & BA0_MIDCR_TIE) && 1759 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) { 1760 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 1761 chip->midcr &= ~BA0_MIDCR_TIE; 1762 } else { 1763 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte); 1764 } 1765 } 1766 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1767 } 1768 } else { 1769 if (chip->midcr & BA0_MIDCR_TIE) { 1770 chip->midcr &= ~BA0_MIDCR_TIE; 1771 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1772 } 1773 } 1774 spin_unlock_irqrestore(&chip->reg_lock, flags); 1775} 1776 1777static struct snd_rawmidi_ops snd_cs4281_midi_output = 1778{ 1779 .open = snd_cs4281_midi_output_open, 1780 .close = snd_cs4281_midi_output_close, 1781 .trigger = snd_cs4281_midi_output_trigger, 1782}; 1783 1784static struct snd_rawmidi_ops snd_cs4281_midi_input = 1785{ 1786 .open = snd_cs4281_midi_input_open, 1787 .close = snd_cs4281_midi_input_close, 1788 .trigger = snd_cs4281_midi_input_trigger, 1789}; 1790 1791static int __devinit snd_cs4281_midi(struct cs4281 * chip, int device, 1792 struct snd_rawmidi **rrawmidi) 1793{ 1794 struct snd_rawmidi *rmidi; 1795 int err; 1796 1797 if (rrawmidi) 1798 *rrawmidi = NULL; 1799 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0) 1800 return err; 1801 strcpy(rmidi->name, "CS4281"); 1802 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output); 1803 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input); 1804 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; 1805 rmidi->private_data = chip; 1806 chip->rmidi = rmidi; 1807 if (rrawmidi) 1808 *rrawmidi = rmidi; 1809 return 0; 1810} 1811 1812/* 1813 * Interrupt handler 1814 */ 1815 1816static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id) 1817{ 1818 struct cs4281 *chip = dev_id; 1819 unsigned int status, dma, val; 1820 struct cs4281_dma *cdma; 1821 1822 if (chip == NULL) 1823 return IRQ_NONE; 1824 status = snd_cs4281_peekBA0(chip, BA0_HISR); 1825 if ((status & 0x7fffffff) == 0) { 1826 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1827 return IRQ_NONE; 1828 } 1829 1830 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) { 1831 for (dma = 0; dma < 4; dma++) 1832 if (status & BA0_HISR_DMA(dma)) { 1833 cdma = &chip->dma[dma]; 1834 spin_lock(&chip->reg_lock); 1835 /* ack DMA IRQ */ 1836 val = snd_cs4281_peekBA0(chip, cdma->regHDSR); 1837 /* end or middle transfer position twice */ 1838 cdma->frag++; 1839 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) { 1840 cdma->frag--; 1841 chip->spurious_dhtc_irq++; 1842 spin_unlock(&chip->reg_lock); 1843 continue; 1844 } 1845 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) { 1846 cdma->frag--; 1847 chip->spurious_dtc_irq++; 1848 spin_unlock(&chip->reg_lock); 1849 continue; 1850 } 1851 spin_unlock(&chip->reg_lock); 1852 snd_pcm_period_elapsed(cdma->substream); 1853 } 1854 } 1855 1856 if ((status & BA0_HISR_MIDI) && chip->rmidi) { 1857 unsigned char c; 1858 1859 spin_lock(&chip->reg_lock); 1860 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) { 1861 c = snd_cs4281_peekBA0(chip, BA0_MIDRP); 1862 if ((chip->midcr & BA0_MIDCR_RIE) == 0) 1863 continue; 1864 snd_rawmidi_receive(chip->midi_input, &c, 1); 1865 } 1866 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) { 1867 if ((chip->midcr & BA0_MIDCR_TIE) == 0) 1868 break; 1869 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { 1870 chip->midcr &= ~BA0_MIDCR_TIE; 1871 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1872 break; 1873 } 1874 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c); 1875 } 1876 spin_unlock(&chip->reg_lock); 1877 } 1878 1879 /* EOI to the PCI part... reenables interrupts */ 1880 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1881 1882 return IRQ_HANDLED; 1883} 1884 1885 1886/* 1887 * OPL3 command 1888 */ 1889static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd, 1890 unsigned char val) 1891{ 1892 unsigned long flags; 1893 struct cs4281 *chip = opl3->private_data; 1894 void __iomem *port; 1895 1896 if (cmd & OPL3_RIGHT) 1897 port = chip->ba0 + BA0_B1AP; /* right port */ 1898 else 1899 port = chip->ba0 + BA0_B0AP; /* left port */ 1900 1901 spin_lock_irqsave(&opl3->reg_lock, flags); 1902 1903 writel((unsigned int)cmd, port); 1904 udelay(10); 1905 1906 writel((unsigned int)val, port + 4); 1907 udelay(30); 1908 1909 spin_unlock_irqrestore(&opl3->reg_lock, flags); 1910} 1911 1912static int __devinit snd_cs4281_probe(struct pci_dev *pci, 1913 const struct pci_device_id *pci_id) 1914{ 1915 static int dev; 1916 struct snd_card *card; 1917 struct cs4281 *chip; 1918 struct snd_opl3 *opl3; 1919 int err; 1920 1921 if (dev >= SNDRV_CARDS) 1922 return -ENODEV; 1923 if (!enable[dev]) { 1924 dev++; 1925 return -ENOENT; 1926 } 1927 1928 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 1929 if (card == NULL) 1930 return -ENOMEM; 1931 1932 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) { 1933 snd_card_free(card); 1934 return err; 1935 } 1936 card->private_data = chip; 1937 1938 if ((err = snd_cs4281_mixer(chip)) < 0) { 1939 snd_card_free(card); 1940 return err; 1941 } 1942 if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) { 1943 snd_card_free(card); 1944 return err; 1945 } 1946 if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) { 1947 snd_card_free(card); 1948 return err; 1949 } 1950 if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) { 1951 snd_card_free(card); 1952 return err; 1953 } 1954 opl3->private_data = chip; 1955 opl3->command = snd_cs4281_opl3_command; 1956 snd_opl3_init(opl3); 1957 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) { 1958 snd_card_free(card); 1959 return err; 1960 } 1961 snd_cs4281_create_gameport(chip); 1962 strcpy(card->driver, "CS4281"); 1963 strcpy(card->shortname, "Cirrus Logic CS4281"); 1964 sprintf(card->longname, "%s at 0x%lx, irq %d", 1965 card->shortname, 1966 chip->ba0_addr, 1967 chip->irq); 1968 1969 if ((err = snd_card_register(card)) < 0) { 1970 snd_card_free(card); 1971 return err; 1972 } 1973 1974 pci_set_drvdata(pci, card); 1975 dev++; 1976 return 0; 1977} 1978 1979static void __devexit snd_cs4281_remove(struct pci_dev *pci) 1980{ 1981 snd_card_free(pci_get_drvdata(pci)); 1982 pci_set_drvdata(pci, NULL); 1983} 1984 1985/* 1986 * Power Management 1987 */ 1988#ifdef CONFIG_PM 1989 1990static int saved_regs[SUSPEND_REGISTERS] = { 1991 BA0_JSCTL, 1992 BA0_GPIOR, 1993 BA0_SSCR, 1994 BA0_MIDCR, 1995 BA0_SRCSA, 1996 BA0_PASR, 1997 BA0_CASR, 1998 BA0_DACSR, 1999 BA0_ADCSR, 2000 BA0_FMLVC, 2001 BA0_FMRVC, 2002 BA0_PPLVC, 2003 BA0_PPRVC, 2004}; 2005 2006#define CLKCR1_CKRA 0x00010000L 2007 2008static int cs4281_suspend(struct pci_dev *pci, pm_message_t state) 2009{ 2010 struct snd_card *card = pci_get_drvdata(pci); 2011 struct cs4281 *chip = card->private_data; 2012 u32 ulCLK; 2013 unsigned int i; 2014 2015 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2016 snd_pcm_suspend_all(chip->pcm); 2017 2018 snd_ac97_suspend(chip->ac97); 2019 snd_ac97_suspend(chip->ac97_secondary); 2020 2021 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2022 ulCLK |= CLKCR1_CKRA; 2023 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2024 2025 /* Disable interrupts. */ 2026 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM); 2027 2028 /* remember the status registers */ 2029 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 2030 if (saved_regs[i]) 2031 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]); 2032 2033 /* Turn off the serial ports. */ 2034 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); 2035 2036 /* Power off FM, Joystick, AC link, */ 2037 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); 2038 2039 /* DLL off. */ 2040 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 2041 2042 /* AC link off. */ 2043 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); 2044 2045 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2046 ulCLK &= ~CLKCR1_CKRA; 2047 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2048 2049 pci_disable_device(pci); 2050 pci_save_state(pci); 2051 pci_set_power_state(pci, pci_choose_state(pci, state)); 2052 return 0; 2053} 2054 2055static int cs4281_resume(struct pci_dev *pci) 2056{ 2057 struct snd_card *card = pci_get_drvdata(pci); 2058 struct cs4281 *chip = card->private_data; 2059 unsigned int i; 2060 u32 ulCLK; 2061 2062 pci_set_power_state(pci, PCI_D0); 2063 pci_restore_state(pci); 2064 if (pci_enable_device(pci) < 0) { 2065 printk(KERN_ERR "cs4281: pci_enable_device failed, " 2066 "disabling device\n"); 2067 snd_card_disconnect(card); 2068 return -EIO; 2069 } 2070 pci_set_master(pci); 2071 2072 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2073 ulCLK |= CLKCR1_CKRA; 2074 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2075 2076 snd_cs4281_chip_init(chip); 2077 2078 /* restore the status registers */ 2079 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 2080 if (saved_regs[i]) 2081 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]); 2082 2083 snd_ac97_resume(chip->ac97); 2084 snd_ac97_resume(chip->ac97_secondary); 2085 2086 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2087 ulCLK &= ~CLKCR1_CKRA; 2088 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2089 2090 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2091 return 0; 2092} 2093#endif /* CONFIG_PM */ 2094 2095static struct pci_driver driver = { 2096 .name = "CS4281", 2097 .id_table = snd_cs4281_ids, 2098 .probe = snd_cs4281_probe, 2099 .remove = __devexit_p(snd_cs4281_remove), 2100#ifdef CONFIG_PM 2101 .suspend = cs4281_suspend, 2102 .resume = cs4281_resume, 2103#endif 2104}; 2105 2106static int __init alsa_card_cs4281_init(void) 2107{ 2108 return pci_register_driver(&driver); 2109} 2110 2111static void __exit alsa_card_cs4281_exit(void) 2112{ 2113 pci_unregister_driver(&driver); 2114} 2115 2116module_init(alsa_card_cs4281_init) 2117module_exit(alsa_card_cs4281_exit) 2118