1 2 3#include <sound/driver.h> 4#include <asm/io.h> 5#include <linux/init.h> 6#include <linux/pci.h> 7#include <linux/delay.h> 8#include <linux/slab.h> 9#include <linux/gameport.h> 10#include <linux/moduleparam.h> 11#include <linux/dma-mapping.h> 12#include <sound/core.h> 13#include <sound/control.h> 14#include <sound/pcm.h> 15#include <sound/rawmidi.h> 16#include <sound/mpu401.h> 17#include <sound/opl3.h> 18#include <sound/initval.h> 19#include "azt3328.h" 20 21MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>"); 22MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)"); 23MODULE_LICENSE("GPL"); 24MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}"); 25 26#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 27#define SUPPORT_JOYSTICK 1 28#endif 29 30#define DEBUG_MISC 0 31#define DEBUG_CALLS 0 32#define DEBUG_MIXER 0 33#define DEBUG_PLAY_REC 0 34#define DEBUG_IO 0 35#define DEBUG_TIMER 0 36#define MIXER_TESTING 0 37 38#if DEBUG_MISC 39#define snd_azf3328_dbgmisc(format, args...) printk(KERN_ERR format, ##args) 40#else 41#define snd_azf3328_dbgmisc(format, args...) 42#endif 43 44#if DEBUG_CALLS 45#define snd_azf3328_dbgcalls(format, args...) printk(format, ##args) 46#define snd_azf3328_dbgcallenter() printk(KERN_ERR "--> %s\n", __FUNCTION__) 47#define snd_azf3328_dbgcallleave() printk(KERN_ERR "<-- %s\n", __FUNCTION__) 48#else 49#define snd_azf3328_dbgcalls(format, args...) 50#define snd_azf3328_dbgcallenter() 51#define snd_azf3328_dbgcallleave() 52#endif 53 54#if DEBUG_MIXER 55#define snd_azf3328_dbgmixer(format, args...) printk(format, ##args) 56#else 57#define snd_azf3328_dbgmixer(format, args...) 58#endif 59 60#if DEBUG_PLAY_REC 61#define snd_azf3328_dbgplay(format, args...) printk(KERN_ERR format, ##args) 62#else 63#define snd_azf3328_dbgplay(format, args...) 64#endif 65 66#if DEBUG_MISC 67#define snd_azf3328_dbgtimer(format, args...) printk(KERN_ERR format, ##args) 68#else 69#define snd_azf3328_dbgtimer(format, args...) 70#endif 71 72static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 73module_param_array(index, int, NULL, 0444); 74MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard."); 75 76static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 77module_param_array(id, charp, NULL, 0444); 78MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard."); 79 80static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 81module_param_array(enable, bool, NULL, 0444); 82MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard."); 83 84#ifdef SUPPORT_JOYSTICK 85static int joystick[SNDRV_CARDS]; 86module_param_array(joystick, bool, NULL, 0444); 87MODULE_PARM_DESC(joystick, "Enable joystick for AZF3328 soundcard."); 88#endif 89 90static int seqtimer_scaling = 128; 91module_param(seqtimer_scaling, int, 0444); 92MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128."); 93 94struct snd_azf3328 { 95 /* often-used fields towards beginning, then grouped */ 96 unsigned long codec_port; 97 unsigned long io2_port; 98 unsigned long mpu_port; 99 unsigned long synth_port; 100 unsigned long mixer_port; 101 102 spinlock_t reg_lock; 103 104 struct snd_timer *timer; 105 106 struct snd_pcm *pcm; 107 struct snd_pcm_substream *playback_substream; 108 struct snd_pcm_substream *capture_substream; 109 unsigned int is_playing; 110 unsigned int is_recording; 111 112 struct snd_card *card; 113 struct snd_rawmidi *rmidi; 114 115#ifdef SUPPORT_JOYSTICK 116 struct gameport *gameport; 117#endif 118 119 struct pci_dev *pci; 120 int irq; 121 122#ifdef CONFIG_PM 123 /* register value containers for power management 124 * Note: not always full I/O range preserved (just like Win driver!) */ 125 u16 saved_regs_codec [AZF_IO_SIZE_CODEC_PM / 2]; 126 u16 saved_regs_io2 [AZF_IO_SIZE_IO2_PM / 2]; 127 u16 saved_regs_mpu [AZF_IO_SIZE_MPU_PM / 2]; 128 u16 saved_regs_synth[AZF_IO_SIZE_SYNTH_PM / 2]; 129 u16 saved_regs_mixer[AZF_IO_SIZE_MIXER_PM / 2]; 130#endif 131}; 132 133static const struct pci_device_id snd_azf3328_ids[] = { 134 { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */ 135 { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */ 136 { 0, } 137}; 138 139MODULE_DEVICE_TABLE(pci, snd_azf3328_ids); 140 141static inline void 142snd_azf3328_codec_outb(const struct snd_azf3328 *chip, int reg, u8 value) 143{ 144 outb(value, chip->codec_port + reg); 145} 146 147static inline u8 148snd_azf3328_codec_inb(const struct snd_azf3328 *chip, int reg) 149{ 150 return inb(chip->codec_port + reg); 151} 152 153static inline void 154snd_azf3328_codec_outw(const struct snd_azf3328 *chip, int reg, u16 value) 155{ 156 outw(value, chip->codec_port + reg); 157} 158 159static inline u16 160snd_azf3328_codec_inw(const struct snd_azf3328 *chip, int reg) 161{ 162 return inw(chip->codec_port + reg); 163} 164 165static inline void 166snd_azf3328_codec_outl(const struct snd_azf3328 *chip, int reg, u32 value) 167{ 168 outl(value, chip->codec_port + reg); 169} 170 171static inline void 172snd_azf3328_io2_outb(const struct snd_azf3328 *chip, int reg, u8 value) 173{ 174 outb(value, chip->io2_port + reg); 175} 176 177static inline u8 178snd_azf3328_io2_inb(const struct snd_azf3328 *chip, int reg) 179{ 180 return inb(chip->io2_port + reg); 181} 182 183static inline void 184snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, int reg, u16 value) 185{ 186 outw(value, chip->mixer_port + reg); 187} 188 189static inline u16 190snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, int reg) 191{ 192 return inw(chip->mixer_port + reg); 193} 194 195static void 196snd_azf3328_mixer_set_mute(const struct snd_azf3328 *chip, int reg, int do_mute) 197{ 198 unsigned long portbase = chip->mixer_port + reg + 1; 199 unsigned char oldval; 200 201 /* the mute bit is on the *second* (i.e. right) register of a 202 * left/right channel setting */ 203 oldval = inb(portbase); 204 if (do_mute) 205 oldval |= 0x80; 206 else 207 oldval &= ~0x80; 208 outb(oldval, portbase); 209} 210 211static void 212snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip, int reg, unsigned char dst_vol_left, unsigned char dst_vol_right, int chan_sel, int delay) 213{ 214 unsigned long portbase = chip->mixer_port + reg; 215 unsigned char curr_vol_left = 0, curr_vol_right = 0; 216 int left_done = 0, right_done = 0; 217 218 snd_azf3328_dbgcallenter(); 219 if (chan_sel & SET_CHAN_LEFT) 220 curr_vol_left = inb(portbase + 1); 221 else 222 left_done = 1; 223 if (chan_sel & SET_CHAN_RIGHT) 224 curr_vol_right = inb(portbase + 0); 225 else 226 right_done = 1; 227 228 /* take care of muting flag (0x80) contained in left channel */ 229 if (curr_vol_left & 0x80) 230 dst_vol_left |= 0x80; 231 else 232 dst_vol_left &= ~0x80; 233 234 do { 235 if (!left_done) { 236 if (curr_vol_left > dst_vol_left) 237 curr_vol_left--; 238 else 239 if (curr_vol_left < dst_vol_left) 240 curr_vol_left++; 241 else 242 left_done = 1; 243 outb(curr_vol_left, portbase + 1); 244 } 245 if (!right_done) { 246 if (curr_vol_right > dst_vol_right) 247 curr_vol_right--; 248 else 249 if (curr_vol_right < dst_vol_right) 250 curr_vol_right++; 251 else 252 right_done = 1; 253 /* during volume change, the right channel is crackling 254 * somewhat more than the left channel, unfortunately. 255 * This seems to be a hardware issue. */ 256 outb(curr_vol_right, portbase + 0); 257 } 258 if (delay) 259 mdelay(delay); 260 } while ((!left_done) || (!right_done)); 261 snd_azf3328_dbgcallleave(); 262} 263 264/* 265 * general mixer element 266 */ 267struct azf3328_mixer_reg { 268 unsigned int reg; 269 unsigned int lchan_shift, rchan_shift; 270 unsigned int mask; 271 unsigned int invert: 1; 272 unsigned int stereo: 1; 273 unsigned int enum_c: 4; 274}; 275 276#define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \ 277 ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \ 278 (mask << 16) | \ 279 (invert << 24) | \ 280 (stereo << 25) | \ 281 (enum_c << 26)) 282 283static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val) 284{ 285 r->reg = val & 0xff; 286 r->lchan_shift = (val >> 8) & 0x0f; 287 r->rchan_shift = (val >> 12) & 0x0f; 288 r->mask = (val >> 16) & 0xff; 289 r->invert = (val >> 24) & 1; 290 r->stereo = (val >> 25) & 1; 291 r->enum_c = (val >> 26) & 0x0f; 292} 293 294/* 295 * mixer switches/volumes 296 */ 297 298#define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \ 299{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 300 .info = snd_azf3328_info_mixer, \ 301 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 302 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \ 303} 304 305#define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \ 306{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 307 .info = snd_azf3328_info_mixer, \ 308 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 309 .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \ 310} 311 312#define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \ 313{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 314 .info = snd_azf3328_info_mixer, \ 315 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 316 .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \ 317} 318 319#define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \ 320{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 321 .info = snd_azf3328_info_mixer, \ 322 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 323 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \ 324} 325 326#define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \ 327{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 328 .info = snd_azf3328_info_mixer_enum, \ 329 .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \ 330 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \ 331} 332 333static int 334snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol, 335 struct snd_ctl_elem_info *uinfo) 336{ 337 struct azf3328_mixer_reg reg; 338 339 snd_azf3328_dbgcallenter(); 340 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 341 uinfo->type = reg.mask == 1 ? 342 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 343 uinfo->count = reg.stereo + 1; 344 uinfo->value.integer.min = 0; 345 uinfo->value.integer.max = reg.mask; 346 snd_azf3328_dbgcallleave(); 347 return 0; 348} 349 350static int 351snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol, 352 struct snd_ctl_elem_value *ucontrol) 353{ 354 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 355 struct azf3328_mixer_reg reg; 356 unsigned int oreg, val; 357 358 snd_azf3328_dbgcallenter(); 359 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 360 361 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 362 val = (oreg >> reg.lchan_shift) & reg.mask; 363 if (reg.invert) 364 val = reg.mask - val; 365 ucontrol->value.integer.value[0] = val; 366 if (reg.stereo) { 367 val = (oreg >> reg.rchan_shift) & reg.mask; 368 if (reg.invert) 369 val = reg.mask - val; 370 ucontrol->value.integer.value[1] = val; 371 } 372 snd_azf3328_dbgmixer("get: %02x is %04x -> vol %02lx|%02lx " 373 "(shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n", 374 reg.reg, oreg, 375 ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], 376 reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo); 377 snd_azf3328_dbgcallleave(); 378 return 0; 379} 380 381static int 382snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol, 383 struct snd_ctl_elem_value *ucontrol) 384{ 385 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 386 struct azf3328_mixer_reg reg; 387 unsigned int oreg, nreg, val; 388 389 snd_azf3328_dbgcallenter(); 390 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 391 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 392 val = ucontrol->value.integer.value[0] & reg.mask; 393 if (reg.invert) 394 val = reg.mask - val; 395 nreg = oreg & ~(reg.mask << reg.lchan_shift); 396 nreg |= (val << reg.lchan_shift); 397 if (reg.stereo) { 398 val = ucontrol->value.integer.value[1] & reg.mask; 399 if (reg.invert) 400 val = reg.mask - val; 401 nreg &= ~(reg.mask << reg.rchan_shift); 402 nreg |= (val << reg.rchan_shift); 403 } 404 if (reg.mask >= 0x07) /* it's a volume control, so better take care */ 405 snd_azf3328_mixer_write_volume_gradually( 406 chip, reg.reg, nreg >> 8, nreg & 0xff, 407 /* just set both channels, doesn't matter */ 408 SET_CHAN_LEFT|SET_CHAN_RIGHT, 409 0); 410 else 411 snd_azf3328_mixer_outw(chip, reg.reg, nreg); 412 413 snd_azf3328_dbgmixer("put: %02x to %02lx|%02lx, " 414 "oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n", 415 reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], 416 oreg, reg.lchan_shift, reg.rchan_shift, 417 nreg, snd_azf3328_mixer_inw(chip, reg.reg)); 418 snd_azf3328_dbgcallleave(); 419 return (nreg != oreg); 420} 421 422static int 423snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol, 424 struct snd_ctl_elem_info *uinfo) 425{ 426 static const char * const texts1[] = { 427 "Mic1", "Mic2" 428 }; 429 static const char * const texts2[] = { 430 "Mix", "Mic" 431 }; 432 static const char * const texts3[] = { 433 "Mic", "CD", "Video", "Aux", 434 "Line", "Mix", "Mix Mono", "Phone" 435 }; 436 static const char * const texts4[] = { 437 "pre 3D", "post 3D" 438 }; 439 struct azf3328_mixer_reg reg; 440 441 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 442 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 443 uinfo->count = (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1; 444 uinfo->value.enumerated.items = reg.enum_c; 445 if (uinfo->value.enumerated.item > reg.enum_c - 1U) 446 uinfo->value.enumerated.item = reg.enum_c - 1U; 447 if (reg.reg == IDX_MIXER_ADVCTL2) { 448 switch(reg.lchan_shift) { 449 case 8: /* modem out sel */ 450 strcpy(uinfo->value.enumerated.name, texts1[uinfo->value.enumerated.item]); 451 break; 452 case 9: /* mono sel source */ 453 strcpy(uinfo->value.enumerated.name, texts2[uinfo->value.enumerated.item]); 454 break; 455 case 15: /* PCM Out Path */ 456 strcpy(uinfo->value.enumerated.name, texts4[uinfo->value.enumerated.item]); 457 break; 458 } 459 } else 460 strcpy(uinfo->value.enumerated.name, texts3[uinfo->value.enumerated.item] 461); 462 return 0; 463} 464 465static int 466snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol, 467 struct snd_ctl_elem_value *ucontrol) 468{ 469 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 470 struct azf3328_mixer_reg reg; 471 unsigned short val; 472 473 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 474 val = snd_azf3328_mixer_inw(chip, reg.reg); 475 if (reg.reg == IDX_MIXER_REC_SELECT) { 476 ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1); 477 ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1); 478 } else 479 ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1); 480 481 snd_azf3328_dbgmixer("get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n", 482 reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1], 483 reg.lchan_shift, reg.enum_c); 484 return 0; 485} 486 487static int 488snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol, 489 struct snd_ctl_elem_value *ucontrol) 490{ 491 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 492 struct azf3328_mixer_reg reg; 493 unsigned int oreg, nreg, val; 494 495 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 496 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 497 val = oreg; 498 if (reg.reg == IDX_MIXER_REC_SELECT) { 499 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U || 500 ucontrol->value.enumerated.item[1] > reg.enum_c - 1U) 501 return -EINVAL; 502 val = (ucontrol->value.enumerated.item[0] << 8) | 503 (ucontrol->value.enumerated.item[1] << 0); 504 } else { 505 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U) 506 return -EINVAL; 507 val &= ~((reg.enum_c - 1) << reg.lchan_shift); 508 val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift); 509 } 510 snd_azf3328_mixer_outw(chip, reg.reg, val); 511 nreg = val; 512 513 snd_azf3328_dbgmixer("put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg); 514 return (nreg != oreg); 515} 516 517static struct snd_kcontrol_new snd_azf3328_mixer_controls[] __devinitdata = { 518 AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1), 519 AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1), 520 AZF3328_MIXER_SWITCH("Wave Playback Switch", IDX_MIXER_WAVEOUT, 15, 1), 521 AZF3328_MIXER_VOL_STEREO("Wave Playback Volume", IDX_MIXER_WAVEOUT, 0x1f, 1), 522 AZF3328_MIXER_SWITCH("Wave 3D Bypass Playback Switch", IDX_MIXER_ADVCTL2, 7, 1), 523 AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1), 524 AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1), 525 AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1), 526 AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1), 527 AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1), 528 AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0), 529 AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0), 530 AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1), 531 AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1), 532 AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0), 533 AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1), 534 AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1), 535 AZF3328_MIXER_SWITCH("PC Speaker Playback Switch", IDX_MIXER_PCBEEP, 15, 1), 536 AZF3328_MIXER_VOL_SPECIAL("PC Speaker Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1), 537 AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1), 538 AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1), 539 AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1), 540 AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1), 541 AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1), 542 AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1), 543 AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1), 544 AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1), 545 AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8), 546 AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9), 547 AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */ 548 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0), 549 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0), 550 AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0), 551 AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */ 552 AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */ 553#if MIXER_TESTING 554 AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0), 555 AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0), 556 AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0), 557 AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0), 558 AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0), 559 AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0), 560 AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0), 561 AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0), 562 AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0), 563 AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0), 564 AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0), 565 AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0), 566 AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0), 567 AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0), 568 AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0), 569 AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0), 570#endif 571}; 572 573static u16 __devinitdata snd_azf3328_init_values[][2] = { 574 { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f }, 575 { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f }, 576 { IDX_MIXER_BASSTREBLE, 0x0000 }, 577 { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f }, 578 { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f }, 579 { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f }, 580 { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f }, 581 { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f }, 582 { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f }, 583 { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f }, 584 { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f }, 585 { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f }, 586 { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 }, 587}; 588 589static int __devinit 590snd_azf3328_mixer_new(struct snd_azf3328 *chip) 591{ 592 struct snd_card *card; 593 const struct snd_kcontrol_new *sw; 594 unsigned int idx; 595 int err; 596 597 snd_azf3328_dbgcallenter(); 598 snd_assert(chip != NULL && chip->card != NULL, return -EINVAL); 599 600 card = chip->card; 601 602 /* mixer reset */ 603 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); 604 605 /* mute and zero volume channels */ 606 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); idx++) { 607 snd_azf3328_mixer_outw(chip, 608 snd_azf3328_init_values[idx][0], 609 snd_azf3328_init_values[idx][1]); 610 } 611 612 /* add mixer controls */ 613 sw = snd_azf3328_mixer_controls; 614 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls); idx++, sw++) { 615 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0) 616 return err; 617 } 618 snd_component_add(card, "AZF3328 mixer"); 619 strcpy(card->mixername, "AZF3328 mixer"); 620 621 snd_azf3328_dbgcallleave(); 622 return 0; 623} 624 625static int 626snd_azf3328_hw_params(struct snd_pcm_substream *substream, 627 struct snd_pcm_hw_params *hw_params) 628{ 629 int res; 630 snd_azf3328_dbgcallenter(); 631 res = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 632 snd_azf3328_dbgcallleave(); 633 return res; 634} 635 636static int 637snd_azf3328_hw_free(struct snd_pcm_substream *substream) 638{ 639 snd_azf3328_dbgcallenter(); 640 snd_pcm_lib_free_pages(substream); 641 snd_azf3328_dbgcallleave(); 642 return 0; 643} 644 645static void 646snd_azf3328_setfmt(struct snd_azf3328 *chip, 647 unsigned int reg, 648 unsigned int bitrate, 649 unsigned int format_width, 650 unsigned int channels 651) 652{ 653 u16 val = 0xff00; 654 unsigned long flags; 655 656 snd_azf3328_dbgcallenter(); 657 switch (bitrate) { 658 case 4000: val |= SOUNDFORMAT_FREQ_SUSPECTED_4000; break; 659 case 4800: val |= SOUNDFORMAT_FREQ_SUSPECTED_4800; break; 660 case 5512: val |= SOUNDFORMAT_FREQ_5510; break; /* the AZF3328 names it "5510" for some strange reason */ 661 case 6620: val |= SOUNDFORMAT_FREQ_6620; break; 662 case 8000: val |= SOUNDFORMAT_FREQ_8000; break; 663 case 9600: val |= SOUNDFORMAT_FREQ_9600; break; 664 case 11025: val |= SOUNDFORMAT_FREQ_11025; break; 665 case 13240: val |= SOUNDFORMAT_FREQ_SUSPECTED_13240; break; 666 case 16000: val |= SOUNDFORMAT_FREQ_16000; break; 667 case 22050: val |= SOUNDFORMAT_FREQ_22050; break; 668 case 32000: val |= SOUNDFORMAT_FREQ_32000; break; 669 case 44100: val |= SOUNDFORMAT_FREQ_44100; break; 670 case 48000: val |= SOUNDFORMAT_FREQ_48000; break; 671 case 66200: val |= SOUNDFORMAT_FREQ_SUSPECTED_66200; break; 672 default: 673 snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate); 674 val |= SOUNDFORMAT_FREQ_44100; 675 break; 676 } 677 /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */ 678 /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */ 679 /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */ 680 /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */ 681 /* val = 0xff05; 5m11.556s (... -> 44100Hz) */ 682 /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */ 683 /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */ 684 /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */ 685 /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */ 686 687 if (channels == 2) 688 val |= SOUNDFORMAT_FLAG_2CHANNELS; 689 690 if (format_width == 16) 691 val |= SOUNDFORMAT_FLAG_16BIT; 692 693 spin_lock_irqsave(&chip->reg_lock, flags); 694 695 /* set bitrate/format */ 696 snd_azf3328_codec_outw(chip, reg, val); 697 698 if (reg == IDX_IO_PLAY_SOUNDFORMAT) /* only do it for playback */ 699 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, 700 snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) | 701 DMA_PLAY_SOMETHING1 | 702 DMA_PLAY_SOMETHING2 | 703 SOMETHING_ALMOST_ALWAYS_SET | 704 DMA_EPILOGUE_SOMETHING | 705 DMA_SOMETHING_ELSE 706 ); 707 708 spin_unlock_irqrestore(&chip->reg_lock, flags); 709 snd_azf3328_dbgcallleave(); 710} 711 712static void 713snd_azf3328_setdmaa(struct snd_azf3328 *chip, 714 long unsigned int addr, 715 unsigned int count, 716 unsigned int size, 717 int do_recording) 718{ 719 unsigned long flags, portbase; 720 unsigned int is_running; 721 722 snd_azf3328_dbgcallenter(); 723 if (do_recording) { 724 /* access capture registers, i.e. skip playback reg section */ 725 portbase = chip->codec_port + 0x20; 726 is_running = chip->is_recording; 727 } else { 728 /* access the playback register section */ 729 portbase = chip->codec_port + 0x00; 730 is_running = chip->is_playing; 731 } 732 733 /* AZF3328 uses a two buffer pointer DMA playback approach */ 734 if (!is_running) { 735 unsigned long addr_area2; 736 unsigned long count_areas, count_tmp; /* width 32bit -- overflow!! */ 737 count_areas = size/2; 738 addr_area2 = addr+count_areas; 739 count_areas--; /* max. index */ 740 snd_azf3328_dbgplay("set DMA: buf1 %08lx[%lu], buf2 %08lx[%lu]\n", addr, count_areas, addr_area2, count_areas); 741 742 /* build combined I/O buffer length word */ 743 count_tmp = count_areas; 744 count_areas |= (count_tmp << 16); 745 spin_lock_irqsave(&chip->reg_lock, flags); 746 outl(addr, portbase + IDX_IO_PLAY_DMA_START_1); 747 outl(addr_area2, portbase + IDX_IO_PLAY_DMA_START_2); 748 outl(count_areas, portbase + IDX_IO_PLAY_DMA_LEN_1); 749 spin_unlock_irqrestore(&chip->reg_lock, flags); 750 } 751 snd_azf3328_dbgcallleave(); 752} 753 754static int 755snd_azf3328_playback_prepare(struct snd_pcm_substream *substream) 756{ 757 758 snd_azf3328_dbgcallenter(); 759 snd_azf3328_dbgcallleave(); 760 return 0; 761} 762 763static int 764snd_azf3328_capture_prepare(struct snd_pcm_substream *substream) 765{ 766 767 snd_azf3328_dbgcallenter(); 768 snd_azf3328_dbgcallleave(); 769 return 0; 770} 771 772static int 773snd_azf3328_playback_trigger(struct snd_pcm_substream *substream, int cmd) 774{ 775 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 776 struct snd_pcm_runtime *runtime = substream->runtime; 777 int result = 0; 778 unsigned int status1; 779 780 snd_azf3328_dbgcalls("snd_azf3328_playback_trigger cmd %d\n", cmd); 781 782 switch (cmd) { 783 case SNDRV_PCM_TRIGGER_START: 784 snd_azf3328_dbgplay("START PLAYBACK\n"); 785 786 /* mute WaveOut */ 787 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1); 788 789 snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT, 790 runtime->rate, 791 snd_pcm_format_width(runtime->format), 792 runtime->channels); 793 794 spin_lock(&chip->reg_lock); 795 /* stop playback */ 796 status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS); 797 status1 &= ~DMA_RESUME; 798 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1); 799 800 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_IRQTYPE, 0xffff); 801 spin_unlock(&chip->reg_lock); 802 803 snd_azf3328_setdmaa(chip, runtime->dma_addr, 804 snd_pcm_lib_period_bytes(substream), 805 snd_pcm_lib_buffer_bytes(substream), 806 0); 807 808 spin_lock(&chip->reg_lock); 809#ifdef WIN9X 810 status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2; 811 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1); 812 813 /* start playback again */ 814 status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING; 815 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1); 816#else /* NT4 */ 817 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, 818 0x0000); 819 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, 820 DMA_PLAY_SOMETHING1); 821 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, 822 DMA_PLAY_SOMETHING1 | 823 DMA_PLAY_SOMETHING2); 824 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, 825 DMA_RESUME | 826 SOMETHING_ALMOST_ALWAYS_SET | 827 DMA_EPILOGUE_SOMETHING | 828 DMA_SOMETHING_ELSE); 829#endif 830 spin_unlock(&chip->reg_lock); 831 832 /* now unmute WaveOut */ 833 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0); 834 835 chip->is_playing = 1; 836 snd_azf3328_dbgplay("STARTED PLAYBACK\n"); 837 break; 838 case SNDRV_PCM_TRIGGER_RESUME: 839 snd_azf3328_dbgplay("RESUME PLAYBACK\n"); 840 /* resume playback if we were active */ 841 if (chip->is_playing) 842 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, 843 snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) | DMA_RESUME); 844 break; 845 case SNDRV_PCM_TRIGGER_STOP: 846 snd_azf3328_dbgplay("STOP PLAYBACK\n"); 847 848 /* mute WaveOut */ 849 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1); 850 851 spin_lock(&chip->reg_lock); 852 /* stop playback */ 853 status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS); 854 855 status1 &= ~DMA_RESUME; 856 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1); 857 858 /* hmm, is this really required? we're resetting the same bit 859 * immediately thereafter... */ 860 status1 |= DMA_PLAY_SOMETHING1; 861 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1); 862 863 status1 &= ~DMA_PLAY_SOMETHING1; 864 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1); 865 spin_unlock(&chip->reg_lock); 866 867 /* now unmute WaveOut */ 868 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0); 869 chip->is_playing = 0; 870 snd_azf3328_dbgplay("STOPPED PLAYBACK\n"); 871 break; 872 case SNDRV_PCM_TRIGGER_SUSPEND: 873 snd_azf3328_dbgplay("SUSPEND PLAYBACK\n"); 874 /* make sure playback is stopped */ 875 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, 876 snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) & ~DMA_RESUME); 877 break; 878 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 879 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n"); 880 break; 881 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 882 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n"); 883 break; 884 default: 885 printk(KERN_ERR "FIXME: unknown trigger mode!\n"); 886 return -EINVAL; 887 } 888 889 snd_azf3328_dbgcallleave(); 890 return result; 891} 892 893/* this is just analogous to playback; I'm not quite sure whether recording 894 * should actually be triggered like that */ 895static int 896snd_azf3328_capture_trigger(struct snd_pcm_substream *substream, int cmd) 897{ 898 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 899 struct snd_pcm_runtime *runtime = substream->runtime; 900 int result = 0; 901 unsigned int status1; 902 903 snd_azf3328_dbgcalls("snd_azf3328_capture_trigger cmd %d\n", cmd); 904 905 switch (cmd) { 906 case SNDRV_PCM_TRIGGER_START: 907 908 snd_azf3328_dbgplay("START CAPTURE\n"); 909 910 snd_azf3328_setfmt(chip, IDX_IO_REC_SOUNDFORMAT, 911 runtime->rate, 912 snd_pcm_format_width(runtime->format), 913 runtime->channels); 914 915 spin_lock(&chip->reg_lock); 916 /* stop recording */ 917 status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS); 918 status1 &= ~DMA_RESUME; 919 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1); 920 921 snd_azf3328_codec_outw(chip, IDX_IO_REC_IRQTYPE, 0xffff); 922 spin_unlock(&chip->reg_lock); 923 924 snd_azf3328_setdmaa(chip, runtime->dma_addr, 925 snd_pcm_lib_period_bytes(substream), 926 snd_pcm_lib_buffer_bytes(substream), 927 1); 928 929 spin_lock(&chip->reg_lock); 930#ifdef WIN9X 931 status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2; 932 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1); 933 934 /* start capture again */ 935 status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING; 936 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1); 937#else 938 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, 939 0x0000); 940 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, 941 DMA_PLAY_SOMETHING1); 942 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, 943 DMA_PLAY_SOMETHING1 | 944 DMA_PLAY_SOMETHING2); 945 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, 946 DMA_RESUME | 947 SOMETHING_ALMOST_ALWAYS_SET | 948 DMA_EPILOGUE_SOMETHING | 949 DMA_SOMETHING_ELSE); 950#endif 951 spin_unlock(&chip->reg_lock); 952 953 chip->is_recording = 1; 954 snd_azf3328_dbgplay("STARTED CAPTURE\n"); 955 break; 956 case SNDRV_PCM_TRIGGER_RESUME: 957 snd_azf3328_dbgplay("RESUME CAPTURE\n"); 958 /* resume recording if we were active */ 959 if (chip->is_recording) 960 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, 961 snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) | DMA_RESUME); 962 break; 963 case SNDRV_PCM_TRIGGER_STOP: 964 snd_azf3328_dbgplay("STOP CAPTURE\n"); 965 966 spin_lock(&chip->reg_lock); 967 /* stop recording */ 968 status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS); 969 970 status1 &= ~DMA_RESUME; 971 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1); 972 973 status1 |= DMA_PLAY_SOMETHING1; 974 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1); 975 976 status1 &= ~DMA_PLAY_SOMETHING1; 977 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1); 978 spin_unlock(&chip->reg_lock); 979 980 chip->is_recording = 0; 981 snd_azf3328_dbgplay("STOPPED CAPTURE\n"); 982 break; 983 case SNDRV_PCM_TRIGGER_SUSPEND: 984 snd_azf3328_dbgplay("SUSPEND CAPTURE\n"); 985 /* make sure recording is stopped */ 986 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, 987 snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) & ~DMA_RESUME); 988 break; 989 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 990 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n"); 991 break; 992 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 993 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n"); 994 break; 995 default: 996 printk(KERN_ERR "FIXME: unknown trigger mode!\n"); 997 return -EINVAL; 998 } 999 1000 snd_azf3328_dbgcallleave(); 1001 return result; 1002} 1003 1004static snd_pcm_uframes_t 1005snd_azf3328_playback_pointer(struct snd_pcm_substream *substream) 1006{ 1007 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 1008 unsigned long bufptr, result; 1009 snd_pcm_uframes_t frmres; 1010 1011#ifdef QUERY_HARDWARE 1012 bufptr = inl(chip->codec_port+IDX_IO_PLAY_DMA_START_1); 1013#else 1014 bufptr = substream->runtime->dma_addr; 1015#endif 1016 result = inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS); 1017 1018 /* calculate offset */ 1019 result -= bufptr; 1020 frmres = bytes_to_frames( substream->runtime, result); 1021 snd_azf3328_dbgplay("PLAY @ 0x%8lx, frames %8ld\n", result, frmres); 1022 return frmres; 1023} 1024 1025static snd_pcm_uframes_t 1026snd_azf3328_capture_pointer(struct snd_pcm_substream *substream) 1027{ 1028 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 1029 unsigned long bufptr, result; 1030 snd_pcm_uframes_t frmres; 1031 1032#ifdef QUERY_HARDWARE 1033 bufptr = inl(chip->codec_port+IDX_IO_REC_DMA_START_1); 1034#else 1035 bufptr = substream->runtime->dma_addr; 1036#endif 1037 result = inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS); 1038 1039 /* calculate offset */ 1040 result -= bufptr; 1041 frmres = bytes_to_frames( substream->runtime, result); 1042 snd_azf3328_dbgplay("REC @ 0x%8lx, frames %8ld\n", result, frmres); 1043 return frmres; 1044} 1045 1046static irqreturn_t 1047snd_azf3328_interrupt(int irq, void *dev_id) 1048{ 1049 struct snd_azf3328 *chip = dev_id; 1050 u8 status, which; 1051 static unsigned long irq_count; 1052 1053 status = snd_azf3328_codec_inb(chip, IDX_IO_IRQSTATUS); 1054 1055 /* fast path out, to ease interrupt sharing */ 1056 if (!(status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_MPU401|IRQ_TIMER))) 1057 return IRQ_NONE; /* must be interrupt for another device */ 1058 1059 snd_azf3328_dbgplay("Interrupt %ld!\nIDX_IO_PLAY_FLAGS %04x, IDX_IO_PLAY_IRQTYPE %04x, IDX_IO_IRQSTATUS %04x\n", 1060 irq_count, 1061 snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS), 1062 snd_azf3328_codec_inw(chip, IDX_IO_PLAY_IRQTYPE), 1063 status); 1064 1065 if (status & IRQ_TIMER) { 1066 /* snd_azf3328_dbgplay("timer %ld\n", inl(chip->codec_port+IDX_IO_TIMER_VALUE) & TIMER_VALUE_MASK); */ 1067 if (chip->timer) 1068 snd_timer_interrupt(chip->timer, chip->timer->sticks); 1069 /* ACK timer */ 1070 spin_lock(&chip->reg_lock); 1071 snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07); 1072 spin_unlock(&chip->reg_lock); 1073 snd_azf3328_dbgplay("azt3328: timer IRQ\n"); 1074 } 1075 if (status & IRQ_PLAYBACK) { 1076 spin_lock(&chip->reg_lock); 1077 which = snd_azf3328_codec_inb(chip, IDX_IO_PLAY_IRQTYPE); 1078 /* ack all IRQ types immediately */ 1079 snd_azf3328_codec_outb(chip, IDX_IO_PLAY_IRQTYPE, which); 1080 spin_unlock(&chip->reg_lock); 1081 1082 if (chip->pcm && chip->playback_substream) { 1083 snd_pcm_period_elapsed(chip->playback_substream); 1084 snd_azf3328_dbgplay("PLAY period done (#%x), @ %x\n", 1085 which, 1086 inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS)); 1087 } else 1088 snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n"); 1089 if (which & IRQ_PLAY_SOMETHING) 1090 snd_azf3328_dbgplay("azt3328: unknown play IRQ type occurred, please report!\n"); 1091 } 1092 if (status & IRQ_RECORDING) { 1093 spin_lock(&chip->reg_lock); 1094 which = snd_azf3328_codec_inb(chip, IDX_IO_REC_IRQTYPE); 1095 /* ack all IRQ types immediately */ 1096 snd_azf3328_codec_outb(chip, IDX_IO_REC_IRQTYPE, which); 1097 spin_unlock(&chip->reg_lock); 1098 1099 if (chip->pcm && chip->capture_substream) { 1100 snd_pcm_period_elapsed(chip->capture_substream); 1101 snd_azf3328_dbgplay("REC period done (#%x), @ %x\n", 1102 which, 1103 inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS)); 1104 } else 1105 snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n"); 1106 if (which & IRQ_REC_SOMETHING) 1107 snd_azf3328_dbgplay("azt3328: unknown rec IRQ type occurred, please report!\n"); 1108 } 1109 /* MPU401 has less critical IRQ requirements 1110 * than timer and playback/recording, right? */ 1111 if (status & IRQ_MPU401) { 1112 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); 1113 1114 /* hmm, do we have to ack the IRQ here somehow? 1115 * If so, then I don't know how... */ 1116 snd_azf3328_dbgplay("azt3328: MPU401 IRQ\n"); 1117 } 1118 irq_count++; 1119 return IRQ_HANDLED; 1120} 1121 1122/*****************************************************************/ 1123 1124static const struct snd_pcm_hardware snd_azf3328_playback = 1125{ 1126 .info = SNDRV_PCM_INFO_MMAP | 1127 SNDRV_PCM_INFO_INTERLEAVED | 1128 SNDRV_PCM_INFO_MMAP_VALID, 1129 .formats = SNDRV_PCM_FMTBIT_S8 | 1130 SNDRV_PCM_FMTBIT_U8 | 1131 SNDRV_PCM_FMTBIT_S16_LE | 1132 SNDRV_PCM_FMTBIT_U16_LE, 1133 .rates = SNDRV_PCM_RATE_5512 | 1134 SNDRV_PCM_RATE_8000_48000 | 1135 SNDRV_PCM_RATE_KNOT, 1136 .rate_min = 4000, 1137 .rate_max = 66200, 1138 .channels_min = 1, 1139 .channels_max = 2, 1140 .buffer_bytes_max = 65536, 1141 .period_bytes_min = 64, 1142 .period_bytes_max = 65536, 1143 .periods_min = 1, 1144 .periods_max = 1024, 1145 .fifo_size = 0, 1146}; 1147 1148static const struct snd_pcm_hardware snd_azf3328_capture = 1149{ 1150 .info = SNDRV_PCM_INFO_MMAP | 1151 SNDRV_PCM_INFO_INTERLEAVED | 1152 SNDRV_PCM_INFO_MMAP_VALID, 1153 .formats = SNDRV_PCM_FMTBIT_S8 | 1154 SNDRV_PCM_FMTBIT_U8 | 1155 SNDRV_PCM_FMTBIT_S16_LE | 1156 SNDRV_PCM_FMTBIT_U16_LE, 1157 .rates = SNDRV_PCM_RATE_5512 | 1158 SNDRV_PCM_RATE_8000_48000 | 1159 SNDRV_PCM_RATE_KNOT, 1160 .rate_min = 4000, 1161 .rate_max = 66200, 1162 .channels_min = 1, 1163 .channels_max = 2, 1164 .buffer_bytes_max = 65536, 1165 .period_bytes_min = 64, 1166 .period_bytes_max = 65536, 1167 .periods_min = 1, 1168 .periods_max = 1024, 1169 .fifo_size = 0, 1170}; 1171 1172 1173static unsigned int snd_azf3328_fixed_rates[] = { 1174 4000, 4800, 5512, 6620, 8000, 9600, 11025, 13240, 16000, 22050, 32000, 1175 44100, 48000, 66200 }; 1176static struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = { 1177 .count = ARRAY_SIZE(snd_azf3328_fixed_rates), 1178 .list = snd_azf3328_fixed_rates, 1179 .mask = 0, 1180}; 1181 1182/*****************************************************************/ 1183 1184static int 1185snd_azf3328_playback_open(struct snd_pcm_substream *substream) 1186{ 1187 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 1188 struct snd_pcm_runtime *runtime = substream->runtime; 1189 1190 snd_azf3328_dbgcallenter(); 1191 chip->playback_substream = substream; 1192 runtime->hw = snd_azf3328_playback; 1193 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1194 &snd_azf3328_hw_constraints_rates); 1195 snd_azf3328_dbgcallleave(); 1196 return 0; 1197} 1198 1199static int 1200snd_azf3328_capture_open(struct snd_pcm_substream *substream) 1201{ 1202 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 1203 struct snd_pcm_runtime *runtime = substream->runtime; 1204 1205 snd_azf3328_dbgcallenter(); 1206 chip->capture_substream = substream; 1207 runtime->hw = snd_azf3328_capture; 1208 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1209 &snd_azf3328_hw_constraints_rates); 1210 snd_azf3328_dbgcallleave(); 1211 return 0; 1212} 1213 1214static int 1215snd_azf3328_playback_close(struct snd_pcm_substream *substream) 1216{ 1217 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 1218 1219 snd_azf3328_dbgcallenter(); 1220 chip->playback_substream = NULL; 1221 snd_azf3328_dbgcallleave(); 1222 return 0; 1223} 1224 1225static int 1226snd_azf3328_capture_close(struct snd_pcm_substream *substream) 1227{ 1228 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 1229 1230 snd_azf3328_dbgcallenter(); 1231 chip->capture_substream = NULL; 1232 snd_azf3328_dbgcallleave(); 1233 return 0; 1234} 1235 1236/******************************************************************/ 1237 1238static struct snd_pcm_ops snd_azf3328_playback_ops = { 1239 .open = snd_azf3328_playback_open, 1240 .close = snd_azf3328_playback_close, 1241 .ioctl = snd_pcm_lib_ioctl, 1242 .hw_params = snd_azf3328_hw_params, 1243 .hw_free = snd_azf3328_hw_free, 1244 .prepare = snd_azf3328_playback_prepare, 1245 .trigger = snd_azf3328_playback_trigger, 1246 .pointer = snd_azf3328_playback_pointer 1247}; 1248 1249static struct snd_pcm_ops snd_azf3328_capture_ops = { 1250 .open = snd_azf3328_capture_open, 1251 .close = snd_azf3328_capture_close, 1252 .ioctl = snd_pcm_lib_ioctl, 1253 .hw_params = snd_azf3328_hw_params, 1254 .hw_free = snd_azf3328_hw_free, 1255 .prepare = snd_azf3328_capture_prepare, 1256 .trigger = snd_azf3328_capture_trigger, 1257 .pointer = snd_azf3328_capture_pointer 1258}; 1259 1260static int __devinit 1261snd_azf3328_pcm(struct snd_azf3328 *chip, int device) 1262{ 1263 struct snd_pcm *pcm; 1264 int err; 1265 1266 snd_azf3328_dbgcallenter(); 1267 if ((err = snd_pcm_new(chip->card, "AZF3328 DSP", device, 1, 1, &pcm)) < 0) 1268 return err; 1269 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_azf3328_playback_ops); 1270 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_azf3328_capture_ops); 1271 1272 pcm->private_data = chip; 1273 pcm->info_flags = 0; 1274 strcpy(pcm->name, chip->card->shortname); 1275 chip->pcm = pcm; 1276 1277 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1278 snd_dma_pci_data(chip->pci), 64*1024, 64*1024); 1279 1280 snd_azf3328_dbgcallleave(); 1281 return 0; 1282} 1283 1284/******************************************************************/ 1285 1286#ifdef SUPPORT_JOYSTICK 1287static int __devinit 1288snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev) 1289{ 1290 struct gameport *gp; 1291 struct resource *r; 1292 1293 if (!joystick[dev]) 1294 return -ENODEV; 1295 1296 if (!(r = request_region(0x200, 8, "AZF3328 gameport"))) { 1297 printk(KERN_WARNING "azt3328: cannot reserve joystick ports\n"); 1298 return -EBUSY; 1299 } 1300 1301 chip->gameport = gp = gameport_allocate_port(); 1302 if (!gp) { 1303 printk(KERN_ERR "azt3328: cannot allocate memory for gameport\n"); 1304 release_and_free_resource(r); 1305 return -ENOMEM; 1306 } 1307 1308 gameport_set_name(gp, "AZF3328 Gameport"); 1309 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 1310 gameport_set_dev_parent(gp, &chip->pci->dev); 1311 gp->io = 0x200; 1312 gameport_set_port_data(gp, r); 1313 1314 snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR, 1315 snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) | LEGACY_JOY); 1316 1317 gameport_register_port(chip->gameport); 1318 1319 return 0; 1320} 1321 1322static void 1323snd_azf3328_free_joystick(struct snd_azf3328 *chip) 1324{ 1325 if (chip->gameport) { 1326 struct resource *r = gameport_get_port_data(chip->gameport); 1327 1328 gameport_unregister_port(chip->gameport); 1329 chip->gameport = NULL; 1330 /* disable gameport */ 1331 snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR, 1332 snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY); 1333 release_and_free_resource(r); 1334 } 1335} 1336#else 1337static inline int 1338snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev) { return -ENOSYS; } 1339static inline void 1340snd_azf3328_free_joystick(struct snd_azf3328 *chip) { } 1341#endif 1342 1343/******************************************************************/ 1344 1345static int 1346snd_azf3328_free(struct snd_azf3328 *chip) 1347{ 1348 if (chip->irq < 0) 1349 goto __end_hw; 1350 1351 /* reset (close) mixer */ 1352 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1); /* first mute master volume */ 1353 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); 1354 1355 /* well, at least we know how to disable the timer IRQ */ 1356 snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00); 1357 1358 synchronize_irq(chip->irq); 1359__end_hw: 1360 snd_azf3328_free_joystick(chip); 1361 if (chip->irq >= 0) 1362 free_irq(chip->irq, chip); 1363 pci_release_regions(chip->pci); 1364 pci_disable_device(chip->pci); 1365 1366 kfree(chip); 1367 return 0; 1368} 1369 1370static int 1371snd_azf3328_dev_free(struct snd_device *device) 1372{ 1373 struct snd_azf3328 *chip = device->device_data; 1374 return snd_azf3328_free(chip); 1375} 1376 1377/******************************************************************/ 1378 1379/*** NOTE: the physical timer resolution actually is 1024000 ticks per second, 1380 *** but announcing those attributes to user-space would make programs 1381 *** configure the timer to a 1 tick value, resulting in an absolutely fatal 1382 *** timer IRQ storm. 1383 *** Thus I chose to announce a down-scaled virtual timer to the outside and 1384 *** calculate real timer countdown values internally. 1385 *** (the scale factor can be set via module parameter "seqtimer_scaling"). 1386 ***/ 1387 1388static int 1389snd_azf3328_timer_start(struct snd_timer *timer) 1390{ 1391 struct snd_azf3328 *chip; 1392 unsigned long flags; 1393 unsigned int delay; 1394 1395 snd_azf3328_dbgcallenter(); 1396 chip = snd_timer_chip(timer); 1397 delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK; 1398 if (delay < 49) { 1399 /* uhoh, that's not good, since user-space won't know about 1400 * this timing tweak 1401 * (we need to do it to avoid a lockup, though) */ 1402 1403 snd_azf3328_dbgtimer("delay was too low (%d)!\n", delay); 1404 delay = 49; /* minimum time is 49 ticks */ 1405 } 1406 snd_azf3328_dbgtimer("setting timer countdown value %d, add COUNTDOWN|IRQ\n", delay); 1407 delay |= TIMER_ENABLE_COUNTDOWN | TIMER_ENABLE_IRQ; 1408 spin_lock_irqsave(&chip->reg_lock, flags); 1409 snd_azf3328_codec_outl(chip, IDX_IO_TIMER_VALUE, delay); 1410 spin_unlock_irqrestore(&chip->reg_lock, flags); 1411 snd_azf3328_dbgcallleave(); 1412 return 0; 1413} 1414 1415static int 1416snd_azf3328_timer_stop(struct snd_timer *timer) 1417{ 1418 struct snd_azf3328 *chip; 1419 unsigned long flags; 1420 1421 snd_azf3328_dbgcallenter(); 1422 chip = snd_timer_chip(timer); 1423 spin_lock_irqsave(&chip->reg_lock, flags); 1424 /* disable timer countdown and interrupt */ 1425 snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0); 1426 spin_unlock_irqrestore(&chip->reg_lock, flags); 1427 snd_azf3328_dbgcallleave(); 1428 return 0; 1429} 1430 1431 1432static int 1433snd_azf3328_timer_precise_resolution(struct snd_timer *timer, 1434 unsigned long *num, unsigned long *den) 1435{ 1436 snd_azf3328_dbgcallenter(); 1437 *num = 1; 1438 *den = 1024000 / seqtimer_scaling; 1439 snd_azf3328_dbgcallleave(); 1440 return 0; 1441} 1442 1443static struct snd_timer_hardware snd_azf3328_timer_hw = { 1444 .flags = SNDRV_TIMER_HW_AUTO, 1445 .resolution = 977, /* 1000000/1024000 = 0.9765625us */ 1446 .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */ 1447 .start = snd_azf3328_timer_start, 1448 .stop = snd_azf3328_timer_stop, 1449 .precise_resolution = snd_azf3328_timer_precise_resolution, 1450}; 1451 1452static int __devinit 1453snd_azf3328_timer(struct snd_azf3328 *chip, int device) 1454{ 1455 struct snd_timer *timer = NULL; 1456 struct snd_timer_id tid; 1457 int err; 1458 1459 snd_azf3328_dbgcallenter(); 1460 tid.dev_class = SNDRV_TIMER_CLASS_CARD; 1461 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE; 1462 tid.card = chip->card->number; 1463 tid.device = device; 1464 tid.subdevice = 0; 1465 1466 snd_azf3328_timer_hw.resolution *= seqtimer_scaling; 1467 snd_azf3328_timer_hw.ticks /= seqtimer_scaling; 1468 if ((err = snd_timer_new(chip->card, "AZF3328", &tid, &timer)) < 0) { 1469 goto out; 1470 } 1471 1472 strcpy(timer->name, "AZF3328 timer"); 1473 timer->private_data = chip; 1474 timer->hw = snd_azf3328_timer_hw; 1475 1476 chip->timer = timer; 1477 1478 err = 0; 1479 1480out: 1481 snd_azf3328_dbgcallleave(); 1482 return err; 1483} 1484 1485/******************************************************************/ 1486 1487 1488#if DEBUG_MISC 1489static void 1490snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip) 1491{ 1492 u16 tmp; 1493 1494 snd_azf3328_dbgmisc("codec_port 0x%lx, io2_port 0x%lx, mpu_port 0x%lx, synth_port 0x%lx, mixer_port 0x%lx, irq %d\n", chip->codec_port, chip->io2_port, chip->mpu_port, chip->synth_port, chip->mixer_port, chip->irq); 1495 1496 snd_azf3328_dbgmisc("io2 %02x %02x %02x %02x %02x %02x\n", snd_azf3328_io2_inb(chip, 0), snd_azf3328_io2_inb(chip, 1), snd_azf3328_io2_inb(chip, 2), snd_azf3328_io2_inb(chip, 3), snd_azf3328_io2_inb(chip, 4), snd_azf3328_io2_inb(chip, 5)); 1497 1498 for (tmp=0; tmp <= 0x01; tmp += 1) 1499 snd_azf3328_dbgmisc("0x%02x: opl 0x%04x, mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, mpu330 0x%04x\n", tmp, inb(0x388 + tmp), inb(0x300 + tmp), inb(0x310 + tmp), inb(0x320 + tmp), inb(0x330 + tmp)); 1500 1501 for (tmp = 0; tmp < AZF_IO_SIZE_CODEC; tmp += 2) 1502 snd_azf3328_dbgmisc("codec 0x%02x: 0x%04x\n", tmp, snd_azf3328_codec_inw(chip, tmp)); 1503 1504 for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2) 1505 snd_azf3328_dbgmisc("mixer 0x%02x: 0x%04x\n", tmp, snd_azf3328_mixer_inw(chip, tmp)); 1506} 1507#else 1508static inline void 1509snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip) {} 1510#endif 1511 1512static int __devinit 1513snd_azf3328_create(struct snd_card *card, 1514 struct pci_dev *pci, 1515 unsigned long device_type, 1516 struct snd_azf3328 ** rchip) 1517{ 1518 struct snd_azf3328 *chip; 1519 int err; 1520 static struct snd_device_ops ops = { 1521 .dev_free = snd_azf3328_dev_free, 1522 }; 1523 u16 tmp; 1524 1525 *rchip = NULL; 1526 1527 if ((err = pci_enable_device(pci)) < 0) 1528 return err; 1529 1530 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1531 if (chip == NULL) { 1532 err = -ENOMEM; 1533 goto out_err; 1534 } 1535 spin_lock_init(&chip->reg_lock); 1536 chip->card = card; 1537 chip->pci = pci; 1538 chip->irq = -1; 1539 1540 /* check if we can restrict PCI DMA transfers to 24 bits */ 1541 if (pci_set_dma_mask(pci, DMA_24BIT_MASK) < 0 || 1542 pci_set_consistent_dma_mask(pci, DMA_24BIT_MASK) < 0) { 1543 snd_printk(KERN_ERR "architecture does not support 24bit PCI busmaster DMA\n"); 1544 err = -ENXIO; 1545 goto out_err; 1546 } 1547 1548 if ((err = pci_request_regions(pci, "Aztech AZF3328")) < 0) { 1549 goto out_err; 1550 } 1551 1552 chip->codec_port = pci_resource_start(pci, 0); 1553 chip->io2_port = pci_resource_start(pci, 1); 1554 chip->mpu_port = pci_resource_start(pci, 2); 1555 chip->synth_port = pci_resource_start(pci, 3); 1556 chip->mixer_port = pci_resource_start(pci, 4); 1557 1558 if (request_irq(pci->irq, snd_azf3328_interrupt, 1559 IRQF_SHARED, card->shortname, chip)) { 1560 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 1561 err = -EBUSY; 1562 goto out_err; 1563 } 1564 chip->irq = pci->irq; 1565 pci_set_master(pci); 1566 synchronize_irq(chip->irq); 1567 1568 snd_azf3328_debug_show_ports(chip); 1569 1570 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1571 goto out_err; 1572 } 1573 1574 /* create mixer interface & switches */ 1575 if ((err = snd_azf3328_mixer_new(chip)) < 0) 1576 goto out_err; 1577 1578 1579 /* standard chip init stuff */ 1580 /* default IRQ init value */ 1581 tmp = DMA_PLAY_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE; 1582 1583 spin_lock_irq(&chip->reg_lock); 1584 snd_azf3328_codec_outb(chip, IDX_IO_PLAY_FLAGS, tmp); 1585 snd_azf3328_codec_outb(chip, IDX_IO_REC_FLAGS, tmp); 1586 snd_azf3328_codec_outb(chip, IDX_IO_SOMETHING_FLAGS, tmp); 1587 snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00); /* disable timer */ 1588 spin_unlock_irq(&chip->reg_lock); 1589 1590 snd_card_set_dev(card, &pci->dev); 1591 1592 *rchip = chip; 1593 1594 err = 0; 1595 goto out; 1596 1597out_err: 1598 if (chip) 1599 snd_azf3328_free(chip); 1600 pci_disable_device(pci); 1601 1602out: 1603 return err; 1604} 1605 1606static int __devinit 1607snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1608{ 1609 static int dev; 1610 struct snd_card *card; 1611 struct snd_azf3328 *chip; 1612 struct snd_opl3 *opl3; 1613 int err; 1614 1615 snd_azf3328_dbgcallenter(); 1616 if (dev >= SNDRV_CARDS) 1617 return -ENODEV; 1618 if (!enable[dev]) { 1619 dev++; 1620 return -ENOENT; 1621 } 1622 1623 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0 ); 1624 if (card == NULL) 1625 return -ENOMEM; 1626 1627 strcpy(card->driver, "AZF3328"); 1628 strcpy(card->shortname, "Aztech AZF3328 (PCI168)"); 1629 1630 if ((err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip)) < 0) { 1631 goto out_err; 1632 } 1633 1634 card->private_data = chip; 1635 1636 if ((err = snd_mpu401_uart_new( card, 0, MPU401_HW_MPU401, 1637 chip->mpu_port, MPU401_INFO_INTEGRATED, 1638 pci->irq, 0, &chip->rmidi)) < 0) { 1639 snd_printk(KERN_ERR "azf3328: no MPU-401 device at 0x%lx?\n", chip->mpu_port); 1640 goto out_err; 1641 } 1642 1643 if ((err = snd_azf3328_timer(chip, 0)) < 0) { 1644 goto out_err; 1645 } 1646 1647 if ((err = snd_azf3328_pcm(chip, 0)) < 0) { 1648 goto out_err; 1649 } 1650 1651 if (snd_opl3_create(card, chip->synth_port, chip->synth_port+2, 1652 OPL3_HW_AUTO, 1, &opl3) < 0) { 1653 snd_printk(KERN_ERR "azf3328: no OPL3 device at 0x%lx-0x%lx?\n", 1654 chip->synth_port, chip->synth_port+2 ); 1655 } else { 1656 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) { 1657 goto out_err; 1658 } 1659 } 1660 1661 opl3->private_data = chip; 1662 1663 sprintf(card->longname, "%s at 0x%lx, irq %i", 1664 card->shortname, chip->codec_port, chip->irq); 1665 1666 if ((err = snd_card_register(card)) < 0) { 1667 goto out_err; 1668 } 1669 1670#ifdef MODULE 1671 printk( 1672"azt3328: Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n" 1673"azt3328: Hardware was completely undocumented, unfortunately.\n" 1674"azt3328: Feel free to contact andi AT lisas.de for bug reports etc.!\n" 1675"azt3328: User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n", 1676 1024000 / seqtimer_scaling, seqtimer_scaling); 1677#endif 1678 1679 if (snd_azf3328_config_joystick(chip, dev) < 0) 1680 snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR, 1681 snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY); 1682 1683 pci_set_drvdata(pci, card); 1684 dev++; 1685 1686 err = 0; 1687 goto out; 1688 1689out_err: 1690 snd_card_free(card); 1691 1692out: 1693 snd_azf3328_dbgcallleave(); 1694 return err; 1695} 1696 1697static void __devexit 1698snd_azf3328_remove(struct pci_dev *pci) 1699{ 1700 snd_azf3328_dbgcallenter(); 1701 snd_card_free(pci_get_drvdata(pci)); 1702 pci_set_drvdata(pci, NULL); 1703 snd_azf3328_dbgcallleave(); 1704} 1705 1706#ifdef CONFIG_PM 1707static int 1708snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state) 1709{ 1710 struct snd_card *card = pci_get_drvdata(pci); 1711 struct snd_azf3328 *chip = card->private_data; 1712 int reg; 1713 1714 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1715 1716 snd_pcm_suspend_all(chip->pcm); 1717 1718 for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; reg++) 1719 chip->saved_regs_mixer[reg] = inw(chip->mixer_port + reg * 2); 1720 1721 /* make sure to disable master volume etc. to prevent looping sound */ 1722 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1); 1723 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1); 1724 1725 for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; reg++) 1726 chip->saved_regs_codec[reg] = inw(chip->codec_port + reg * 2); 1727 for (reg = 0; reg < AZF_IO_SIZE_IO2_PM / 2; reg++) 1728 chip->saved_regs_io2[reg] = inw(chip->io2_port + reg * 2); 1729 for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; reg++) 1730 chip->saved_regs_mpu[reg] = inw(chip->mpu_port + reg * 2); 1731 for (reg = 0; reg < AZF_IO_SIZE_SYNTH_PM / 2; reg++) 1732 chip->saved_regs_synth[reg] = inw(chip->synth_port + reg * 2); 1733 1734 pci_disable_device(pci); 1735 pci_save_state(pci); 1736 pci_set_power_state(pci, pci_choose_state(pci, state)); 1737 return 0; 1738} 1739 1740static int 1741snd_azf3328_resume(struct pci_dev *pci) 1742{ 1743 struct snd_card *card = pci_get_drvdata(pci); 1744 struct snd_azf3328 *chip = card->private_data; 1745 int reg; 1746 1747 pci_set_power_state(pci, PCI_D0); 1748 pci_restore_state(pci); 1749 if (pci_enable_device(pci) < 0) { 1750 printk(KERN_ERR "azt3328: pci_enable_device failed, " 1751 "disabling device\n"); 1752 snd_card_disconnect(card); 1753 return -EIO; 1754 } 1755 pci_set_master(pci); 1756 1757 for (reg = 0; reg < AZF_IO_SIZE_IO2_PM / 2; reg++) 1758 outw(chip->saved_regs_io2[reg], chip->io2_port + reg * 2); 1759 for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; reg++) 1760 outw(chip->saved_regs_mpu[reg], chip->mpu_port + reg * 2); 1761 for (reg = 0; reg < AZF_IO_SIZE_SYNTH_PM / 2; reg++) 1762 outw(chip->saved_regs_synth[reg], chip->synth_port + reg * 2); 1763 for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; reg++) 1764 outw(chip->saved_regs_mixer[reg], chip->mixer_port + reg * 2); 1765 for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; reg++) 1766 outw(chip->saved_regs_codec[reg], chip->codec_port + reg * 2); 1767 1768 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1769 return 0; 1770} 1771#endif 1772 1773 1774 1775 1776static struct pci_driver driver = { 1777 .name = "AZF3328", 1778 .id_table = snd_azf3328_ids, 1779 .probe = snd_azf3328_probe, 1780 .remove = __devexit_p(snd_azf3328_remove), 1781#ifdef CONFIG_PM 1782 .suspend = snd_azf3328_suspend, 1783 .resume = snd_azf3328_resume, 1784#endif 1785}; 1786 1787static int __init 1788alsa_card_azf3328_init(void) 1789{ 1790 int err; 1791 snd_azf3328_dbgcallenter(); 1792 err = pci_register_driver(&driver); 1793 snd_azf3328_dbgcallleave(); 1794 return err; 1795} 1796 1797static void __exit 1798alsa_card_azf3328_exit(void) 1799{ 1800 snd_azf3328_dbgcallenter(); 1801 pci_unregister_driver(&driver); 1802 snd_azf3328_dbgcallleave(); 1803} 1804 1805module_init(alsa_card_azf3328_init) 1806module_exit(alsa_card_azf3328_exit) 1807