1/* 2 * Driver for A2 audio system used in SGI machines 3 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org> 4 * 5 * Based on Ulf Carlsson's code. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 * 20 * Supported devices: 21 * /dev/dsp standard dsp device, (mostly) OSS compatible 22 * /dev/mixer standard mixer device, (mostly) OSS compatible 23 * 24 */ 25#include <linux/kernel.h> 26#include <linux/module.h> 27#include <linux/sched.h> 28#include <linux/init.h> 29#include <linux/slab.h> 30#include <linux/poll.h> 31#include <linux/interrupt.h> 32#include <linux/dma-mapping.h> 33#include <linux/sound.h> 34#include <linux/soundcard.h> 35#include <linux/mutex.h> 36 37 38#include <asm/io.h> 39#include <asm/sgi/hpc3.h> 40#include <asm/sgi/ip22.h> 41 42#include "hal2.h" 43 44#define DEBUG(args...) 45 46#define DEBUG_MIX(args...) 47 48/* 49 * Before touching these look how it works. It is a bit unusual I know, 50 * but it helps to keep things simple. This driver is considered complete 51 * and I won't add any new features although hardware has many cool 52 * capabilities. 53 * (Historical note: HAL2 driver was first written by Ulf Carlsson - ALSA 54 * 0.3 running with 2.2.x kernel. Then ALSA changed completely and it 55 * seemed easier to me to write OSS driver from scratch - this one. Now 56 * when ALSA is official part of 2.6 kernel it's time to write ALSA driver 57 * using (hopefully) final version of ALSA interface) 58 */ 59#define H2_BLOCK_SIZE 1024 60#define H2_ADC_BUFSIZE 8192 61#define H2_DAC_BUFSIZE 16834 62 63struct hal2_pbus { 64 struct hpc3_pbus_dmacregs *pbus; 65 int pbusnr; 66 unsigned int ctrl; /* Current state of pbus->pbdma_ctrl */ 67}; 68 69struct hal2_desc { 70 struct hpc_dma_desc desc; 71 u32 cnt; /* don't touch, it is also padding */ 72}; 73 74struct hal2_codec { 75 unsigned char *buffer; 76 struct hal2_desc *desc; 77 int desc_count; 78 int tail, head; /* tail index, head index */ 79 struct hal2_pbus pbus; 80 unsigned int format; /* Audio data format */ 81 int voices; /* mono/stereo */ 82 unsigned int sample_rate; 83 unsigned int master; /* Master frequency */ 84 unsigned short mod; /* MOD value */ 85 unsigned short inc; /* INC value */ 86 87 wait_queue_head_t dma_wait; 88 spinlock_t lock; 89 struct mutex sem; 90 91 int usecount; /* recording and playback are 92 * independent */ 93}; 94 95#define H2_MIX_OUTPUT_ATT 0 96#define H2_MIX_INPUT_GAIN 1 97#define H2_MIXERS 2 98struct hal2_mixer { 99 int modcnt; 100 unsigned int master; 101 unsigned int volume[H2_MIXERS]; 102}; 103 104struct hal2_card { 105 int dev_dsp; /* audio device */ 106 int dev_mixer; /* mixer device */ 107 int dev_midi; /* midi device */ 108 109 struct hal2_ctl_regs *ctl_regs; /* HAL2 ctl registers */ 110 struct hal2_aes_regs *aes_regs; /* HAL2 aes registers */ 111 struct hal2_vol_regs *vol_regs; /* HAL2 vol registers */ 112 struct hal2_syn_regs *syn_regs; /* HAL2 syn registers */ 113 114 struct hal2_codec dac; 115 struct hal2_codec adc; 116 struct hal2_mixer mixer; 117}; 118 119#define H2_INDIRECT_WAIT(regs) while (regs->isr & H2_ISR_TSTATUS); 120 121#define H2_READ_ADDR(addr) (addr | (1<<7)) 122#define H2_WRITE_ADDR(addr) (addr) 123 124static char *hal2str = "HAL2"; 125 126/* 127 * I doubt anyone has a machine with two HAL2 cards. It's possible to 128 * have two HPC's, so it is probably possible to have two HAL2 cards. 129 * Try to deal with it, but note that it is not tested. 130 */ 131#define MAXCARDS 2 132static struct hal2_card* hal2_card[MAXCARDS]; 133 134static const struct { 135 unsigned char idx:4, avail:1; 136} mixtable[SOUND_MIXER_NRDEVICES] = { 137 [SOUND_MIXER_PCM] = { H2_MIX_OUTPUT_ATT, 1 }, /* voice */ 138 [SOUND_MIXER_MIC] = { H2_MIX_INPUT_GAIN, 1 }, /* mic */ 139}; 140 141#define H2_SUPPORTED_FORMATS (AFMT_S16_LE | AFMT_S16_BE) 142 143static inline void hal2_isr_write(struct hal2_card *hal2, u16 val) 144{ 145 hal2->ctl_regs->isr = val; 146} 147 148static inline u16 hal2_isr_look(struct hal2_card *hal2) 149{ 150 return hal2->ctl_regs->isr; 151} 152 153static inline u16 hal2_rev_look(struct hal2_card *hal2) 154{ 155 return hal2->ctl_regs->rev; 156} 157 158#ifdef HAL2_DUMP_REGS 159static u16 hal2_i_look16(struct hal2_card *hal2, u16 addr) 160{ 161 struct hal2_ctl_regs *regs = hal2->ctl_regs; 162 163 regs->iar = H2_READ_ADDR(addr); 164 H2_INDIRECT_WAIT(regs); 165 return regs->idr0; 166} 167#endif 168 169static u32 hal2_i_look32(struct hal2_card *hal2, u16 addr) 170{ 171 u32 ret; 172 struct hal2_ctl_regs *regs = hal2->ctl_regs; 173 174 regs->iar = H2_READ_ADDR(addr); 175 H2_INDIRECT_WAIT(regs); 176 ret = regs->idr0 & 0xffff; 177 regs->iar = H2_READ_ADDR(addr | 0x1); 178 H2_INDIRECT_WAIT(regs); 179 ret |= (regs->idr0 & 0xffff) << 16; 180 return ret; 181} 182 183static void hal2_i_write16(struct hal2_card *hal2, u16 addr, u16 val) 184{ 185 struct hal2_ctl_regs *regs = hal2->ctl_regs; 186 187 regs->idr0 = val; 188 regs->idr1 = 0; 189 regs->idr2 = 0; 190 regs->idr3 = 0; 191 regs->iar = H2_WRITE_ADDR(addr); 192 H2_INDIRECT_WAIT(regs); 193} 194 195static void hal2_i_write32(struct hal2_card *hal2, u16 addr, u32 val) 196{ 197 struct hal2_ctl_regs *regs = hal2->ctl_regs; 198 199 regs->idr0 = val & 0xffff; 200 regs->idr1 = val >> 16; 201 regs->idr2 = 0; 202 regs->idr3 = 0; 203 regs->iar = H2_WRITE_ADDR(addr); 204 H2_INDIRECT_WAIT(regs); 205} 206 207static void hal2_i_setbit16(struct hal2_card *hal2, u16 addr, u16 bit) 208{ 209 struct hal2_ctl_regs *regs = hal2->ctl_regs; 210 211 regs->iar = H2_READ_ADDR(addr); 212 H2_INDIRECT_WAIT(regs); 213 regs->idr0 = (regs->idr0 & 0xffff) | bit; 214 regs->idr1 = 0; 215 regs->idr2 = 0; 216 regs->idr3 = 0; 217 regs->iar = H2_WRITE_ADDR(addr); 218 H2_INDIRECT_WAIT(regs); 219} 220 221static void hal2_i_setbit32(struct hal2_card *hal2, u16 addr, u32 bit) 222{ 223 u32 tmp; 224 struct hal2_ctl_regs *regs = hal2->ctl_regs; 225 226 regs->iar = H2_READ_ADDR(addr); 227 H2_INDIRECT_WAIT(regs); 228 tmp = (regs->idr0 & 0xffff) | (regs->idr1 << 16) | bit; 229 regs->idr0 = tmp & 0xffff; 230 regs->idr1 = tmp >> 16; 231 regs->idr2 = 0; 232 regs->idr3 = 0; 233 regs->iar = H2_WRITE_ADDR(addr); 234 H2_INDIRECT_WAIT(regs); 235} 236 237static void hal2_i_clearbit16(struct hal2_card *hal2, u16 addr, u16 bit) 238{ 239 struct hal2_ctl_regs *regs = hal2->ctl_regs; 240 241 regs->iar = H2_READ_ADDR(addr); 242 H2_INDIRECT_WAIT(regs); 243 regs->idr0 = (regs->idr0 & 0xffff) & ~bit; 244 regs->idr1 = 0; 245 regs->idr2 = 0; 246 regs->idr3 = 0; 247 regs->iar = H2_WRITE_ADDR(addr); 248 H2_INDIRECT_WAIT(regs); 249} 250 251 252#ifdef HAL2_DUMP_REGS 253static void hal2_dump_regs(struct hal2_card *hal2) 254{ 255 DEBUG("isr: %08hx ", hal2_isr_look(hal2)); 256 DEBUG("rev: %08hx\n", hal2_rev_look(hal2)); 257 DEBUG("relay: %04hx\n", hal2_i_look16(hal2, H2I_RELAY_C)); 258 DEBUG("port en: %04hx ", hal2_i_look16(hal2, H2I_DMA_PORT_EN)); 259 DEBUG("dma end: %04hx ", hal2_i_look16(hal2, H2I_DMA_END)); 260 DEBUG("dma drv: %04hx\n", hal2_i_look16(hal2, H2I_DMA_DRV)); 261 DEBUG("syn ctl: %04hx ", hal2_i_look16(hal2, H2I_SYNTH_C)); 262 DEBUG("aesrx ctl: %04hx ", hal2_i_look16(hal2, H2I_AESRX_C)); 263 DEBUG("aestx ctl: %04hx ", hal2_i_look16(hal2, H2I_AESTX_C)); 264 DEBUG("dac ctl1: %04hx ", hal2_i_look16(hal2, H2I_ADC_C1)); 265 DEBUG("dac ctl2: %08x ", hal2_i_look32(hal2, H2I_ADC_C2)); 266 DEBUG("adc ctl1: %04hx ", hal2_i_look16(hal2, H2I_DAC_C1)); 267 DEBUG("adc ctl2: %08x ", hal2_i_look32(hal2, H2I_DAC_C2)); 268 DEBUG("syn map: %04hx\n", hal2_i_look16(hal2, H2I_SYNTH_MAP_C)); 269 DEBUG("bres1 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES1_C1)); 270 DEBUG("bres1 ctl2: %04x ", hal2_i_look32(hal2, H2I_BRES1_C2)); 271 DEBUG("bres2 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES2_C1)); 272 DEBUG("bres2 ctl2: %04x ", hal2_i_look32(hal2, H2I_BRES2_C2)); 273 DEBUG("bres3 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES3_C1)); 274 DEBUG("bres3 ctl2: %04x\n", hal2_i_look32(hal2, H2I_BRES3_C2)); 275} 276#endif 277 278static struct hal2_card* hal2_dsp_find_card(int minor) 279{ 280 int i; 281 282 for (i = 0; i < MAXCARDS; i++) 283 if (hal2_card[i] != NULL && hal2_card[i]->dev_dsp == minor) 284 return hal2_card[i]; 285 return NULL; 286} 287 288static struct hal2_card* hal2_mixer_find_card(int minor) 289{ 290 int i; 291 292 for (i = 0; i < MAXCARDS; i++) 293 if (hal2_card[i] != NULL && hal2_card[i]->dev_mixer == minor) 294 return hal2_card[i]; 295 return NULL; 296} 297 298static void hal2_inc_head(struct hal2_codec *codec) 299{ 300 codec->head++; 301 if (codec->head == codec->desc_count) 302 codec->head = 0; 303} 304 305static void hal2_inc_tail(struct hal2_codec *codec) 306{ 307 codec->tail++; 308 if (codec->tail == codec->desc_count) 309 codec->tail = 0; 310} 311 312static void hal2_dac_interrupt(struct hal2_codec *dac) 313{ 314 int running; 315 316 spin_lock(&dac->lock); 317 /* if tail buffer contains zero samples DMA stream was already 318 * stopped */ 319 running = dac->desc[dac->tail].cnt; 320 dac->desc[dac->tail].cnt = 0; 321 dac->desc[dac->tail].desc.cntinfo = HPCDMA_XIE | HPCDMA_EOX; 322 /* we just proccessed empty buffer, don't update tail pointer */ 323 if (running) 324 hal2_inc_tail(dac); 325 spin_unlock(&dac->lock); 326 327 wake_up(&dac->dma_wait); 328} 329 330static void hal2_adc_interrupt(struct hal2_codec *adc) 331{ 332 int running; 333 334 spin_lock(&adc->lock); 335 /* if head buffer contains nonzero samples DMA stream was already 336 * stopped */ 337 running = !adc->desc[adc->head].cnt; 338 adc->desc[adc->head].cnt = H2_BLOCK_SIZE; 339 adc->desc[adc->head].desc.cntinfo = HPCDMA_XIE | HPCDMA_EOR; 340 /* we just proccessed empty buffer, don't update head pointer */ 341 if (running) 342 hal2_inc_head(adc); 343 spin_unlock(&adc->lock); 344 345 wake_up(&adc->dma_wait); 346} 347 348static irqreturn_t hal2_interrupt(int irq, void *dev_id) 349{ 350 struct hal2_card *hal2 = dev_id; 351 irqreturn_t ret = IRQ_NONE; 352 353 /* decide what caused this interrupt */ 354 if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) { 355 hal2_dac_interrupt(&hal2->dac); 356 ret = IRQ_HANDLED; 357 } 358 if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) { 359 hal2_adc_interrupt(&hal2->adc); 360 ret = IRQ_HANDLED; 361 } 362 return ret; 363} 364 365static int hal2_compute_rate(struct hal2_codec *codec, unsigned int rate) 366{ 367 unsigned short mod; 368 369 DEBUG("rate: %d\n", rate); 370 371 if (rate < 4000) rate = 4000; 372 else if (rate > 48000) rate = 48000; 373 374 if (44100 % rate < 48000 % rate) { 375 mod = 4 * 44100 / rate; 376 codec->master = 44100; 377 } else { 378 mod = 4 * 48000 / rate; 379 codec->master = 48000; 380 } 381 382 codec->inc = 4; 383 codec->mod = mod; 384 rate = 4 * codec->master / mod; 385 386 DEBUG("real_rate: %d\n", rate); 387 388 return rate; 389} 390 391static void hal2_set_dac_rate(struct hal2_card *hal2) 392{ 393 unsigned int master = hal2->dac.master; 394 int inc = hal2->dac.inc; 395 int mod = hal2->dac.mod; 396 397 DEBUG("master: %d inc: %d mod: %d\n", master, inc, mod); 398 399 hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0); 400 hal2_i_write32(hal2, H2I_BRES1_C2, ((0xffff & (inc - mod - 1)) << 16) | inc); 401} 402 403static void hal2_set_adc_rate(struct hal2_card *hal2) 404{ 405 unsigned int master = hal2->adc.master; 406 int inc = hal2->adc.inc; 407 int mod = hal2->adc.mod; 408 409 DEBUG("master: %d inc: %d mod: %d\n", master, inc, mod); 410 411 hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0); 412 hal2_i_write32(hal2, H2I_BRES2_C2, ((0xffff & (inc - mod - 1)) << 16) | inc); 413} 414 415static void hal2_setup_dac(struct hal2_card *hal2) 416{ 417 unsigned int fifobeg, fifoend, highwater, sample_size; 418 struct hal2_pbus *pbus = &hal2->dac.pbus; 419 420 DEBUG("hal2_setup_dac\n"); 421 422 /* Now we set up some PBUS information. The PBUS needs information about 423 * what portion of the fifo it will use. If it's receiving or 424 * transmitting, and finally whether the stream is little endian or big 425 * endian. The information is written later, on the start call. 426 */ 427 sample_size = 2 * hal2->dac.voices; 428 /* Fifo should be set to hold exactly four samples. Highwater mark 429 * should be set to two samples. */ 430 highwater = (sample_size * 2) >> 1; /* halfwords */ 431 fifobeg = 0; /* playback is first */ 432 fifoend = (sample_size * 4) >> 3; /* doublewords */ 433 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD | 434 (highwater << 8) | (fifobeg << 16) | (fifoend << 24) | 435 (hal2->dac.format & AFMT_S16_LE ? HPC3_PDMACTRL_SEL : 0); 436 /* We disable everything before we do anything at all */ 437 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD; 438 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX); 439 /* Setup the HAL2 for playback */ 440 hal2_set_dac_rate(hal2); 441 /* Set endianess */ 442 if (hal2->dac.format & AFMT_S16_LE) 443 hal2_i_setbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX); 444 else 445 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX); 446 /* Set DMA bus */ 447 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr)); 448 /* We are using 1st Bresenham clock generator for playback */ 449 hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT) 450 | (1 << H2I_C1_CLKID_SHIFT) 451 | (hal2->dac.voices << H2I_C1_DATAT_SHIFT)); 452} 453 454static void hal2_setup_adc(struct hal2_card *hal2) 455{ 456 unsigned int fifobeg, fifoend, highwater, sample_size; 457 struct hal2_pbus *pbus = &hal2->adc.pbus; 458 459 DEBUG("hal2_setup_adc\n"); 460 461 sample_size = 2 * hal2->adc.voices; 462 highwater = (sample_size * 2) >> 1; /* halfwords */ 463 fifobeg = (4 * 4) >> 3; /* record is second */ 464 fifoend = (4 * 4 + sample_size * 4) >> 3; /* doublewords */ 465 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD | 466 (highwater << 8) | (fifobeg << 16) | (fifoend << 24) | 467 (hal2->adc.format & AFMT_S16_LE ? HPC3_PDMACTRL_SEL : 0); 468 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD; 469 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR); 470 /* Setup the HAL2 for record */ 471 hal2_set_adc_rate(hal2); 472 /* Set endianess */ 473 if (hal2->adc.format & AFMT_S16_LE) 474 hal2_i_setbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR); 475 else 476 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR); 477 /* Set DMA bus */ 478 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr)); 479 /* We are using 2nd Bresenham clock generator for record */ 480 hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT) 481 | (2 << H2I_C1_CLKID_SHIFT) 482 | (hal2->adc.voices << H2I_C1_DATAT_SHIFT)); 483} 484 485static dma_addr_t hal2_desc_addr(struct hal2_codec *codec, int i) 486{ 487 if (--i < 0) 488 i = codec->desc_count - 1; 489 return codec->desc[i].desc.pnext; 490} 491 492static void hal2_start_dac(struct hal2_card *hal2) 493{ 494 struct hal2_codec *dac = &hal2->dac; 495 struct hal2_pbus *pbus = &dac->pbus; 496 497 pbus->pbus->pbdma_dptr = hal2_desc_addr(dac, dac->tail); 498 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT; 499 /* enable DAC */ 500 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX); 501} 502 503static void hal2_start_adc(struct hal2_card *hal2) 504{ 505 struct hal2_codec *adc = &hal2->adc; 506 struct hal2_pbus *pbus = &adc->pbus; 507 508 pbus->pbus->pbdma_dptr = hal2_desc_addr(adc, adc->head); 509 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT; 510 /* enable ADC */ 511 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR); 512} 513 514static inline void hal2_stop_dac(struct hal2_card *hal2) 515{ 516 hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD; 517 /* The HAL2 itself may remain enabled safely */ 518} 519 520static inline void hal2_stop_adc(struct hal2_card *hal2) 521{ 522 hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD; 523} 524 525static int hal2_alloc_dmabuf(struct hal2_codec *codec, int size, 526 int count, int cntinfo, int dir) 527{ 528 struct hal2_desc *desc, *dma_addr; 529 int i; 530 531 DEBUG("allocating %dk DMA buffer.\n", size / 1024); 532 533 codec->buffer = (unsigned char *)__get_free_pages(GFP_KERNEL | GFP_DMA, 534 get_order(size)); 535 if (!codec->buffer) 536 return -ENOMEM; 537 desc = dma_alloc_coherent(NULL, count * sizeof(struct hal2_desc), 538 (dma_addr_t *)&dma_addr, GFP_KERNEL); 539 if (!desc) { 540 free_pages((unsigned long)codec->buffer, get_order(size)); 541 return -ENOMEM; 542 } 543 codec->desc = desc; 544 for (i = 0; i < count; i++) { 545 desc->desc.pbuf = dma_map_single(NULL, 546 (void *)(codec->buffer + i * H2_BLOCK_SIZE), 547 H2_BLOCK_SIZE, dir); 548 desc->desc.cntinfo = cntinfo; 549 desc->desc.pnext = (i == count - 1) ? 550 (u32)dma_addr : (u32)(dma_addr + i + 1); 551 desc->cnt = 0; 552 desc++; 553 } 554 codec->desc_count = count; 555 codec->head = codec->tail = 0; 556 return 0; 557} 558 559static int hal2_alloc_dac_dmabuf(struct hal2_codec *codec) 560{ 561 return hal2_alloc_dmabuf(codec, H2_DAC_BUFSIZE, 562 H2_DAC_BUFSIZE / H2_BLOCK_SIZE, 563 HPCDMA_XIE | HPCDMA_EOX, 564 DMA_TO_DEVICE); 565} 566 567static int hal2_alloc_adc_dmabuf(struct hal2_codec *codec) 568{ 569 return hal2_alloc_dmabuf(codec, H2_ADC_BUFSIZE, 570 H2_ADC_BUFSIZE / H2_BLOCK_SIZE, 571 HPCDMA_XIE | H2_BLOCK_SIZE, 572 DMA_TO_DEVICE); 573} 574 575static void hal2_free_dmabuf(struct hal2_codec *codec, int size, int dir) 576{ 577 dma_addr_t dma_addr; 578 int i; 579 580 dma_addr = codec->desc[codec->desc_count - 1].desc.pnext; 581 for (i = 0; i < codec->desc_count; i++) 582 dma_unmap_single(NULL, codec->desc[i].desc.pbuf, 583 H2_BLOCK_SIZE, dir); 584 dma_free_coherent(NULL, codec->desc_count * sizeof(struct hal2_desc), 585 (void *)codec->desc, dma_addr); 586 free_pages((unsigned long)codec->buffer, get_order(size)); 587} 588 589static void hal2_free_dac_dmabuf(struct hal2_codec *codec) 590{ 591 return hal2_free_dmabuf(codec, H2_DAC_BUFSIZE, DMA_TO_DEVICE); 592} 593 594static void hal2_free_adc_dmabuf(struct hal2_codec *codec) 595{ 596 return hal2_free_dmabuf(codec, H2_ADC_BUFSIZE, DMA_FROM_DEVICE); 597} 598 599/* 600 * Add 'count' bytes to 'buffer' from DMA ring buffers. Return number of 601 * bytes added or -EFAULT if copy_from_user failed. 602 */ 603static int hal2_get_buffer(struct hal2_card *hal2, char *buffer, int count) 604{ 605 unsigned long flags; 606 int size, ret = 0; 607 unsigned char *buf; 608 struct hal2_desc *tail; 609 struct hal2_codec *adc = &hal2->adc; 610 611 DEBUG("getting %d bytes ", count); 612 613 spin_lock_irqsave(&adc->lock, flags); 614 tail = &adc->desc[adc->tail]; 615 /* enable DMA stream if there are no data */ 616 if (!tail->cnt && !(adc->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT)) 617 hal2_start_adc(hal2); 618 while (tail->cnt > 0 && count > 0) { 619 size = min((int)tail->cnt, count); 620 buf = &adc->buffer[(adc->tail + 1) * H2_BLOCK_SIZE - tail->cnt]; 621 spin_unlock_irqrestore(&adc->lock, flags); 622 dma_sync_single(NULL, tail->desc.pbuf, size, DMA_FROM_DEVICE); 623 if (copy_to_user(buffer, buf, size)) { 624 ret = -EFAULT; 625 goto out; 626 } 627 spin_lock_irqsave(&adc->lock, flags); 628 tail->cnt -= size; 629 /* buffer is empty, update tail pointer */ 630 if (tail->cnt == 0) { 631 tail->desc.cntinfo = HPCDMA_XIE | H2_BLOCK_SIZE; 632 hal2_inc_tail(adc); 633 tail = &adc->desc[adc->tail]; 634 /* enable DMA stream again if needed */ 635 if (!(adc->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT)) 636 hal2_start_adc(hal2); 637 } 638 buffer += size; 639 ret += size; 640 count -= size; 641 642 DEBUG("(%d) ", size); 643 } 644 spin_unlock_irqrestore(&adc->lock, flags); 645out: 646 DEBUG("\n"); 647 648 return ret; 649} 650 651/* 652 * Add 'count' bytes from 'buffer' to DMA ring buffers. Return number of 653 * bytes added or -EFAULT if copy_from_user failed. 654 */ 655static int hal2_add_buffer(struct hal2_card *hal2, char *buffer, int count) 656{ 657 unsigned long flags; 658 unsigned char *buf; 659 int size, ret = 0; 660 struct hal2_desc *head; 661 struct hal2_codec *dac = &hal2->dac; 662 663 DEBUG("adding %d bytes ", count); 664 665 spin_lock_irqsave(&dac->lock, flags); 666 head = &dac->desc[dac->head]; 667 while (head->cnt == 0 && count > 0) { 668 size = min((int)H2_BLOCK_SIZE, count); 669 buf = &dac->buffer[dac->head * H2_BLOCK_SIZE]; 670 spin_unlock_irqrestore(&dac->lock, flags); 671 if (copy_from_user(buf, buffer, size)) { 672 ret = -EFAULT; 673 goto out; 674 } 675 dma_sync_single(NULL, head->desc.pbuf, size, DMA_TO_DEVICE); 676 spin_lock_irqsave(&dac->lock, flags); 677 head->desc.cntinfo = size | HPCDMA_XIE; 678 head->cnt = size; 679 buffer += size; 680 ret += size; 681 count -= size; 682 hal2_inc_head(dac); 683 head = &dac->desc[dac->head]; 684 685 DEBUG("(%d) ", size); 686 } 687 if (!(dac->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT) && ret > 0) 688 hal2_start_dac(hal2); 689 spin_unlock_irqrestore(&dac->lock, flags); 690out: 691 DEBUG("\n"); 692 693 return ret; 694} 695 696#define hal2_reset_dac_pointer(hal2) hal2_reset_pointer(hal2, 1) 697#define hal2_reset_adc_pointer(hal2) hal2_reset_pointer(hal2, 0) 698static void hal2_reset_pointer(struct hal2_card *hal2, int is_dac) 699{ 700 int i; 701 struct hal2_codec *codec = (is_dac) ? &hal2->dac : &hal2->adc; 702 703 DEBUG("hal2_reset_pointer\n"); 704 705 for (i = 0; i < codec->desc_count; i++) { 706 codec->desc[i].cnt = 0; 707 codec->desc[i].desc.cntinfo = HPCDMA_XIE | (is_dac) ? 708 HPCDMA_EOX : H2_BLOCK_SIZE; 709 } 710 codec->head = codec->tail = 0; 711} 712 713static int hal2_sync_dac(struct hal2_card *hal2) 714{ 715 DECLARE_WAITQUEUE(wait, current); 716 struct hal2_codec *dac = &hal2->dac; 717 int ret = 0; 718 unsigned long flags; 719 signed long timeout = 1000 * H2_BLOCK_SIZE * 2 * dac->voices * 720 HZ / dac->sample_rate / 900; 721 722 while (dac->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT) { 723 add_wait_queue(&dac->dma_wait, &wait); 724 set_current_state(TASK_INTERRUPTIBLE); 725 schedule_timeout(timeout); 726 spin_lock_irqsave(&dac->lock, flags); 727 if (dac->desc[dac->tail].cnt) 728 ret = -ETIME; 729 spin_unlock_irqrestore(&dac->lock, flags); 730 if (signal_pending(current)) 731 ret = -ERESTARTSYS; 732 if (ret) { 733 hal2_stop_dac(hal2); 734 hal2_reset_dac_pointer(hal2); 735 } 736 remove_wait_queue(&dac->dma_wait, &wait); 737 } 738 739 return ret; 740} 741 742static int hal2_write_mixer(struct hal2_card *hal2, int index, int vol) 743{ 744 unsigned int l, r, tmp; 745 746 DEBUG_MIX("mixer %d write\n", index); 747 748 if (index >= SOUND_MIXER_NRDEVICES || !mixtable[index].avail) 749 return -EINVAL; 750 751 r = (vol >> 8) & 0xff; 752 if (r > 100) 753 r = 100; 754 l = vol & 0xff; 755 if (l > 100) 756 l = 100; 757 758 hal2->mixer.volume[mixtable[index].idx] = l | (r << 8); 759 760 switch (mixtable[index].idx) { 761 case H2_MIX_OUTPUT_ATT: 762 763 DEBUG_MIX("output attenuator %d,%d\n", l, r); 764 765 if (r | l) { 766 tmp = hal2_i_look32(hal2, H2I_DAC_C2); 767 tmp &= ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE); 768 769 /* Attenuator has five bits */ 770 l = 31 * (100 - l) / 99; 771 r = 31 * (100 - r) / 99; 772 773 DEBUG_MIX("left: %d, right %d\n", l, r); 774 775 tmp |= (l << H2I_C2_L_ATT_SHIFT) & H2I_C2_L_ATT_M; 776 tmp |= (r << H2I_C2_R_ATT_SHIFT) & H2I_C2_R_ATT_M; 777 hal2_i_write32(hal2, H2I_DAC_C2, tmp); 778 } else 779 hal2_i_setbit32(hal2, H2I_DAC_C2, H2I_C2_MUTE); 780 break; 781 case H2_MIX_INPUT_GAIN: 782 783 DEBUG_MIX("input gain %d,%d\n", l, r); 784 785 tmp = hal2_i_look32(hal2, H2I_ADC_C2); 786 tmp &= ~(H2I_C2_L_GAIN_M | H2I_C2_R_GAIN_M); 787 788 /* Gain control has four bits */ 789 l = 16 * l / 100; 790 r = 16 * r / 100; 791 792 DEBUG_MIX("left: %d, right %d\n", l, r); 793 794 tmp |= (l << H2I_C2_L_GAIN_SHIFT) & H2I_C2_L_GAIN_M; 795 tmp |= (r << H2I_C2_R_GAIN_SHIFT) & H2I_C2_R_GAIN_M; 796 hal2_i_write32(hal2, H2I_ADC_C2, tmp); 797 798 break; 799 } 800 801 return 0; 802} 803 804static void hal2_init_mixer(struct hal2_card *hal2) 805{ 806 int i; 807 808 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) 809 if (mixtable[i].avail) 810 hal2->mixer.volume[mixtable[i].idx] = 100 | (100 << 8); 811 812 /* disable attenuator */ 813 hal2_i_write32(hal2, H2I_DAC_C2, 0); 814 /* set max input gain */ 815 hal2_i_write32(hal2, H2I_ADC_C2, H2I_C2_MUTE | 816 (H2I_C2_L_GAIN_M << H2I_C2_L_GAIN_SHIFT) | 817 (H2I_C2_R_GAIN_M << H2I_C2_R_GAIN_SHIFT)); 818 /* set max volume */ 819 hal2->mixer.master = 0xff; 820 hal2->vol_regs->left = 0xff; 821 hal2->vol_regs->right = 0xff; 822} 823 824static void hal2_volume_control(int direction) 825{ 826 unsigned int master = hal2_card[0]->mixer.master; 827 struct hal2_vol_regs *vol = hal2_card[0]->vol_regs; 828 829 /* volume up */ 830 if (direction > 0 && master < 0xff) 831 master++; 832 /* volume down */ 833 else if (direction < 0 && master > 0) 834 master--; 835 /* TODO: mute/unmute */ 836 vol->left = master; 837 vol->right = master; 838 hal2_card[0]->mixer.master = master; 839} 840 841static int hal2_mixer_ioctl(struct hal2_card *hal2, unsigned int cmd, 842 unsigned long arg) 843{ 844 int val; 845 846 if (cmd == SOUND_MIXER_INFO) { 847 mixer_info info; 848 849 memset(&info, 0, sizeof(info)); 850 strlcpy(info.id, hal2str, sizeof(info.id)); 851 strlcpy(info.name, hal2str, sizeof(info.name)); 852 info.modify_counter = hal2->mixer.modcnt; 853 if (copy_to_user((void *)arg, &info, sizeof(info))) 854 return -EFAULT; 855 return 0; 856 } 857 if (cmd == SOUND_OLD_MIXER_INFO) { 858 _old_mixer_info info; 859 860 memset(&info, 0, sizeof(info)); 861 strlcpy(info.id, hal2str, sizeof(info.id)); 862 strlcpy(info.name, hal2str, sizeof(info.name)); 863 if (copy_to_user((void *)arg, &info, sizeof(info))) 864 return -EFAULT; 865 return 0; 866 } 867 if (cmd == OSS_GETVERSION) 868 return put_user(SOUND_VERSION, (int *)arg); 869 870 if (_IOC_TYPE(cmd) != 'M' || _IOC_SIZE(cmd) != sizeof(int)) 871 return -EINVAL; 872 873 if (_IOC_DIR(cmd) == _IOC_READ) { 874 switch (_IOC_NR(cmd)) { 875 /* Give the current record source */ 876 case SOUND_MIXER_RECSRC: 877 val = 0; 878 break; 879 /* Give the supported mixers, all of them support stereo */ 880 case SOUND_MIXER_DEVMASK: 881 case SOUND_MIXER_STEREODEVS: { 882 int i; 883 884 for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++) 885 if (mixtable[i].avail) 886 val |= 1 << i; 887 break; 888 } 889 /* Arg contains a bit for each supported recording source */ 890 case SOUND_MIXER_RECMASK: 891 val = 0; 892 break; 893 case SOUND_MIXER_CAPS: 894 val = 0; 895 break; 896 /* Read a specific mixer */ 897 default: { 898 int i = _IOC_NR(cmd); 899 900 if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].avail) 901 return -EINVAL; 902 val = hal2->mixer.volume[mixtable[i].idx]; 903 break; 904 } 905 } 906 return put_user(val, (int *)arg); 907 } 908 909 if (_IOC_DIR(cmd) != (_IOC_WRITE|_IOC_READ)) 910 return -EINVAL; 911 912 hal2->mixer.modcnt++; 913 914 if (get_user(val, (int *)arg)) 915 return -EFAULT; 916 917 switch (_IOC_NR(cmd)) { 918 /* Arg contains a bit for each recording source */ 919 case SOUND_MIXER_RECSRC: 920 return 0; 921 default: 922 return hal2_write_mixer(hal2, _IOC_NR(cmd), val); 923 } 924 925 return 0; 926} 927 928static int hal2_open_mixdev(struct inode *inode, struct file *file) 929{ 930 struct hal2_card *hal2 = hal2_mixer_find_card(iminor(inode)); 931 932 if (hal2) { 933 file->private_data = hal2; 934 return nonseekable_open(inode, file); 935 } 936 return -ENODEV; 937} 938 939static int hal2_release_mixdev(struct inode *inode, struct file *file) 940{ 941 return 0; 942} 943 944static int hal2_ioctl_mixdev(struct inode *inode, struct file *file, 945 unsigned int cmd, unsigned long arg) 946{ 947 return hal2_mixer_ioctl((struct hal2_card *)file->private_data, cmd, arg); 948} 949 950static int hal2_ioctl(struct inode *inode, struct file *file, 951 unsigned int cmd, unsigned long arg) 952{ 953 int val; 954 struct hal2_card *hal2 = (struct hal2_card *) file->private_data; 955 956 switch (cmd) { 957 case OSS_GETVERSION: 958 return put_user(SOUND_VERSION, (int *)arg); 959 960 case SNDCTL_DSP_SYNC: 961 if (file->f_mode & FMODE_WRITE) 962 return hal2_sync_dac(hal2); 963 return 0; 964 965 case SNDCTL_DSP_SETDUPLEX: 966 return 0; 967 968 case SNDCTL_DSP_GETCAPS: 969 return put_user(DSP_CAP_DUPLEX | DSP_CAP_MULTI, (int *)arg); 970 971 case SNDCTL_DSP_RESET: 972 if (file->f_mode & FMODE_READ) { 973 hal2_stop_adc(hal2); 974 hal2_reset_adc_pointer(hal2); 975 } 976 if (file->f_mode & FMODE_WRITE) { 977 hal2_stop_dac(hal2); 978 hal2_reset_dac_pointer(hal2); 979 } 980 return 0; 981 982 case SNDCTL_DSP_SPEED: 983 if (get_user(val, (int *)arg)) 984 return -EFAULT; 985 if (file->f_mode & FMODE_READ) { 986 hal2_stop_adc(hal2); 987 val = hal2_compute_rate(&hal2->adc, val); 988 hal2->adc.sample_rate = val; 989 hal2_set_adc_rate(hal2); 990 } 991 if (file->f_mode & FMODE_WRITE) { 992 hal2_stop_dac(hal2); 993 val = hal2_compute_rate(&hal2->dac, val); 994 hal2->dac.sample_rate = val; 995 hal2_set_dac_rate(hal2); 996 } 997 return put_user(val, (int *)arg); 998 999 case SNDCTL_DSP_STEREO: 1000 if (get_user(val, (int *)arg)) 1001 return -EFAULT; 1002 if (file->f_mode & FMODE_READ) { 1003 hal2_stop_adc(hal2); 1004 hal2->adc.voices = (val) ? 2 : 1; 1005 hal2_setup_adc(hal2); 1006 } 1007 if (file->f_mode & FMODE_WRITE) { 1008 hal2_stop_dac(hal2); 1009 hal2->dac.voices = (val) ? 2 : 1; 1010 hal2_setup_dac(hal2); 1011 } 1012 return 0; 1013 1014 case SNDCTL_DSP_CHANNELS: 1015 if (get_user(val, (int *)arg)) 1016 return -EFAULT; 1017 if (val != 0) { 1018 if (file->f_mode & FMODE_READ) { 1019 hal2_stop_adc(hal2); 1020 hal2->adc.voices = (val == 1) ? 1 : 2; 1021 hal2_setup_adc(hal2); 1022 } 1023 if (file->f_mode & FMODE_WRITE) { 1024 hal2_stop_dac(hal2); 1025 hal2->dac.voices = (val == 1) ? 1 : 2; 1026 hal2_setup_dac(hal2); 1027 } 1028 } 1029 val = -EINVAL; 1030 if (file->f_mode & FMODE_READ) 1031 val = hal2->adc.voices; 1032 if (file->f_mode & FMODE_WRITE) 1033 val = hal2->dac.voices; 1034 return put_user(val, (int *)arg); 1035 1036 case SNDCTL_DSP_GETFMTS: /* Returns a mask */ 1037 return put_user(H2_SUPPORTED_FORMATS, (int *)arg); 1038 1039 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/ 1040 if (get_user(val, (int *)arg)) 1041 return -EFAULT; 1042 if (val != AFMT_QUERY) { 1043 if (!(val & H2_SUPPORTED_FORMATS)) 1044 return -EINVAL; 1045 if (file->f_mode & FMODE_READ) { 1046 hal2_stop_adc(hal2); 1047 hal2->adc.format = val; 1048 hal2_setup_adc(hal2); 1049 } 1050 if (file->f_mode & FMODE_WRITE) { 1051 hal2_stop_dac(hal2); 1052 hal2->dac.format = val; 1053 hal2_setup_dac(hal2); 1054 } 1055 } else { 1056 val = -EINVAL; 1057 if (file->f_mode & FMODE_READ) 1058 val = hal2->adc.format; 1059 if (file->f_mode & FMODE_WRITE) 1060 val = hal2->dac.format; 1061 } 1062 return put_user(val, (int *)arg); 1063 1064 case SNDCTL_DSP_POST: 1065 return 0; 1066 1067 case SNDCTL_DSP_GETOSPACE: { 1068 audio_buf_info info; 1069 int i; 1070 unsigned long flags; 1071 struct hal2_codec *dac = &hal2->dac; 1072 1073 if (!(file->f_mode & FMODE_WRITE)) 1074 return -EINVAL; 1075 info.fragments = 0; 1076 spin_lock_irqsave(&dac->lock, flags); 1077 for (i = 0; i < dac->desc_count; i++) 1078 if (dac->desc[i].cnt == 0) 1079 info.fragments++; 1080 spin_unlock_irqrestore(&dac->lock, flags); 1081 info.fragstotal = dac->desc_count; 1082 info.fragsize = H2_BLOCK_SIZE; 1083 info.bytes = info.fragsize * info.fragments; 1084 1085 return copy_to_user((void *)arg, &info, sizeof(info)) ? -EFAULT : 0; 1086 } 1087 1088 case SNDCTL_DSP_GETISPACE: { 1089 audio_buf_info info; 1090 int i; 1091 unsigned long flags; 1092 struct hal2_codec *adc = &hal2->adc; 1093 1094 if (!(file->f_mode & FMODE_READ)) 1095 return -EINVAL; 1096 info.fragments = 0; 1097 info.bytes = 0; 1098 spin_lock_irqsave(&adc->lock, flags); 1099 for (i = 0; i < adc->desc_count; i++) 1100 if (adc->desc[i].cnt > 0) { 1101 info.fragments++; 1102 info.bytes += adc->desc[i].cnt; 1103 } 1104 spin_unlock_irqrestore(&adc->lock, flags); 1105 info.fragstotal = adc->desc_count; 1106 info.fragsize = H2_BLOCK_SIZE; 1107 1108 return copy_to_user((void *)arg, &info, sizeof(info)) ? -EFAULT : 0; 1109 } 1110 1111 case SNDCTL_DSP_NONBLOCK: 1112 file->f_flags |= O_NONBLOCK; 1113 return 0; 1114 1115 case SNDCTL_DSP_GETBLKSIZE: 1116 return put_user(H2_BLOCK_SIZE, (int *)arg); 1117 1118 case SNDCTL_DSP_SETFRAGMENT: 1119 return 0; 1120 1121 case SOUND_PCM_READ_RATE: 1122 val = -EINVAL; 1123 if (file->f_mode & FMODE_READ) 1124 val = hal2->adc.sample_rate; 1125 if (file->f_mode & FMODE_WRITE) 1126 val = hal2->dac.sample_rate; 1127 return put_user(val, (int *)arg); 1128 1129 case SOUND_PCM_READ_CHANNELS: 1130 val = -EINVAL; 1131 if (file->f_mode & FMODE_READ) 1132 val = hal2->adc.voices; 1133 if (file->f_mode & FMODE_WRITE) 1134 val = hal2->dac.voices; 1135 return put_user(val, (int *)arg); 1136 1137 case SOUND_PCM_READ_BITS: 1138 return put_user(16, (int *)arg); 1139 } 1140 1141 return hal2_mixer_ioctl(hal2, cmd, arg); 1142} 1143 1144static ssize_t hal2_read(struct file *file, char *buffer, 1145 size_t count, loff_t *ppos) 1146{ 1147 ssize_t err; 1148 struct hal2_card *hal2 = (struct hal2_card *) file->private_data; 1149 struct hal2_codec *adc = &hal2->adc; 1150 1151 if (!count) 1152 return 0; 1153 if (mutex_lock_interruptible(&adc->sem)) 1154 return -EINTR; 1155 if (file->f_flags & O_NONBLOCK) { 1156 err = hal2_get_buffer(hal2, buffer, count); 1157 err = err == 0 ? -EAGAIN : err; 1158 } else { 1159 do { 1160 /* ~10% longer */ 1161 signed long timeout = 1000 * H2_BLOCK_SIZE * 1162 2 * adc->voices * HZ / adc->sample_rate / 900; 1163 unsigned long flags; 1164 DECLARE_WAITQUEUE(wait, current); 1165 ssize_t cnt = 0; 1166 1167 err = hal2_get_buffer(hal2, buffer, count); 1168 if (err > 0) { 1169 count -= err; 1170 cnt += err; 1171 buffer += err; 1172 err = cnt; 1173 } 1174 if (count > 0 && err >= 0) { 1175 add_wait_queue(&adc->dma_wait, &wait); 1176 set_current_state(TASK_INTERRUPTIBLE); 1177 schedule_timeout(timeout); 1178 spin_lock_irqsave(&adc->lock, flags); 1179 if (!adc->desc[adc->tail].cnt) 1180 err = -EAGAIN; 1181 spin_unlock_irqrestore(&adc->lock, flags); 1182 if (signal_pending(current)) 1183 err = -ERESTARTSYS; 1184 remove_wait_queue(&adc->dma_wait, &wait); 1185 if (err < 0) { 1186 hal2_stop_adc(hal2); 1187 hal2_reset_adc_pointer(hal2); 1188 } 1189 } 1190 } while (count > 0 && err >= 0); 1191 } 1192 mutex_unlock(&adc->sem); 1193 1194 return err; 1195} 1196 1197static ssize_t hal2_write(struct file *file, const char *buffer, 1198 size_t count, loff_t *ppos) 1199{ 1200 ssize_t err; 1201 char *buf = (char*) buffer; 1202 struct hal2_card *hal2 = (struct hal2_card *) file->private_data; 1203 struct hal2_codec *dac = &hal2->dac; 1204 1205 if (!count) 1206 return 0; 1207 if (mutex_lock_interruptible(&dac->sem)) 1208 return -EINTR; 1209 if (file->f_flags & O_NONBLOCK) { 1210 err = hal2_add_buffer(hal2, buf, count); 1211 err = err == 0 ? -EAGAIN : err; 1212 } else { 1213 do { 1214 /* ~10% longer */ 1215 signed long timeout = 1000 * H2_BLOCK_SIZE * 1216 2 * dac->voices * HZ / dac->sample_rate / 900; 1217 unsigned long flags; 1218 DECLARE_WAITQUEUE(wait, current); 1219 ssize_t cnt = 0; 1220 1221 err = hal2_add_buffer(hal2, buf, count); 1222 if (err > 0) { 1223 count -= err; 1224 cnt += err; 1225 buf += err; 1226 err = cnt; 1227 } 1228 if (count > 0 && err >= 0) { 1229 add_wait_queue(&dac->dma_wait, &wait); 1230 set_current_state(TASK_INTERRUPTIBLE); 1231 schedule_timeout(timeout); 1232 spin_lock_irqsave(&dac->lock, flags); 1233 if (dac->desc[dac->head].cnt) 1234 err = -EAGAIN; 1235 spin_unlock_irqrestore(&dac->lock, flags); 1236 if (signal_pending(current)) 1237 err = -ERESTARTSYS; 1238 remove_wait_queue(&dac->dma_wait, &wait); 1239 if (err < 0) { 1240 hal2_stop_dac(hal2); 1241 hal2_reset_dac_pointer(hal2); 1242 } 1243 } 1244 } while (count > 0 && err >= 0); 1245 } 1246 mutex_unlock(&dac->sem); 1247 1248 return err; 1249} 1250 1251static unsigned int hal2_poll(struct file *file, struct poll_table_struct *wait) 1252{ 1253 unsigned long flags; 1254 unsigned int mask = 0; 1255 struct hal2_card *hal2 = (struct hal2_card *) file->private_data; 1256 1257 if (file->f_mode & FMODE_READ) { 1258 struct hal2_codec *adc = &hal2->adc; 1259 1260 poll_wait(file, &adc->dma_wait, wait); 1261 spin_lock_irqsave(&adc->lock, flags); 1262 if (adc->desc[adc->tail].cnt > 0) 1263 mask |= POLLIN; 1264 spin_unlock_irqrestore(&adc->lock, flags); 1265 } 1266 1267 if (file->f_mode & FMODE_WRITE) { 1268 struct hal2_codec *dac = &hal2->dac; 1269 1270 poll_wait(file, &dac->dma_wait, wait); 1271 spin_lock_irqsave(&dac->lock, flags); 1272 if (dac->desc[dac->head].cnt == 0) 1273 mask |= POLLOUT; 1274 spin_unlock_irqrestore(&dac->lock, flags); 1275 } 1276 1277 return mask; 1278} 1279 1280static int hal2_open(struct inode *inode, struct file *file) 1281{ 1282 int err; 1283 struct hal2_card *hal2 = hal2_dsp_find_card(iminor(inode)); 1284 1285 if (!hal2) 1286 return -ENODEV; 1287 file->private_data = hal2; 1288 if (file->f_mode & FMODE_READ) { 1289 struct hal2_codec *adc = &hal2->adc; 1290 1291 if (adc->usecount) 1292 return -EBUSY; 1293 /* OSS spec wanted us to use 8 bit, 8 kHz mono by default, 1294 * but HAL2 can't do 8bit audio */ 1295 adc->format = AFMT_S16_BE; 1296 adc->voices = 1; 1297 adc->sample_rate = hal2_compute_rate(adc, 8000); 1298 hal2_set_adc_rate(hal2); 1299 err = hal2_alloc_adc_dmabuf(adc); 1300 if (err) 1301 return err; 1302 hal2_setup_adc(hal2); 1303 adc->usecount++; 1304 } 1305 if (file->f_mode & FMODE_WRITE) { 1306 struct hal2_codec *dac = &hal2->dac; 1307 1308 if (dac->usecount) 1309 return -EBUSY; 1310 dac->format = AFMT_S16_BE; 1311 dac->voices = 1; 1312 dac->sample_rate = hal2_compute_rate(dac, 8000); 1313 hal2_set_dac_rate(hal2); 1314 err = hal2_alloc_dac_dmabuf(dac); 1315 if (err) 1316 return err; 1317 hal2_setup_dac(hal2); 1318 dac->usecount++; 1319 } 1320 1321 return nonseekable_open(inode, file); 1322} 1323 1324static int hal2_release(struct inode *inode, struct file *file) 1325{ 1326 struct hal2_card *hal2 = (struct hal2_card *) file->private_data; 1327 1328 if (file->f_mode & FMODE_READ) { 1329 struct hal2_codec *adc = &hal2->adc; 1330 1331 mutex_lock(&adc->sem); 1332 hal2_stop_adc(hal2); 1333 hal2_free_adc_dmabuf(adc); 1334 adc->usecount--; 1335 mutex_unlock(&adc->sem); 1336 } 1337 if (file->f_mode & FMODE_WRITE) { 1338 struct hal2_codec *dac = &hal2->dac; 1339 1340 mutex_lock(&dac->sem); 1341 hal2_sync_dac(hal2); 1342 hal2_free_dac_dmabuf(dac); 1343 dac->usecount--; 1344 mutex_unlock(&dac->sem); 1345 } 1346 1347 return 0; 1348} 1349 1350static const struct file_operations hal2_audio_fops = { 1351 .owner = THIS_MODULE, 1352 .llseek = no_llseek, 1353 .read = hal2_read, 1354 .write = hal2_write, 1355 .poll = hal2_poll, 1356 .ioctl = hal2_ioctl, 1357 .open = hal2_open, 1358 .release = hal2_release, 1359}; 1360 1361static const struct file_operations hal2_mixer_fops = { 1362 .owner = THIS_MODULE, 1363 .llseek = no_llseek, 1364 .ioctl = hal2_ioctl_mixdev, 1365 .open = hal2_open_mixdev, 1366 .release = hal2_release_mixdev, 1367}; 1368 1369static void hal2_init_codec(struct hal2_codec *codec, struct hpc3_regs *hpc3, 1370 int index) 1371{ 1372 codec->pbus.pbusnr = index; 1373 codec->pbus.pbus = &hpc3->pbdma[index]; 1374 init_waitqueue_head(&codec->dma_wait); 1375 mutex_init(&codec->sem); 1376 spin_lock_init(&codec->lock); 1377} 1378 1379static int hal2_detect(struct hal2_card *hal2) 1380{ 1381 unsigned short board, major, minor; 1382 unsigned short rev; 1383 1384 /* reset HAL2 */ 1385 hal2_isr_write(hal2, 0); 1386 /* release reset */ 1387 hal2_isr_write(hal2, H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N); 1388 1389 hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE); 1390 if ((rev = hal2_rev_look(hal2)) & H2_REV_AUDIO_PRESENT) 1391 return -ENODEV; 1392 1393 board = (rev & H2_REV_BOARD_M) >> 12; 1394 major = (rev & H2_REV_MAJOR_CHIP_M) >> 4; 1395 minor = (rev & H2_REV_MINOR_CHIP_M); 1396 1397 printk(KERN_INFO "SGI HAL2 revision %i.%i.%i\n", 1398 board, major, minor); 1399 1400 return 0; 1401} 1402 1403static int hal2_init_card(struct hal2_card **phal2, struct hpc3_regs *hpc3) 1404{ 1405 int ret = 0; 1406 struct hal2_card *hal2; 1407 1408 hal2 = kzalloc(sizeof(struct hal2_card), GFP_KERNEL); 1409 if (!hal2) 1410 return -ENOMEM; 1411 1412 hal2->ctl_regs = (struct hal2_ctl_regs *)hpc3->pbus_extregs[0]; 1413 hal2->aes_regs = (struct hal2_aes_regs *)hpc3->pbus_extregs[1]; 1414 hal2->vol_regs = (struct hal2_vol_regs *)hpc3->pbus_extregs[2]; 1415 hal2->syn_regs = (struct hal2_syn_regs *)hpc3->pbus_extregs[3]; 1416 1417 if (hal2_detect(hal2) < 0) { 1418 ret = -ENODEV; 1419 goto free_card; 1420 } 1421 1422 hal2_init_codec(&hal2->dac, hpc3, 0); 1423 hal2_init_codec(&hal2->adc, hpc3, 1); 1424 1425 /* 1426 * All DMA channel interfaces in HAL2 are designed to operate with 1427 * PBUS programmed for 2 cycles in D3, 2 cycles in D4 and 2 cycles 1428 * in D5. HAL2 is a 16-bit device which can accept both big and little 1429 * endian format. It assumes that even address bytes are on high 1430 * portion of PBUS (15:8) and assumes that HPC3 is programmed to 1431 * accept a live (unsynchronized) version of P_DREQ_N from HAL2. 1432 */ 1433#define HAL2_PBUS_DMACFG ((0 << HPC3_DMACFG_D3R_SHIFT) | \ 1434 (2 << HPC3_DMACFG_D4R_SHIFT) | \ 1435 (2 << HPC3_DMACFG_D5R_SHIFT) | \ 1436 (0 << HPC3_DMACFG_D3W_SHIFT) | \ 1437 (2 << HPC3_DMACFG_D4W_SHIFT) | \ 1438 (2 << HPC3_DMACFG_D5W_SHIFT) | \ 1439 HPC3_DMACFG_DS16 | \ 1440 HPC3_DMACFG_EVENHI | \ 1441 HPC3_DMACFG_RTIME | \ 1442 (8 << HPC3_DMACFG_BURST_SHIFT) | \ 1443 HPC3_DMACFG_DRQLIVE) 1444 /* 1445 * Ignore what's mentioned in the specification and write value which 1446 * works in The Real World (TM) 1447 */ 1448 hpc3->pbus_dmacfg[hal2->dac.pbus.pbusnr][0] = 0x8208844; 1449 hpc3->pbus_dmacfg[hal2->adc.pbus.pbusnr][0] = 0x8208844; 1450 1451 if (request_irq(SGI_HPCDMA_IRQ, hal2_interrupt, IRQF_SHARED, 1452 hal2str, hal2)) { 1453 printk(KERN_ERR "HAL2: Can't get irq %d\n", SGI_HPCDMA_IRQ); 1454 ret = -EAGAIN; 1455 goto free_card; 1456 } 1457 1458 hal2->dev_dsp = register_sound_dsp(&hal2_audio_fops, -1); 1459 if (hal2->dev_dsp < 0) { 1460 ret = hal2->dev_dsp; 1461 goto free_irq; 1462 } 1463 1464 hal2->dev_mixer = register_sound_mixer(&hal2_mixer_fops, -1); 1465 if (hal2->dev_mixer < 0) { 1466 ret = hal2->dev_mixer; 1467 goto unregister_dsp; 1468 } 1469 1470 hal2_init_mixer(hal2); 1471 1472 *phal2 = hal2; 1473 return 0; 1474unregister_dsp: 1475 unregister_sound_dsp(hal2->dev_dsp); 1476free_irq: 1477 free_irq(SGI_HPCDMA_IRQ, hal2); 1478free_card: 1479 kfree(hal2); 1480 1481 return ret; 1482} 1483 1484extern void (*indy_volume_button)(int); 1485 1486/* 1487 * Assuming only one HAL2 card. Mail me if you ever meet machine with 1488 * more than one. 1489 */ 1490static int __init init_hal2(void) 1491{ 1492 int i, error; 1493 1494 for (i = 0; i < MAXCARDS; i++) 1495 hal2_card[i] = NULL; 1496 1497 error = hal2_init_card(&hal2_card[0], hpc3c0); 1498 1499 /* let Indy's volume buttons work */ 1500 if (!error && !ip22_is_fullhouse()) 1501 indy_volume_button = hal2_volume_control; 1502 1503 return error; 1504 1505} 1506 1507static void __exit exit_hal2(void) 1508{ 1509 int i; 1510 1511 /* unregister volume butons callback function */ 1512 indy_volume_button = NULL; 1513 1514 for (i = 0; i < MAXCARDS; i++) 1515 if (hal2_card[i]) { 1516 free_irq(SGI_HPCDMA_IRQ, hal2_card[i]); 1517 unregister_sound_dsp(hal2_card[i]->dev_dsp); 1518 unregister_sound_mixer(hal2_card[i]->dev_mixer); 1519 kfree(hal2_card[i]); 1520 } 1521} 1522 1523module_init(init_hal2); 1524module_exit(exit_hal2); 1525 1526MODULE_DESCRIPTION("OSS compatible driver for SGI HAL2 audio"); 1527MODULE_AUTHOR("Ladislav Michl"); 1528MODULE_LICENSE("GPL"); 1529