1/*****************************************************************************/ 2 3/* 4 * es1371.c -- Creative Ensoniq ES1371. 5 * 6 * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 * Special thanks to Ensoniq 23 * 24 * Supported devices: 25 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible 26 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible 27 * /dev/dsp1 additional DAC, like /dev/dsp, but outputs to mixer "SYNTH" setting 28 * /dev/midi simple MIDI UART interface, no ioctl 29 * 30 * NOTE: the card does not have any FM/Wavetable synthesizer, it is supposed 31 * to be done in software. That is what /dev/dac is for. By now (Q2 1998) 32 * there are several MIDI to PCM (WAV) packages, one of them is timidity. 33 * 34 * Revision history 35 * 04.06.1998 0.1 Initial release 36 * Mixer stuff should be overhauled; especially optional AC97 mixer bits 37 * should be detected. This results in strange behaviour of some mixer 38 * settings, like master volume and mic. 39 * 08.06.1998 0.2 First release using Alan Cox' soundcore instead of miscdevice 40 * 03.08.1998 0.3 Do not include modversions.h 41 * Now mixer behaviour can basically be selected between 42 * "OSS documented" and "OSS actual" behaviour 43 * 31.08.1998 0.4 Fix realplayer problems - dac.count issues 44 * 27.10.1998 0.5 Fix joystick support 45 * -- Oliver Neukum (c188@org.chemie.uni-muenchen.de) 46 * 10.12.1998 0.6 Fix drain_dac trying to wait on not yet initialized DMA 47 * 23.12.1998 0.7 Fix a few f_file & FMODE_ bugs 48 * Don't wake up app until there are fragsize bytes to read/write 49 * 06.01.1999 0.8 remove the silly SA_INTERRUPT flag. 50 * hopefully killed the egcs section type conflict 51 * 12.03.1999 0.9 cinfo.blocks should be reset after GETxPTR ioctl. 52 * reported by Johan Maes <joma@telindus.be> 53 * 22.03.1999 0.10 return EAGAIN instead of EBUSY when O_NONBLOCK 54 * read/write cannot be executed 55 * 07.04.1999 0.11 implemented the following ioctl's: SOUND_PCM_READ_RATE, 56 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS; 57 * Alpha fixes reported by Peter Jones <pjones@redhat.com> 58 * Another Alpha fix (wait_src_ready in init routine) 59 * reported by "Ivan N. Kokshaysky" <ink@jurassic.park.msu.ru> 60 * Note: joystick address handling might still be wrong on archs 61 * other than i386 62 * 15.06.1999 0.12 Fix bad allocation bug. 63 * Thanks to Deti Fliegl <fliegl@in.tum.de> 64 * 28.06.1999 0.13 Add pci_set_master 65 * 03.08.1999 0.14 adapt to Linus' new __setup/__initcall 66 * added kernel command line option "es1371=joystickaddr" 67 * removed CONFIG_SOUND_ES1371_JOYPORT_BOOT kludge 68 * 10.08.1999 0.15 (Re)added S/PDIF module option for cards revision >= 4. 69 * Initial version by Dave Platt <dplatt@snulbug.mtview.ca.us>. 70 * module_init/__setup fixes 71 * 08.16.1999 0.16 Joe Cotellese <joec@ensoniq.com> 72 * Added detection for ES1371 revision ID so that we can 73 * detect the ES1373 and later parts. 74 * added AC97 #defines for readability 75 * added a /proc file system for dumping hardware state 76 * updated SRC and CODEC w/r functions to accommodate bugs 77 * in some versions of the ES137x chips. 78 * 31.08.1999 0.17 add spin_lock_init 79 * replaced current->state = x with set_current_state(x) 80 * 03.09.1999 0.18 change read semantics for MIDI to match 81 * OSS more closely; remove possible wakeup race 82 * 21.10.1999 0.19 Round sampling rates, requested by 83 * Kasamatsu Kenichi <t29w0267@ip.media.kyoto-u.ac.jp> 84 * 27.10.1999 0.20 Added SigmaTel 3D enhancement string 85 * Codec ID printing changes 86 * 28.10.1999 0.21 More waitqueue races fixed 87 * Joe Cotellese <joec@ensoniq.com> 88 * Changed PCI detection routine so we can more easily 89 * detect ES137x chip and derivatives. 90 * 05.01.2000 0.22 Should now work with rev7 boards; patch by 91 * Eric Lemar, elemar@cs.washington.edu 92 * 08.01.2000 0.23 Prevent some ioctl's from returning bad count values on underrun/overrun; 93 * Tim Janik's BSE (Bedevilled Sound Engine) found this 94 * 07.02.2000 0.24 Use pci_alloc_consistent and pci_register_driver 95 * 07.02.2000 0.25 Use ac97_codec 96 * 01.03.2000 0.26 SPDIF patch by Mikael Bouillot <mikael.bouillot@bigfoot.com> 97 * Use pci_module_init 98 * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask 99 * 12.12.2000 0.28 More dma buffer initializations, patch from 100 * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com> 101 * 05.01.2001 0.29 Hopefully updates will not be required anymore when Creative bumps 102 * the CT5880 revision. 103 * suggested by Stephan M��ller <smueller@chronox.de> 104 * 31.01.2001 0.30 Register/Unregister gameport 105 * Fix SETTRIGGER non OSS API conformity 106 * 14.07.2001 0.31 Add list of laptops needing amplifier control 107 * 03.01.2003 0.32 open_mode fixes from Georg Acher <acher@in.tum.de> 108 */ 109 110/*****************************************************************************/ 111 112#include <linux/interrupt.h> 113#include <linux/module.h> 114#include <linux/string.h> 115#include <linux/ioport.h> 116#include <linux/sched.h> 117#include <linux/delay.h> 118#include <linux/sound.h> 119#include <linux/slab.h> 120#include <linux/soundcard.h> 121#include <linux/pci.h> 122#include <linux/init.h> 123#include <linux/poll.h> 124#include <linux/bitops.h> 125#include <linux/proc_fs.h> 126#include <linux/spinlock.h> 127#include <linux/smp_lock.h> 128#include <linux/ac97_codec.h> 129#include <linux/gameport.h> 130#include <linux/wait.h> 131#include <linux/dma-mapping.h> 132#include <linux/mutex.h> 133#include <linux/mm.h> 134#include <linux/kernel.h> 135 136#include <asm/io.h> 137#include <asm/page.h> 138#include <asm/uaccess.h> 139 140#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 141#define SUPPORT_JOYSTICK 142#endif 143 144/* --------------------------------------------------------------------- */ 145 146#undef OSS_DOCUMENTED_MIXER_SEMANTICS 147#define ES1371_DEBUG 148#define DBG(x) {} 149/*#define DBG(x) {x}*/ 150 151/* --------------------------------------------------------------------- */ 152 153#ifndef PCI_VENDOR_ID_ENSONIQ 154#define PCI_VENDOR_ID_ENSONIQ 0x1274 155#endif 156 157#ifndef PCI_VENDOR_ID_ECTIVA 158#define PCI_VENDOR_ID_ECTIVA 0x1102 159#endif 160 161#ifndef PCI_DEVICE_ID_ENSONIQ_ES1371 162#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371 163#endif 164 165#ifndef PCI_DEVICE_ID_ENSONIQ_CT5880 166#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880 167#endif 168 169#ifndef PCI_DEVICE_ID_ECTIVA_EV1938 170#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938 171#endif 172 173/* ES1371 chip ID */ 174/* This is a little confusing because all ES1371 compatible chips have the 175 same DEVICE_ID, the only thing differentiating them is the REV_ID field. 176 This is only significant if you want to enable features on the later parts. 177 Yes, I know it's stupid and why didn't we use the sub IDs? 178*/ 179#define ES1371REV_ES1373_A 0x04 180#define ES1371REV_ES1373_B 0x06 181#define ES1371REV_CT5880_A 0x07 182#define CT5880REV_CT5880_C 0x02 183#define CT5880REV_CT5880_D 0x03 184#define ES1371REV_ES1371_B 0x09 185#define EV1938REV_EV1938_A 0x00 186#define ES1371REV_ES1373_8 0x08 187 188#define ES1371_MAGIC ((PCI_VENDOR_ID_ENSONIQ<<16)|PCI_DEVICE_ID_ENSONIQ_ES1371) 189 190#define ES1371_EXTENT 0x40 191#define JOY_EXTENT 8 192 193#define ES1371_REG_CONTROL 0x00 194#define ES1371_REG_STATUS 0x04 /* on the 5880 it is control/status */ 195#define ES1371_REG_UART_DATA 0x08 196#define ES1371_REG_UART_STATUS 0x09 197#define ES1371_REG_UART_CONTROL 0x09 198#define ES1371_REG_UART_TEST 0x0a 199#define ES1371_REG_MEMPAGE 0x0c 200#define ES1371_REG_SRCONV 0x10 201#define ES1371_REG_CODEC 0x14 202#define ES1371_REG_LEGACY 0x18 203#define ES1371_REG_SERIAL_CONTROL 0x20 204#define ES1371_REG_DAC1_SCOUNT 0x24 205#define ES1371_REG_DAC2_SCOUNT 0x28 206#define ES1371_REG_ADC_SCOUNT 0x2c 207 208#define ES1371_REG_DAC1_FRAMEADR 0xc30 209#define ES1371_REG_DAC1_FRAMECNT 0xc34 210#define ES1371_REG_DAC2_FRAMEADR 0xc38 211#define ES1371_REG_DAC2_FRAMECNT 0xc3c 212#define ES1371_REG_ADC_FRAMEADR 0xd30 213#define ES1371_REG_ADC_FRAMECNT 0xd34 214 215#define ES1371_FMT_U8_MONO 0 216#define ES1371_FMT_U8_STEREO 1 217#define ES1371_FMT_S16_MONO 2 218#define ES1371_FMT_S16_STEREO 3 219#define ES1371_FMT_STEREO 1 220#define ES1371_FMT_S16 2 221#define ES1371_FMT_MASK 3 222 223static const unsigned sample_size[] = { 1, 2, 2, 4 }; 224static const unsigned sample_shift[] = { 0, 1, 1, 2 }; 225 226#define CTRL_RECEN_B 0x08000000 /* 1 = don't mix analog in to digital out */ 227#define CTRL_SPDIFEN_B 0x04000000 228#define CTRL_JOY_SHIFT 24 229#define CTRL_JOY_MASK 3 230#define CTRL_JOY_200 0x00000000 /* joystick base address */ 231#define CTRL_JOY_208 0x01000000 232#define CTRL_JOY_210 0x02000000 233#define CTRL_JOY_218 0x03000000 234#define CTRL_GPIO_IN0 0x00100000 /* general purpose inputs/outputs */ 235#define CTRL_GPIO_IN1 0x00200000 236#define CTRL_GPIO_IN2 0x00400000 237#define CTRL_GPIO_IN3 0x00800000 238#define CTRL_GPIO_OUT0 0x00010000 239#define CTRL_GPIO_OUT1 0x00020000 240#define CTRL_GPIO_OUT2 0x00040000 241#define CTRL_GPIO_OUT3 0x00080000 242#define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */ 243#define CTRL_SYNCRES 0x00004000 /* AC97 warm reset */ 244#define CTRL_ADCSTOP 0x00002000 /* stop ADC transfers */ 245#define CTRL_PWR_INTRM 0x00001000 /* 1 = power level ints enabled */ 246#define CTRL_M_CB 0x00000800 /* recording source: 0 = ADC, 1 = MPEG */ 247#define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */ 248#define CTRL_PDLEV0 0x00000000 /* power down level */ 249#define CTRL_PDLEV1 0x00000100 250#define CTRL_PDLEV2 0x00000200 251#define CTRL_PDLEV3 0x00000300 252#define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */ 253#define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */ 254#define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */ 255#define CTRL_ADC_EN 0x00000010 /* enable ADC */ 256#define CTRL_UART_EN 0x00000008 /* enable MIDI uart */ 257#define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port */ 258#define CTRL_XTALCLKDIS 0x00000002 /* 1 = disable crystal clock input */ 259#define CTRL_PCICLKDIS 0x00000001 /* 1 = disable PCI clock distribution */ 260 261 262#define STAT_INTR 0x80000000 /* wired or of all interrupt bits */ 263#define CSTAT_5880_AC97_RST 0x20000000 /* CT5880 Reset bit */ 264#define STAT_EN_SPDIF 0x00040000 /* enable S/PDIF circuitry */ 265#define STAT_TS_SPDIF 0x00020000 /* test S/PDIF circuitry */ 266#define STAT_TESTMODE 0x00010000 /* test ASIC */ 267#define STAT_SYNC_ERR 0x00000100 /* 1 = codec sync error */ 268#define STAT_VC 0x000000c0 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */ 269#define STAT_SH_VC 6 270#define STAT_MPWR 0x00000020 /* power level interrupt */ 271#define STAT_MCCB 0x00000010 /* CCB int pending */ 272#define STAT_UART 0x00000008 /* UART int pending */ 273#define STAT_DAC1 0x00000004 /* DAC1 int pending */ 274#define STAT_DAC2 0x00000002 /* DAC2 int pending */ 275#define STAT_ADC 0x00000001 /* ADC int pending */ 276 277#define USTAT_RXINT 0x80 /* UART rx int pending */ 278#define USTAT_TXINT 0x04 /* UART tx int pending */ 279#define USTAT_TXRDY 0x02 /* UART tx ready */ 280#define USTAT_RXRDY 0x01 /* UART rx ready */ 281 282#define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */ 283#define UCTRL_TXINTEN 0x60 /* TX int enable field mask */ 284#define UCTRL_ENA_TXINT 0x20 /* enable TX int */ 285#define UCTRL_CNTRL 0x03 /* control field */ 286#define UCTRL_CNTRL_SWR 0x03 /* software reset command */ 287 288/* sample rate converter */ 289#define SRC_OKSTATE 1 290 291#define SRC_RAMADDR_MASK 0xfe000000 292#define SRC_RAMADDR_SHIFT 25 293#define SRC_DAC1FREEZE (1UL << 21) 294#define SRC_DAC2FREEZE (1UL << 20) 295#define SRC_ADCFREEZE (1UL << 19) 296 297 298#define SRC_WE 0x01000000 /* read/write control for SRC RAM */ 299#define SRC_BUSY 0x00800000 /* SRC busy */ 300#define SRC_DIS 0x00400000 /* 1 = disable SRC */ 301#define SRC_DDAC1 0x00200000 /* 1 = disable accum update for DAC1 */ 302#define SRC_DDAC2 0x00100000 /* 1 = disable accum update for DAC2 */ 303#define SRC_DADC 0x00080000 /* 1 = disable accum update for ADC2 */ 304#define SRC_CTLMASK 0x00780000 305#define SRC_RAMDATA_MASK 0x0000ffff 306#define SRC_RAMDATA_SHIFT 0 307 308#define SRCREG_ADC 0x78 309#define SRCREG_DAC1 0x70 310#define SRCREG_DAC2 0x74 311#define SRCREG_VOL_ADC 0x6c 312#define SRCREG_VOL_DAC1 0x7c 313#define SRCREG_VOL_DAC2 0x7e 314 315#define SRCREG_TRUNC_N 0x00 316#define SRCREG_INT_REGS 0x01 317#define SRCREG_ACCUM_FRAC 0x02 318#define SRCREG_VFREQ_FRAC 0x03 319 320#define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */ 321#define CODEC_PIADD_MASK 0x007f0000 322#define CODEC_PIADD_SHIFT 16 323#define CODEC_PIDAT_MASK 0x0000ffff 324#define CODEC_PIDAT_SHIFT 0 325 326#define CODEC_RDY 0x80000000 /* AC97 read data valid */ 327#define CODEC_WIP 0x40000000 /* AC97 write in progress */ 328#define CODEC_PORD 0x00800000 /* 0 = write AC97 register */ 329#define CODEC_POADD_MASK 0x007f0000 330#define CODEC_POADD_SHIFT 16 331#define CODEC_PODAT_MASK 0x0000ffff 332#define CODEC_PODAT_SHIFT 0 333 334 335#define LEGACY_JFAST 0x80000000 /* fast joystick timing */ 336#define LEGACY_FIRQ 0x01000000 /* force IRQ */ 337 338#define SCTRL_DACTEST 0x00400000 /* 1 = DAC test, test vector generation purposes */ 339#define SCTRL_P2ENDINC 0x00380000 /* */ 340#define SCTRL_SH_P2ENDINC 19 341#define SCTRL_P2STINC 0x00070000 /* */ 342#define SCTRL_SH_P2STINC 16 343#define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */ 344#define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */ 345#define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */ 346#define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */ 347#define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */ 348#define SCTRL_R1INTEN 0x00000400 /* enable interrupt */ 349#define SCTRL_P2INTEN 0x00000200 /* enable interrupt */ 350#define SCTRL_P1INTEN 0x00000100 /* enable interrupt */ 351#define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */ 352#define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */ 353#define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */ 354#define SCTRL_R1SMB 0x00000010 /* 1 = stereo */ 355#define SCTRL_R1FMT 0x00000030 /* format mask */ 356#define SCTRL_SH_R1FMT 4 357#define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */ 358#define SCTRL_P2SMB 0x00000004 /* 1 = stereo */ 359#define SCTRL_P2FMT 0x0000000c /* format mask */ 360#define SCTRL_SH_P2FMT 2 361#define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */ 362#define SCTRL_P1SMB 0x00000001 /* 1 = stereo */ 363#define SCTRL_P1FMT 0x00000003 /* format mask */ 364#define SCTRL_SH_P1FMT 0 365 366 367/* misc stuff */ 368#define POLL_COUNT 0x1000 369#define FMODE_DAC 4 /* slight misuse of mode_t */ 370 371/* MIDI buffer sizes */ 372 373#define MIDIINBUF 256 374#define MIDIOUTBUF 256 375 376#define FMODE_MIDI_SHIFT 3 377#define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT) 378#define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT) 379 380#define ES1371_MODULE_NAME "es1371" 381#define PFX ES1371_MODULE_NAME ": " 382 383/* --------------------------------------------------------------------- */ 384 385struct es1371_state { 386 /* magic */ 387 unsigned int magic; 388 389 /* list of es1371 devices */ 390 struct list_head devs; 391 392 /* the corresponding pci_dev structure */ 393 struct pci_dev *dev; 394 395 /* soundcore stuff */ 396 int dev_audio; 397 int dev_dac; 398 int dev_midi; 399 400 /* hardware resources */ 401 unsigned long io; /* long for SPARC */ 402 unsigned int irq; 403 404 /* PCI ID's */ 405 u16 vendor; 406 u16 device; 407 u8 rev; /* the chip revision */ 408 409 /* options */ 410 int spdif_volume; /* S/PDIF output is enabled if != -1 */ 411 412#ifdef ES1371_DEBUG 413 /* debug /proc entry */ 414 struct proc_dir_entry *ps; 415#endif /* ES1371_DEBUG */ 416 417 struct ac97_codec *codec; 418 419 /* wave stuff */ 420 unsigned ctrl; 421 unsigned sctrl; 422 unsigned dac1rate, dac2rate, adcrate; 423 424 spinlock_t lock; 425 struct mutex open_mutex; 426 mode_t open_mode; 427 wait_queue_head_t open_wait; 428 429 struct dmabuf { 430 void *rawbuf; 431 dma_addr_t dmaaddr; 432 unsigned buforder; 433 unsigned numfrag; 434 unsigned fragshift; 435 unsigned hwptr, swptr; 436 unsigned total_bytes; 437 int count; 438 unsigned error; /* over/underrun */ 439 wait_queue_head_t wait; 440 /* redundant, but makes calculations easier */ 441 unsigned fragsize; 442 unsigned dmasize; 443 unsigned fragsamples; 444 /* OSS stuff */ 445 unsigned mapped:1; 446 unsigned ready:1; 447 unsigned endcleared:1; 448 unsigned enabled:1; 449 unsigned ossfragshift; 450 int ossmaxfrags; 451 unsigned subdivision; 452 } dma_dac1, dma_dac2, dma_adc; 453 454 /* midi stuff */ 455 struct { 456 unsigned ird, iwr, icnt; 457 unsigned ord, owr, ocnt; 458 wait_queue_head_t iwait; 459 wait_queue_head_t owait; 460 unsigned char ibuf[MIDIINBUF]; 461 unsigned char obuf[MIDIOUTBUF]; 462 } midi; 463 464#ifdef SUPPORT_JOYSTICK 465 struct gameport *gameport; 466#endif 467 468 struct mutex sem; 469}; 470 471/* --------------------------------------------------------------------- */ 472 473static LIST_HEAD(devs); 474 475/* --------------------------------------------------------------------- */ 476 477static inline unsigned ld2(unsigned int x) 478{ 479 unsigned r = 0; 480 481 if (x >= 0x10000) { 482 x >>= 16; 483 r += 16; 484 } 485 if (x >= 0x100) { 486 x >>= 8; 487 r += 8; 488 } 489 if (x >= 0x10) { 490 x >>= 4; 491 r += 4; 492 } 493 if (x >= 4) { 494 x >>= 2; 495 r += 2; 496 } 497 if (x >= 2) 498 r++; 499 return r; 500} 501 502/* --------------------------------------------------------------------- */ 503 504static unsigned wait_src_ready(struct es1371_state *s) 505{ 506 unsigned int t, r; 507 508 for (t = 0; t < POLL_COUNT; t++) { 509 if (!((r = inl(s->io + ES1371_REG_SRCONV)) & SRC_BUSY)) 510 return r; 511 udelay(1); 512 } 513 printk(KERN_DEBUG PFX "sample rate converter timeout r = 0x%08x\n", r); 514 return r; 515} 516 517static unsigned src_read(struct es1371_state *s, unsigned reg) 518{ 519 unsigned int temp,i,orig; 520 521 /* wait for ready */ 522 temp = wait_src_ready (s); 523 524 /* we can only access the SRC at certain times, make sure 525 we're allowed to before we read */ 526 527 orig = temp; 528 /* expose the SRC state bits */ 529 outl ( (temp & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT) | 0x10000UL, 530 s->io + ES1371_REG_SRCONV); 531 532 /* now, wait for busy and the correct time to read */ 533 temp = wait_src_ready (s); 534 535 if ( (temp & 0x00870000UL ) != ( SRC_OKSTATE << 16 )){ 536 /* wait for the right state */ 537 for (i=0; i<POLL_COUNT; i++){ 538 temp = inl (s->io + ES1371_REG_SRCONV); 539 if ( (temp & 0x00870000UL ) == ( SRC_OKSTATE << 16 )) 540 break; 541 } 542 } 543 544 /* hide the state bits */ 545 outl ((orig & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT), s->io + ES1371_REG_SRCONV); 546 return temp; 547 548 549} 550 551static void src_write(struct es1371_state *s, unsigned reg, unsigned data) 552{ 553 554 unsigned int r; 555 556 r = wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC); 557 r |= (reg << SRC_RAMADDR_SHIFT) & SRC_RAMADDR_MASK; 558 r |= (data << SRC_RAMDATA_SHIFT) & SRC_RAMDATA_MASK; 559 outl(r | SRC_WE, s->io + ES1371_REG_SRCONV); 560 561} 562 563/* --------------------------------------------------------------------- */ 564 565/* most of the following here is black magic */ 566static void set_adc_rate(struct es1371_state *s, unsigned rate) 567{ 568 unsigned long flags; 569 unsigned int n, truncm, freq; 570 571 if (rate > 48000) 572 rate = 48000; 573 if (rate < 4000) 574 rate = 4000; 575 n = rate / 3000; 576 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9))) 577 n--; 578 truncm = (21 * n - 1) | 1; 579 freq = ((48000UL << 15) / rate) * n; 580 s->adcrate = (48000UL << 15) / (freq / n); 581 spin_lock_irqsave(&s->lock, flags); 582 if (rate >= 24000) { 583 if (truncm > 239) 584 truncm = 239; 585 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N, 586 (((239 - truncm) >> 1) << 9) | (n << 4)); 587 } else { 588 if (truncm > 119) 589 truncm = 119; 590 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N, 591 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4)); 592 } 593 src_write(s, SRCREG_ADC+SRCREG_INT_REGS, 594 (src_read(s, SRCREG_ADC+SRCREG_INT_REGS) & 0x00ff) | 595 ((freq >> 5) & 0xfc00)); 596 src_write(s, SRCREG_ADC+SRCREG_VFREQ_FRAC, freq & 0x7fff); 597 src_write(s, SRCREG_VOL_ADC, n << 8); 598 src_write(s, SRCREG_VOL_ADC+1, n << 8); 599 spin_unlock_irqrestore(&s->lock, flags); 600} 601 602 603static void set_dac1_rate(struct es1371_state *s, unsigned rate) 604{ 605 unsigned long flags; 606 unsigned int freq, r; 607 608 if (rate > 48000) 609 rate = 48000; 610 if (rate < 4000) 611 rate = 4000; 612 freq = ((rate << 15) + 1500) / 3000; 613 s->dac1rate = (freq * 3000 + 16384) >> 15; 614 spin_lock_irqsave(&s->lock, flags); 615 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC)) | SRC_DDAC1; 616 outl(r, s->io + ES1371_REG_SRCONV); 617 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 618 (src_read(s, SRCREG_DAC1+SRCREG_INT_REGS) & 0x00ff) | 619 ((freq >> 5) & 0xfc00)); 620 src_write(s, SRCREG_DAC1+SRCREG_VFREQ_FRAC, freq & 0x7fff); 621 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC)); 622 outl(r, s->io + ES1371_REG_SRCONV); 623 spin_unlock_irqrestore(&s->lock, flags); 624} 625 626static void set_dac2_rate(struct es1371_state *s, unsigned rate) 627{ 628 unsigned long flags; 629 unsigned int freq, r; 630 631 if (rate > 48000) 632 rate = 48000; 633 if (rate < 4000) 634 rate = 4000; 635 freq = ((rate << 15) + 1500) / 3000; 636 s->dac2rate = (freq * 3000 + 16384) >> 15; 637 spin_lock_irqsave(&s->lock, flags); 638 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC)) | SRC_DDAC2; 639 outl(r, s->io + ES1371_REG_SRCONV); 640 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 641 (src_read(s, SRCREG_DAC2+SRCREG_INT_REGS) & 0x00ff) | 642 ((freq >> 5) & 0xfc00)); 643 src_write(s, SRCREG_DAC2+SRCREG_VFREQ_FRAC, freq & 0x7fff); 644 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC)); 645 outl(r, s->io + ES1371_REG_SRCONV); 646 spin_unlock_irqrestore(&s->lock, flags); 647} 648 649/* --------------------------------------------------------------------- */ 650 651static void __devinit src_init(struct es1371_state *s) 652{ 653 unsigned int i; 654 655 /* before we enable or disable the SRC we need 656 to wait for it to become ready */ 657 wait_src_ready(s); 658 659 outl(SRC_DIS, s->io + ES1371_REG_SRCONV); 660 661 for (i = 0; i < 0x80; i++) 662 src_write(s, i, 0); 663 664 src_write(s, SRCREG_DAC1+SRCREG_TRUNC_N, 16 << 4); 665 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 16 << 10); 666 src_write(s, SRCREG_DAC2+SRCREG_TRUNC_N, 16 << 4); 667 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 16 << 10); 668 src_write(s, SRCREG_VOL_ADC, 1 << 12); 669 src_write(s, SRCREG_VOL_ADC+1, 1 << 12); 670 src_write(s, SRCREG_VOL_DAC1, 1 << 12); 671 src_write(s, SRCREG_VOL_DAC1+1, 1 << 12); 672 src_write(s, SRCREG_VOL_DAC2, 1 << 12); 673 src_write(s, SRCREG_VOL_DAC2+1, 1 << 12); 674 set_adc_rate(s, 22050); 675 set_dac1_rate(s, 22050); 676 set_dac2_rate(s, 22050); 677 678 /* WARNING: 679 * enabling the sample rate converter without properly programming 680 * its parameters causes the chip to lock up (the SRC busy bit will 681 * be stuck high, and I've found no way to rectify this other than 682 * power cycle) 683 */ 684 wait_src_ready(s); 685 outl(0, s->io+ES1371_REG_SRCONV); 686} 687 688/* --------------------------------------------------------------------- */ 689 690static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data) 691{ 692 struct es1371_state *s = (struct es1371_state *)codec->private_data; 693 unsigned long flags; 694 unsigned t, x; 695 696 spin_lock_irqsave(&s->lock, flags); 697 for (t = 0; t < POLL_COUNT; t++) 698 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP)) 699 break; 700 701 /* save the current state for later */ 702 x = wait_src_ready(s); 703 704 /* enable SRC state data in SRC mux */ 705 outl((x & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC)) | 0x00010000, 706 s->io+ES1371_REG_SRCONV); 707 708 /* wait for not busy (state 0) first to avoid 709 transition states */ 710 for (t=0; t<POLL_COUNT; t++){ 711 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 ) 712 break; 713 udelay(1); 714 } 715 716 /* wait for a SAFE time to write addr/data and then do it, dammit */ 717 for (t=0; t<POLL_COUNT; t++){ 718 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000) 719 break; 720 udelay(1); 721 } 722 723 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | 724 ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), s->io+ES1371_REG_CODEC); 725 726 /* restore SRC reg */ 727 wait_src_ready(s); 728 outl(x, s->io+ES1371_REG_SRCONV); 729 spin_unlock_irqrestore(&s->lock, flags); 730} 731 732static u16 rdcodec(struct ac97_codec *codec, u8 addr) 733{ 734 struct es1371_state *s = (struct es1371_state *)codec->private_data; 735 unsigned long flags; 736 unsigned t, x; 737 738 spin_lock_irqsave(&s->lock, flags); 739 740 /* wait for WIP to go away */ 741 for (t = 0; t < 0x1000; t++) 742 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP)) 743 break; 744 745 /* save the current state for later */ 746 x = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC)); 747 748 /* enable SRC state data in SRC mux */ 749 outl( x | 0x00010000, 750 s->io+ES1371_REG_SRCONV); 751 752 /* wait for not busy (state 0) first to avoid 753 transition states */ 754 for (t=0; t<POLL_COUNT; t++){ 755 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 ) 756 break; 757 udelay(1); 758 } 759 760 /* wait for a SAFE time to write addr/data and then do it, dammit */ 761 for (t=0; t<POLL_COUNT; t++){ 762 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000) 763 break; 764 udelay(1); 765 } 766 767 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD, s->io+ES1371_REG_CODEC); 768 /* restore SRC reg */ 769 wait_src_ready(s); 770 outl(x, s->io+ES1371_REG_SRCONV); 771 772 /* wait for WIP again */ 773 for (t = 0; t < 0x1000; t++) 774 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP)) 775 break; 776 777 /* now wait for the stinkin' data (RDY) */ 778 for (t = 0; t < POLL_COUNT; t++) 779 if ((x = inl(s->io+ES1371_REG_CODEC)) & CODEC_RDY) 780 break; 781 782 spin_unlock_irqrestore(&s->lock, flags); 783 return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT); 784} 785 786/* --------------------------------------------------------------------- */ 787 788static inline void stop_adc(struct es1371_state *s) 789{ 790 unsigned long flags; 791 792 spin_lock_irqsave(&s->lock, flags); 793 s->ctrl &= ~CTRL_ADC_EN; 794 outl(s->ctrl, s->io+ES1371_REG_CONTROL); 795 spin_unlock_irqrestore(&s->lock, flags); 796} 797 798static inline void stop_dac1(struct es1371_state *s) 799{ 800 unsigned long flags; 801 802 spin_lock_irqsave(&s->lock, flags); 803 s->ctrl &= ~CTRL_DAC1_EN; 804 outl(s->ctrl, s->io+ES1371_REG_CONTROL); 805 spin_unlock_irqrestore(&s->lock, flags); 806} 807 808static inline void stop_dac2(struct es1371_state *s) 809{ 810 unsigned long flags; 811 812 spin_lock_irqsave(&s->lock, flags); 813 s->ctrl &= ~CTRL_DAC2_EN; 814 outl(s->ctrl, s->io+ES1371_REG_CONTROL); 815 spin_unlock_irqrestore(&s->lock, flags); 816} 817 818static void start_dac1(struct es1371_state *s) 819{ 820 unsigned long flags; 821 unsigned fragremain, fshift; 822 823 spin_lock_irqsave(&s->lock, flags); 824 if (!(s->ctrl & CTRL_DAC1_EN) && (s->dma_dac1.mapped || s->dma_dac1.count > 0) 825 && s->dma_dac1.ready) { 826 s->ctrl |= CTRL_DAC1_EN; 827 s->sctrl = (s->sctrl & ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD)) | SCTRL_P1INTEN; 828 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 829 fragremain = ((- s->dma_dac1.hwptr) & (s->dma_dac1.fragsize-1)); 830 fshift = sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT]; 831 if (fragremain < 2*fshift) 832 fragremain = s->dma_dac1.fragsize; 833 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT); 834 outl(s->ctrl, s->io+ES1371_REG_CONTROL); 835 outl((s->dma_dac1.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT); 836 } 837 spin_unlock_irqrestore(&s->lock, flags); 838} 839 840static void start_dac2(struct es1371_state *s) 841{ 842 unsigned long flags; 843 unsigned fragremain, fshift; 844 845 spin_lock_irqsave(&s->lock, flags); 846 if (!(s->ctrl & CTRL_DAC2_EN) && (s->dma_dac2.mapped || s->dma_dac2.count > 0) 847 && s->dma_dac2.ready) { 848 s->ctrl |= CTRL_DAC2_EN; 849 s->sctrl = (s->sctrl & ~(SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN | 850 SCTRL_P2ENDINC | SCTRL_P2STINC)) | SCTRL_P2INTEN | 851 (((s->sctrl & SCTRL_P2FMT) ? 2 : 1) << SCTRL_SH_P2ENDINC) | 852 (0 << SCTRL_SH_P2STINC); 853 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 854 fragremain = ((- s->dma_dac2.hwptr) & (s->dma_dac2.fragsize-1)); 855 fshift = sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT]; 856 if (fragremain < 2*fshift) 857 fragremain = s->dma_dac2.fragsize; 858 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT); 859 outl(s->ctrl, s->io+ES1371_REG_CONTROL); 860 outl((s->dma_dac2.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT); 861 } 862 spin_unlock_irqrestore(&s->lock, flags); 863} 864 865static void start_adc(struct es1371_state *s) 866{ 867 unsigned long flags; 868 unsigned fragremain, fshift; 869 870 spin_lock_irqsave(&s->lock, flags); 871 if (!(s->ctrl & CTRL_ADC_EN) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize)) 872 && s->dma_adc.ready) { 873 s->ctrl |= CTRL_ADC_EN; 874 s->sctrl = (s->sctrl & ~SCTRL_R1LOOPSEL) | SCTRL_R1INTEN; 875 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 876 fragremain = ((- s->dma_adc.hwptr) & (s->dma_adc.fragsize-1)); 877 fshift = sample_shift[(s->sctrl & SCTRL_R1FMT) >> SCTRL_SH_R1FMT]; 878 if (fragremain < 2*fshift) 879 fragremain = s->dma_adc.fragsize; 880 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT); 881 outl(s->ctrl, s->io+ES1371_REG_CONTROL); 882 outl((s->dma_adc.fragsize >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT); 883 } 884 spin_unlock_irqrestore(&s->lock, flags); 885} 886 887/* --------------------------------------------------------------------- */ 888 889#define DMABUF_DEFAULTORDER (17-PAGE_SHIFT) 890#define DMABUF_MINORDER 1 891 892 893static inline void dealloc_dmabuf(struct es1371_state *s, struct dmabuf *db) 894{ 895 struct page *page, *pend; 896 897 if (db->rawbuf) { 898 /* undo marking the pages as reserved */ 899 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1); 900 for (page = virt_to_page(db->rawbuf); page <= pend; page++) 901 ClearPageReserved(page); 902 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr); 903 } 904 db->rawbuf = NULL; 905 db->mapped = db->ready = 0; 906} 907 908static int prog_dmabuf(struct es1371_state *s, struct dmabuf *db, unsigned rate, unsigned fmt, unsigned reg) 909{ 910 int order; 911 unsigned bytepersec; 912 unsigned bufs; 913 struct page *page, *pend; 914 915 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0; 916 if (!db->rawbuf) { 917 db->ready = db->mapped = 0; 918 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--) 919 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr))) 920 break; 921 if (!db->rawbuf) 922 return -ENOMEM; 923 db->buforder = order; 924 /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */ 925 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1); 926 for (page = virt_to_page(db->rawbuf); page <= pend; page++) 927 SetPageReserved(page); 928 } 929 fmt &= ES1371_FMT_MASK; 930 bytepersec = rate << sample_shift[fmt]; 931 bufs = PAGE_SIZE << db->buforder; 932 if (db->ossfragshift) { 933 if ((1000 << db->ossfragshift) < bytepersec) 934 db->fragshift = ld2(bytepersec/1000); 935 else 936 db->fragshift = db->ossfragshift; 937 } else { 938 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1)); 939 if (db->fragshift < 3) 940 db->fragshift = 3; 941 } 942 db->numfrag = bufs >> db->fragshift; 943 while (db->numfrag < 4 && db->fragshift > 3) { 944 db->fragshift--; 945 db->numfrag = bufs >> db->fragshift; 946 } 947 db->fragsize = 1 << db->fragshift; 948 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag) 949 db->numfrag = db->ossmaxfrags; 950 db->fragsamples = db->fragsize >> sample_shift[fmt]; 951 db->dmasize = db->numfrag << db->fragshift; 952 memset(db->rawbuf, (fmt & ES1371_FMT_S16) ? 0 : 0x80, db->dmasize); 953 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE); 954 outl(db->dmaaddr, s->io+(reg & 0xff)); 955 outl((db->dmasize >> 2)-1, s->io+((reg + 4) & 0xff)); 956 db->enabled = 1; 957 db->ready = 1; 958 return 0; 959} 960 961static inline int prog_dmabuf_adc(struct es1371_state *s) 962{ 963 stop_adc(s); 964 return prog_dmabuf(s, &s->dma_adc, s->adcrate, (s->sctrl >> SCTRL_SH_R1FMT) & ES1371_FMT_MASK, 965 ES1371_REG_ADC_FRAMEADR); 966} 967 968static inline int prog_dmabuf_dac2(struct es1371_state *s) 969{ 970 stop_dac2(s); 971 return prog_dmabuf(s, &s->dma_dac2, s->dac2rate, (s->sctrl >> SCTRL_SH_P2FMT) & ES1371_FMT_MASK, 972 ES1371_REG_DAC2_FRAMEADR); 973} 974 975static inline int prog_dmabuf_dac1(struct es1371_state *s) 976{ 977 stop_dac1(s); 978 return prog_dmabuf(s, &s->dma_dac1, s->dac1rate, (s->sctrl >> SCTRL_SH_P1FMT) & ES1371_FMT_MASK, 979 ES1371_REG_DAC1_FRAMEADR); 980} 981 982static inline unsigned get_hwptr(struct es1371_state *s, struct dmabuf *db, unsigned reg) 983{ 984 unsigned hwptr, diff; 985 986 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE); 987 hwptr = (inl(s->io+(reg & 0xff)) >> 14) & 0x3fffc; 988 diff = (db->dmasize + hwptr - db->hwptr) % db->dmasize; 989 db->hwptr = hwptr; 990 return diff; 991} 992 993static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c) 994{ 995 if (bptr + len > bsize) { 996 unsigned x = bsize - bptr; 997 memset(((char *)buf) + bptr, c, x); 998 bptr = 0; 999 len -= x; 1000 } 1001 memset(((char *)buf) + bptr, c, len); 1002} 1003 1004/* call with spinlock held! */ 1005static void es1371_update_ptr(struct es1371_state *s) 1006{ 1007 int diff; 1008 1009 /* update ADC pointer */ 1010 if (s->ctrl & CTRL_ADC_EN) { 1011 diff = get_hwptr(s, &s->dma_adc, ES1371_REG_ADC_FRAMECNT); 1012 s->dma_adc.total_bytes += diff; 1013 s->dma_adc.count += diff; 1014 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize) 1015 wake_up(&s->dma_adc.wait); 1016 if (!s->dma_adc.mapped) { 1017 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) { 1018 s->ctrl &= ~CTRL_ADC_EN; 1019 outl(s->ctrl, s->io+ES1371_REG_CONTROL); 1020 s->dma_adc.error++; 1021 } 1022 } 1023 } 1024 /* update DAC1 pointer */ 1025 if (s->ctrl & CTRL_DAC1_EN) { 1026 diff = get_hwptr(s, &s->dma_dac1, ES1371_REG_DAC1_FRAMECNT); 1027 s->dma_dac1.total_bytes += diff; 1028 if (s->dma_dac1.mapped) { 1029 s->dma_dac1.count += diff; 1030 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize) 1031 wake_up(&s->dma_dac1.wait); 1032 } else { 1033 s->dma_dac1.count -= diff; 1034 if (s->dma_dac1.count <= 0) { 1035 s->ctrl &= ~CTRL_DAC1_EN; 1036 outl(s->ctrl, s->io+ES1371_REG_CONTROL); 1037 s->dma_dac1.error++; 1038 } else if (s->dma_dac1.count <= (signed)s->dma_dac1.fragsize && !s->dma_dac1.endcleared) { 1039 clear_advance(s->dma_dac1.rawbuf, s->dma_dac1.dmasize, s->dma_dac1.swptr, 1040 s->dma_dac1.fragsize, (s->sctrl & SCTRL_P1SEB) ? 0 : 0x80); 1041 s->dma_dac1.endcleared = 1; 1042 } 1043 if (s->dma_dac1.count + (signed)s->dma_dac1.fragsize <= (signed)s->dma_dac1.dmasize) 1044 wake_up(&s->dma_dac1.wait); 1045 } 1046 } 1047 /* update DAC2 pointer */ 1048 if (s->ctrl & CTRL_DAC2_EN) { 1049 diff = get_hwptr(s, &s->dma_dac2, ES1371_REG_DAC2_FRAMECNT); 1050 s->dma_dac2.total_bytes += diff; 1051 if (s->dma_dac2.mapped) { 1052 s->dma_dac2.count += diff; 1053 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize) 1054 wake_up(&s->dma_dac2.wait); 1055 } else { 1056 s->dma_dac2.count -= diff; 1057 if (s->dma_dac2.count <= 0) { 1058 s->ctrl &= ~CTRL_DAC2_EN; 1059 outl(s->ctrl, s->io+ES1371_REG_CONTROL); 1060 s->dma_dac2.error++; 1061 } else if (s->dma_dac2.count <= (signed)s->dma_dac2.fragsize && !s->dma_dac2.endcleared) { 1062 clear_advance(s->dma_dac2.rawbuf, s->dma_dac2.dmasize, s->dma_dac2.swptr, 1063 s->dma_dac2.fragsize, (s->sctrl & SCTRL_P2SEB) ? 0 : 0x80); 1064 s->dma_dac2.endcleared = 1; 1065 } 1066 if (s->dma_dac2.count + (signed)s->dma_dac2.fragsize <= (signed)s->dma_dac2.dmasize) 1067 wake_up(&s->dma_dac2.wait); 1068 } 1069 } 1070} 1071 1072/* hold spinlock for the following! */ 1073static void es1371_handle_midi(struct es1371_state *s) 1074{ 1075 unsigned char ch; 1076 int wake; 1077 1078 if (!(s->ctrl & CTRL_UART_EN)) 1079 return; 1080 wake = 0; 1081 while (inb(s->io+ES1371_REG_UART_STATUS) & USTAT_RXRDY) { 1082 ch = inb(s->io+ES1371_REG_UART_DATA); 1083 if (s->midi.icnt < MIDIINBUF) { 1084 s->midi.ibuf[s->midi.iwr] = ch; 1085 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF; 1086 s->midi.icnt++; 1087 } 1088 wake = 1; 1089 } 1090 if (wake) 1091 wake_up(&s->midi.iwait); 1092 wake = 0; 1093 while ((inb(s->io+ES1371_REG_UART_STATUS) & USTAT_TXRDY) && s->midi.ocnt > 0) { 1094 outb(s->midi.obuf[s->midi.ord], s->io+ES1371_REG_UART_DATA); 1095 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF; 1096 s->midi.ocnt--; 1097 if (s->midi.ocnt < MIDIOUTBUF-16) 1098 wake = 1; 1099 } 1100 if (wake) 1101 wake_up(&s->midi.owait); 1102 outb((s->midi.ocnt > 0) ? UCTRL_RXINTEN | UCTRL_ENA_TXINT : UCTRL_RXINTEN, s->io+ES1371_REG_UART_CONTROL); 1103} 1104 1105static irqreturn_t es1371_interrupt(int irq, void *dev_id) 1106{ 1107 struct es1371_state *s = dev_id; 1108 unsigned int intsrc, sctl; 1109 1110 /* fastpath out, to ease interrupt sharing */ 1111 intsrc = inl(s->io+ES1371_REG_STATUS); 1112 if (!(intsrc & 0x80000000)) 1113 return IRQ_NONE; 1114 spin_lock(&s->lock); 1115 /* clear audio interrupts first */ 1116 sctl = s->sctrl; 1117 if (intsrc & STAT_ADC) 1118 sctl &= ~SCTRL_R1INTEN; 1119 if (intsrc & STAT_DAC1) 1120 sctl &= ~SCTRL_P1INTEN; 1121 if (intsrc & STAT_DAC2) 1122 sctl &= ~SCTRL_P2INTEN; 1123 outl(sctl, s->io+ES1371_REG_SERIAL_CONTROL); 1124 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 1125 es1371_update_ptr(s); 1126 es1371_handle_midi(s); 1127 spin_unlock(&s->lock); 1128 return IRQ_HANDLED; 1129} 1130 1131/* --------------------------------------------------------------------- */ 1132 1133static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value\n"; 1134 1135#define VALIDATE_STATE(s) \ 1136({ \ 1137 if (!(s) || (s)->magic != ES1371_MAGIC) { \ 1138 printk(invalid_magic); \ 1139 return -ENXIO; \ 1140 } \ 1141}) 1142 1143/* --------------------------------------------------------------------- */ 1144 1145/* Conversion table for S/PDIF PCM volume emulation through the SRC */ 1146/* dB-linear table of DAC vol values; -0dB to -46.5dB with mute */ 1147static const unsigned short DACVolTable[101] = 1148{ 1149 0x1000, 0x0f2a, 0x0e60, 0x0da0, 0x0cea, 0x0c3e, 0x0b9a, 0x0aff, 1150 0x0a6d, 0x09e1, 0x095e, 0x08e1, 0x086a, 0x07fa, 0x078f, 0x072a, 1151 0x06cb, 0x0670, 0x061a, 0x05c9, 0x057b, 0x0532, 0x04ed, 0x04ab, 1152 0x046d, 0x0432, 0x03fa, 0x03c5, 0x0392, 0x0363, 0x0335, 0x030b, 1153 0x02e2, 0x02bc, 0x0297, 0x0275, 0x0254, 0x0235, 0x0217, 0x01fb, 1154 0x01e1, 0x01c8, 0x01b0, 0x0199, 0x0184, 0x0170, 0x015d, 0x014b, 1155 0x0139, 0x0129, 0x0119, 0x010b, 0x00fd, 0x00f0, 0x00e3, 0x00d7, 1156 0x00cc, 0x00c1, 0x00b7, 0x00ae, 0x00a5, 0x009c, 0x0094, 0x008c, 1157 0x0085, 0x007e, 0x0077, 0x0071, 0x006b, 0x0066, 0x0060, 0x005b, 1158 0x0057, 0x0052, 0x004e, 0x004a, 0x0046, 0x0042, 0x003f, 0x003c, 1159 0x0038, 0x0036, 0x0033, 0x0030, 0x002e, 0x002b, 0x0029, 0x0027, 1160 0x0025, 0x0023, 0x0021, 0x001f, 0x001e, 0x001c, 0x001b, 0x0019, 1161 0x0018, 0x0017, 0x0016, 0x0014, 0x0000 1162}; 1163 1164/* 1165 * when we are in S/PDIF mode, we want to disable any analog output so 1166 * we filter the mixer ioctls 1167 */ 1168static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd, unsigned long arg) 1169{ 1170 struct es1371_state *s = (struct es1371_state *)codec->private_data; 1171 int val; 1172 unsigned long flags; 1173 unsigned int left, right; 1174 1175 VALIDATE_STATE(s); 1176 /* filter mixer ioctls to catch PCM and MASTER volume when in S/PDIF mode */ 1177 if (s->spdif_volume == -1) 1178 return codec->mixer_ioctl(codec, cmd, arg); 1179 switch (cmd) { 1180 case SOUND_MIXER_WRITE_VOLUME: 1181 return 0; 1182 1183 case SOUND_MIXER_WRITE_PCM: /* use SRC for PCM volume */ 1184 if (get_user(val, (int __user *)arg)) 1185 return -EFAULT; 1186 right = ((val >> 8) & 0xff); 1187 left = (val & 0xff); 1188 if (right > 100) 1189 right = 100; 1190 if (left > 100) 1191 left = 100; 1192 s->spdif_volume = (right << 8) | left; 1193 spin_lock_irqsave(&s->lock, flags); 1194 src_write(s, SRCREG_VOL_DAC2, DACVolTable[100 - left]); 1195 src_write(s, SRCREG_VOL_DAC2+1, DACVolTable[100 - right]); 1196 spin_unlock_irqrestore(&s->lock, flags); 1197 return 0; 1198 1199 case SOUND_MIXER_READ_PCM: 1200 return put_user(s->spdif_volume, (int __user *)arg); 1201 } 1202 return codec->mixer_ioctl(codec, cmd, arg); 1203} 1204 1205/* --------------------------------------------------------------------- */ 1206 1207/* 1208 * AC97 Mixer Register to Connections mapping of the Concert 97 board 1209 * 1210 * AC97_MASTER_VOL_STEREO Line Out 1211 * AC97_MASTER_VOL_MONO TAD Output 1212 * AC97_PCBEEP_VOL none 1213 * AC97_PHONE_VOL TAD Input (mono) 1214 * AC97_MIC_VOL MIC Input (mono) 1215 * AC97_LINEIN_VOL Line Input (stereo) 1216 * AC97_CD_VOL CD Input (stereo) 1217 * AC97_VIDEO_VOL none 1218 * AC97_AUX_VOL Aux Input (stereo) 1219 * AC97_PCMOUT_VOL Wave Output (stereo) 1220 */ 1221 1222static int es1371_open_mixdev(struct inode *inode, struct file *file) 1223{ 1224 int minor = iminor(inode); 1225 struct list_head *list; 1226 struct es1371_state *s; 1227 1228 for (list = devs.next; ; list = list->next) { 1229 if (list == &devs) 1230 return -ENODEV; 1231 s = list_entry(list, struct es1371_state, devs); 1232 if (s->codec->dev_mixer == minor) 1233 break; 1234 } 1235 VALIDATE_STATE(s); 1236 file->private_data = s; 1237 return nonseekable_open(inode, file); 1238} 1239 1240static int es1371_release_mixdev(struct inode *inode, struct file *file) 1241{ 1242 struct es1371_state *s = (struct es1371_state *)file->private_data; 1243 1244 VALIDATE_STATE(s); 1245 return 0; 1246} 1247 1248static int es1371_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) 1249{ 1250 struct es1371_state *s = (struct es1371_state *)file->private_data; 1251 struct ac97_codec *codec = s->codec; 1252 1253 return mixdev_ioctl(codec, cmd, arg); 1254} 1255 1256static /*const*/ struct file_operations es1371_mixer_fops = { 1257 .owner = THIS_MODULE, 1258 .llseek = no_llseek, 1259 .ioctl = es1371_ioctl_mixdev, 1260 .open = es1371_open_mixdev, 1261 .release = es1371_release_mixdev, 1262}; 1263 1264/* --------------------------------------------------------------------- */ 1265 1266static int drain_dac1(struct es1371_state *s, int nonblock) 1267{ 1268 DECLARE_WAITQUEUE(wait, current); 1269 unsigned long flags; 1270 int count, tmo; 1271 1272 if (s->dma_dac1.mapped || !s->dma_dac1.ready) 1273 return 0; 1274 add_wait_queue(&s->dma_dac1.wait, &wait); 1275 for (;;) { 1276 __set_current_state(TASK_INTERRUPTIBLE); 1277 spin_lock_irqsave(&s->lock, flags); 1278 count = s->dma_dac1.count; 1279 spin_unlock_irqrestore(&s->lock, flags); 1280 if (count <= 0) 1281 break; 1282 if (signal_pending(current)) 1283 break; 1284 if (nonblock) { 1285 remove_wait_queue(&s->dma_dac1.wait, &wait); 1286 set_current_state(TASK_RUNNING); 1287 return -EBUSY; 1288 } 1289 tmo = 3 * HZ * (count + s->dma_dac1.fragsize) / 2 / s->dac1rate; 1290 tmo >>= sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT]; 1291 if (!schedule_timeout(tmo + 1)) 1292 DBG(printk(KERN_DEBUG PFX "dac1 dma timed out??\n");) 1293 } 1294 remove_wait_queue(&s->dma_dac1.wait, &wait); 1295 set_current_state(TASK_RUNNING); 1296 if (signal_pending(current)) 1297 return -ERESTARTSYS; 1298 return 0; 1299} 1300 1301static int drain_dac2(struct es1371_state *s, int nonblock) 1302{ 1303 DECLARE_WAITQUEUE(wait, current); 1304 unsigned long flags; 1305 int count, tmo; 1306 1307 if (s->dma_dac2.mapped || !s->dma_dac2.ready) 1308 return 0; 1309 add_wait_queue(&s->dma_dac2.wait, &wait); 1310 for (;;) { 1311 __set_current_state(TASK_UNINTERRUPTIBLE); 1312 spin_lock_irqsave(&s->lock, flags); 1313 count = s->dma_dac2.count; 1314 spin_unlock_irqrestore(&s->lock, flags); 1315 if (count <= 0) 1316 break; 1317 if (signal_pending(current)) 1318 break; 1319 if (nonblock) { 1320 remove_wait_queue(&s->dma_dac2.wait, &wait); 1321 set_current_state(TASK_RUNNING); 1322 return -EBUSY; 1323 } 1324 tmo = 3 * HZ * (count + s->dma_dac2.fragsize) / 2 / s->dac2rate; 1325 tmo >>= sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT]; 1326 if (!schedule_timeout(tmo + 1)) 1327 DBG(printk(KERN_DEBUG PFX "dac2 dma timed out??\n");) 1328 } 1329 remove_wait_queue(&s->dma_dac2.wait, &wait); 1330 set_current_state(TASK_RUNNING); 1331 if (signal_pending(current)) 1332 return -ERESTARTSYS; 1333 return 0; 1334} 1335 1336/* --------------------------------------------------------------------- */ 1337 1338static ssize_t es1371_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos) 1339{ 1340 struct es1371_state *s = (struct es1371_state *)file->private_data; 1341 DECLARE_WAITQUEUE(wait, current); 1342 ssize_t ret = 0; 1343 unsigned long flags; 1344 unsigned swptr; 1345 int cnt; 1346 1347 VALIDATE_STATE(s); 1348 if (s->dma_adc.mapped) 1349 return -ENXIO; 1350 if (!access_ok(VERIFY_WRITE, buffer, count)) 1351 return -EFAULT; 1352 mutex_lock(&s->sem); 1353 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s))) 1354 goto out2; 1355 1356 add_wait_queue(&s->dma_adc.wait, &wait); 1357 while (count > 0) { 1358 spin_lock_irqsave(&s->lock, flags); 1359 swptr = s->dma_adc.swptr; 1360 cnt = s->dma_adc.dmasize-swptr; 1361 if (s->dma_adc.count < cnt) 1362 cnt = s->dma_adc.count; 1363 if (cnt <= 0) 1364 __set_current_state(TASK_INTERRUPTIBLE); 1365 spin_unlock_irqrestore(&s->lock, flags); 1366 if (cnt > count) 1367 cnt = count; 1368 if (cnt <= 0) { 1369 if (s->dma_adc.enabled) 1370 start_adc(s); 1371 if (file->f_flags & O_NONBLOCK) { 1372 if (!ret) 1373 ret = -EAGAIN; 1374 goto out; 1375 } 1376 mutex_unlock(&s->sem); 1377 schedule(); 1378 if (signal_pending(current)) { 1379 if (!ret) 1380 ret = -ERESTARTSYS; 1381 goto out2; 1382 } 1383 mutex_lock(&s->sem); 1384 if (s->dma_adc.mapped) 1385 { 1386 ret = -ENXIO; 1387 goto out; 1388 } 1389 continue; 1390 } 1391 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) { 1392 if (!ret) 1393 ret = -EFAULT; 1394 goto out; 1395 } 1396 swptr = (swptr + cnt) % s->dma_adc.dmasize; 1397 spin_lock_irqsave(&s->lock, flags); 1398 s->dma_adc.swptr = swptr; 1399 s->dma_adc.count -= cnt; 1400 spin_unlock_irqrestore(&s->lock, flags); 1401 count -= cnt; 1402 buffer += cnt; 1403 ret += cnt; 1404 if (s->dma_adc.enabled) 1405 start_adc(s); 1406 } 1407out: 1408 mutex_unlock(&s->sem); 1409out2: 1410 remove_wait_queue(&s->dma_adc.wait, &wait); 1411 set_current_state(TASK_RUNNING); 1412 return ret; 1413} 1414 1415static ssize_t es1371_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos) 1416{ 1417 struct es1371_state *s = (struct es1371_state *)file->private_data; 1418 DECLARE_WAITQUEUE(wait, current); 1419 ssize_t ret; 1420 unsigned long flags; 1421 unsigned swptr; 1422 int cnt; 1423 1424 VALIDATE_STATE(s); 1425 if (s->dma_dac2.mapped) 1426 return -ENXIO; 1427 if (!access_ok(VERIFY_READ, buffer, count)) 1428 return -EFAULT; 1429 mutex_lock(&s->sem); 1430 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s))) 1431 goto out3; 1432 ret = 0; 1433 add_wait_queue(&s->dma_dac2.wait, &wait); 1434 while (count > 0) { 1435 spin_lock_irqsave(&s->lock, flags); 1436 if (s->dma_dac2.count < 0) { 1437 s->dma_dac2.count = 0; 1438 s->dma_dac2.swptr = s->dma_dac2.hwptr; 1439 } 1440 swptr = s->dma_dac2.swptr; 1441 cnt = s->dma_dac2.dmasize-swptr; 1442 if (s->dma_dac2.count + cnt > s->dma_dac2.dmasize) 1443 cnt = s->dma_dac2.dmasize - s->dma_dac2.count; 1444 if (cnt <= 0) 1445 __set_current_state(TASK_INTERRUPTIBLE); 1446 spin_unlock_irqrestore(&s->lock, flags); 1447 if (cnt > count) 1448 cnt = count; 1449 if (cnt <= 0) { 1450 if (s->dma_dac2.enabled) 1451 start_dac2(s); 1452 if (file->f_flags & O_NONBLOCK) { 1453 if (!ret) 1454 ret = -EAGAIN; 1455 goto out; 1456 } 1457 mutex_unlock(&s->sem); 1458 schedule(); 1459 if (signal_pending(current)) { 1460 if (!ret) 1461 ret = -ERESTARTSYS; 1462 goto out2; 1463 } 1464 mutex_lock(&s->sem); 1465 if (s->dma_dac2.mapped) 1466 { 1467 ret = -ENXIO; 1468 goto out; 1469 } 1470 continue; 1471 } 1472 if (copy_from_user(s->dma_dac2.rawbuf + swptr, buffer, cnt)) { 1473 if (!ret) 1474 ret = -EFAULT; 1475 goto out; 1476 } 1477 swptr = (swptr + cnt) % s->dma_dac2.dmasize; 1478 spin_lock_irqsave(&s->lock, flags); 1479 s->dma_dac2.swptr = swptr; 1480 s->dma_dac2.count += cnt; 1481 s->dma_dac2.endcleared = 0; 1482 spin_unlock_irqrestore(&s->lock, flags); 1483 count -= cnt; 1484 buffer += cnt; 1485 ret += cnt; 1486 if (s->dma_dac2.enabled) 1487 start_dac2(s); 1488 } 1489out: 1490 mutex_unlock(&s->sem); 1491out2: 1492 remove_wait_queue(&s->dma_dac2.wait, &wait); 1493out3: 1494 set_current_state(TASK_RUNNING); 1495 return ret; 1496} 1497 1498/* No kernel lock - we have our own spinlock */ 1499static unsigned int es1371_poll(struct file *file, struct poll_table_struct *wait) 1500{ 1501 struct es1371_state *s = (struct es1371_state *)file->private_data; 1502 unsigned long flags; 1503 unsigned int mask = 0; 1504 1505 VALIDATE_STATE(s); 1506 if (file->f_mode & FMODE_WRITE) { 1507 if (!s->dma_dac2.ready && prog_dmabuf_dac2(s)) 1508 return 0; 1509 poll_wait(file, &s->dma_dac2.wait, wait); 1510 } 1511 if (file->f_mode & FMODE_READ) { 1512 if (!s->dma_adc.ready && prog_dmabuf_adc(s)) 1513 return 0; 1514 poll_wait(file, &s->dma_adc.wait, wait); 1515 } 1516 spin_lock_irqsave(&s->lock, flags); 1517 es1371_update_ptr(s); 1518 if (file->f_mode & FMODE_READ) { 1519 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize) 1520 mask |= POLLIN | POLLRDNORM; 1521 } 1522 if (file->f_mode & FMODE_WRITE) { 1523 if (s->dma_dac2.mapped) { 1524 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize) 1525 mask |= POLLOUT | POLLWRNORM; 1526 } else { 1527 if ((signed)s->dma_dac2.dmasize >= s->dma_dac2.count + (signed)s->dma_dac2.fragsize) 1528 mask |= POLLOUT | POLLWRNORM; 1529 } 1530 } 1531 spin_unlock_irqrestore(&s->lock, flags); 1532 return mask; 1533} 1534 1535static int es1371_mmap(struct file *file, struct vm_area_struct *vma) 1536{ 1537 struct es1371_state *s = (struct es1371_state *)file->private_data; 1538 struct dmabuf *db; 1539 int ret = 0; 1540 unsigned long size; 1541 1542 VALIDATE_STATE(s); 1543 lock_kernel(); 1544 mutex_lock(&s->sem); 1545 1546 if (vma->vm_flags & VM_WRITE) { 1547 if ((ret = prog_dmabuf_dac2(s)) != 0) { 1548 goto out; 1549 } 1550 db = &s->dma_dac2; 1551 } else if (vma->vm_flags & VM_READ) { 1552 if ((ret = prog_dmabuf_adc(s)) != 0) { 1553 goto out; 1554 } 1555 db = &s->dma_adc; 1556 } else { 1557 ret = -EINVAL; 1558 goto out; 1559 } 1560 if (vma->vm_pgoff != 0) { 1561 ret = -EINVAL; 1562 goto out; 1563 } 1564 size = vma->vm_end - vma->vm_start; 1565 if (size > (PAGE_SIZE << db->buforder)) { 1566 ret = -EINVAL; 1567 goto out; 1568 } 1569 if (remap_pfn_range(vma, vma->vm_start, 1570 virt_to_phys(db->rawbuf) >> PAGE_SHIFT, 1571 size, vma->vm_page_prot)) { 1572 ret = -EAGAIN; 1573 goto out; 1574 } 1575 db->mapped = 1; 1576out: 1577 mutex_unlock(&s->sem); 1578 unlock_kernel(); 1579 return ret; 1580} 1581 1582static int es1371_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) 1583{ 1584 struct es1371_state *s = (struct es1371_state *)file->private_data; 1585 unsigned long flags; 1586 audio_buf_info abinfo; 1587 count_info cinfo; 1588 int count; 1589 int val, mapped, ret; 1590 void __user *argp = (void __user *)arg; 1591 int __user *p = argp; 1592 1593 VALIDATE_STATE(s); 1594 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac2.mapped) || 1595 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped); 1596 switch (cmd) { 1597 case OSS_GETVERSION: 1598 return put_user(SOUND_VERSION, p); 1599 1600 case SNDCTL_DSP_SYNC: 1601 if (file->f_mode & FMODE_WRITE) 1602 return drain_dac2(s, 0/*file->f_flags & O_NONBLOCK*/); 1603 return 0; 1604 1605 case SNDCTL_DSP_SETDUPLEX: 1606 return 0; 1607 1608 case SNDCTL_DSP_GETCAPS: 1609 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p); 1610 1611 case SNDCTL_DSP_RESET: 1612 if (file->f_mode & FMODE_WRITE) { 1613 stop_dac2(s); 1614 synchronize_irq(s->irq); 1615 s->dma_dac2.swptr = s->dma_dac2.hwptr = s->dma_dac2.count = s->dma_dac2.total_bytes = 0; 1616 } 1617 if (file->f_mode & FMODE_READ) { 1618 stop_adc(s); 1619 synchronize_irq(s->irq); 1620 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0; 1621 } 1622 return 0; 1623 1624 case SNDCTL_DSP_SPEED: 1625 if (get_user(val, p)) 1626 return -EFAULT; 1627 if (val >= 0) { 1628 if (file->f_mode & FMODE_READ) { 1629 stop_adc(s); 1630 s->dma_adc.ready = 0; 1631 set_adc_rate(s, val); 1632 } 1633 if (file->f_mode & FMODE_WRITE) { 1634 stop_dac2(s); 1635 s->dma_dac2.ready = 0; 1636 set_dac2_rate(s, val); 1637 } 1638 } 1639 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p); 1640 1641 case SNDCTL_DSP_STEREO: 1642 if (get_user(val, p)) 1643 return -EFAULT; 1644 if (file->f_mode & FMODE_READ) { 1645 stop_adc(s); 1646 s->dma_adc.ready = 0; 1647 spin_lock_irqsave(&s->lock, flags); 1648 if (val) 1649 s->sctrl |= SCTRL_R1SMB; 1650 else 1651 s->sctrl &= ~SCTRL_R1SMB; 1652 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 1653 spin_unlock_irqrestore(&s->lock, flags); 1654 } 1655 if (file->f_mode & FMODE_WRITE) { 1656 stop_dac2(s); 1657 s->dma_dac2.ready = 0; 1658 spin_lock_irqsave(&s->lock, flags); 1659 if (val) 1660 s->sctrl |= SCTRL_P2SMB; 1661 else 1662 s->sctrl &= ~SCTRL_P2SMB; 1663 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 1664 spin_unlock_irqrestore(&s->lock, flags); 1665 } 1666 return 0; 1667 1668 case SNDCTL_DSP_CHANNELS: 1669 if (get_user(val, p)) 1670 return -EFAULT; 1671 if (val != 0) { 1672 if (file->f_mode & FMODE_READ) { 1673 stop_adc(s); 1674 s->dma_adc.ready = 0; 1675 spin_lock_irqsave(&s->lock, flags); 1676 if (val >= 2) 1677 s->sctrl |= SCTRL_R1SMB; 1678 else 1679 s->sctrl &= ~SCTRL_R1SMB; 1680 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 1681 spin_unlock_irqrestore(&s->lock, flags); 1682 } 1683 if (file->f_mode & FMODE_WRITE) { 1684 stop_dac2(s); 1685 s->dma_dac2.ready = 0; 1686 spin_lock_irqsave(&s->lock, flags); 1687 if (val >= 2) 1688 s->sctrl |= SCTRL_P2SMB; 1689 else 1690 s->sctrl &= ~SCTRL_P2SMB; 1691 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 1692 spin_unlock_irqrestore(&s->lock, flags); 1693 } 1694 } 1695 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p); 1696 1697 case SNDCTL_DSP_GETFMTS: /* Returns a mask */ 1698 return put_user(AFMT_S16_LE|AFMT_U8, p); 1699 1700 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/ 1701 if (get_user(val, p)) 1702 return -EFAULT; 1703 if (val != AFMT_QUERY) { 1704 if (file->f_mode & FMODE_READ) { 1705 stop_adc(s); 1706 s->dma_adc.ready = 0; 1707 spin_lock_irqsave(&s->lock, flags); 1708 if (val == AFMT_S16_LE) 1709 s->sctrl |= SCTRL_R1SEB; 1710 else 1711 s->sctrl &= ~SCTRL_R1SEB; 1712 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 1713 spin_unlock_irqrestore(&s->lock, flags); 1714 } 1715 if (file->f_mode & FMODE_WRITE) { 1716 stop_dac2(s); 1717 s->dma_dac2.ready = 0; 1718 spin_lock_irqsave(&s->lock, flags); 1719 if (val == AFMT_S16_LE) 1720 s->sctrl |= SCTRL_P2SEB; 1721 else 1722 s->sctrl &= ~SCTRL_P2SEB; 1723 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 1724 spin_unlock_irqrestore(&s->lock, flags); 1725 } 1726 } 1727 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ? 1728 AFMT_S16_LE : AFMT_U8, p); 1729 1730 case SNDCTL_DSP_POST: 1731 return 0; 1732 1733 case SNDCTL_DSP_GETTRIGGER: 1734 val = 0; 1735 if (file->f_mode & FMODE_READ && s->ctrl & CTRL_ADC_EN) 1736 val |= PCM_ENABLE_INPUT; 1737 if (file->f_mode & FMODE_WRITE && s->ctrl & CTRL_DAC2_EN) 1738 val |= PCM_ENABLE_OUTPUT; 1739 return put_user(val, p); 1740 1741 case SNDCTL_DSP_SETTRIGGER: 1742 if (get_user(val, p)) 1743 return -EFAULT; 1744 if (file->f_mode & FMODE_READ) { 1745 if (val & PCM_ENABLE_INPUT) { 1746 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s))) 1747 return ret; 1748 s->dma_adc.enabled = 1; 1749 start_adc(s); 1750 } else { 1751 s->dma_adc.enabled = 0; 1752 stop_adc(s); 1753 } 1754 } 1755 if (file->f_mode & FMODE_WRITE) { 1756 if (val & PCM_ENABLE_OUTPUT) { 1757 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s))) 1758 return ret; 1759 s->dma_dac2.enabled = 1; 1760 start_dac2(s); 1761 } else { 1762 s->dma_dac2.enabled = 0; 1763 stop_dac2(s); 1764 } 1765 } 1766 return 0; 1767 1768 case SNDCTL_DSP_GETOSPACE: 1769 if (!(file->f_mode & FMODE_WRITE)) 1770 return -EINVAL; 1771 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0) 1772 return val; 1773 spin_lock_irqsave(&s->lock, flags); 1774 es1371_update_ptr(s); 1775 abinfo.fragsize = s->dma_dac2.fragsize; 1776 count = s->dma_dac2.count; 1777 if (count < 0) 1778 count = 0; 1779 abinfo.bytes = s->dma_dac2.dmasize - count; 1780 abinfo.fragstotal = s->dma_dac2.numfrag; 1781 abinfo.fragments = abinfo.bytes >> s->dma_dac2.fragshift; 1782 spin_unlock_irqrestore(&s->lock, flags); 1783 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0; 1784 1785 case SNDCTL_DSP_GETISPACE: 1786 if (!(file->f_mode & FMODE_READ)) 1787 return -EINVAL; 1788 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0) 1789 return val; 1790 spin_lock_irqsave(&s->lock, flags); 1791 es1371_update_ptr(s); 1792 abinfo.fragsize = s->dma_adc.fragsize; 1793 count = s->dma_adc.count; 1794 if (count < 0) 1795 count = 0; 1796 abinfo.bytes = count; 1797 abinfo.fragstotal = s->dma_adc.numfrag; 1798 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift; 1799 spin_unlock_irqrestore(&s->lock, flags); 1800 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0; 1801 1802 case SNDCTL_DSP_NONBLOCK: 1803 file->f_flags |= O_NONBLOCK; 1804 return 0; 1805 1806 case SNDCTL_DSP_GETODELAY: 1807 if (!(file->f_mode & FMODE_WRITE)) 1808 return -EINVAL; 1809 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0) 1810 return val; 1811 spin_lock_irqsave(&s->lock, flags); 1812 es1371_update_ptr(s); 1813 count = s->dma_dac2.count; 1814 spin_unlock_irqrestore(&s->lock, flags); 1815 if (count < 0) 1816 count = 0; 1817 return put_user(count, p); 1818 1819 case SNDCTL_DSP_GETIPTR: 1820 if (!(file->f_mode & FMODE_READ)) 1821 return -EINVAL; 1822 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0) 1823 return val; 1824 spin_lock_irqsave(&s->lock, flags); 1825 es1371_update_ptr(s); 1826 cinfo.bytes = s->dma_adc.total_bytes; 1827 count = s->dma_adc.count; 1828 if (count < 0) 1829 count = 0; 1830 cinfo.blocks = count >> s->dma_adc.fragshift; 1831 cinfo.ptr = s->dma_adc.hwptr; 1832 if (s->dma_adc.mapped) 1833 s->dma_adc.count &= s->dma_adc.fragsize-1; 1834 spin_unlock_irqrestore(&s->lock, flags); 1835 if (copy_to_user(argp, &cinfo, sizeof(cinfo))) 1836 return -EFAULT; 1837 return 0; 1838 1839 case SNDCTL_DSP_GETOPTR: 1840 if (!(file->f_mode & FMODE_WRITE)) 1841 return -EINVAL; 1842 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0) 1843 return val; 1844 spin_lock_irqsave(&s->lock, flags); 1845 es1371_update_ptr(s); 1846 cinfo.bytes = s->dma_dac2.total_bytes; 1847 count = s->dma_dac2.count; 1848 if (count < 0) 1849 count = 0; 1850 cinfo.blocks = count >> s->dma_dac2.fragshift; 1851 cinfo.ptr = s->dma_dac2.hwptr; 1852 if (s->dma_dac2.mapped) 1853 s->dma_dac2.count &= s->dma_dac2.fragsize-1; 1854 spin_unlock_irqrestore(&s->lock, flags); 1855 if (copy_to_user(argp, &cinfo, sizeof(cinfo))) 1856 return -EFAULT; 1857 return 0; 1858 1859 case SNDCTL_DSP_GETBLKSIZE: 1860 if (file->f_mode & FMODE_WRITE) { 1861 if ((val = prog_dmabuf_dac2(s))) 1862 return val; 1863 return put_user(s->dma_dac2.fragsize, p); 1864 } 1865 if ((val = prog_dmabuf_adc(s))) 1866 return val; 1867 return put_user(s->dma_adc.fragsize, p); 1868 1869 case SNDCTL_DSP_SETFRAGMENT: 1870 if (get_user(val, p)) 1871 return -EFAULT; 1872 if (file->f_mode & FMODE_READ) { 1873 s->dma_adc.ossfragshift = val & 0xffff; 1874 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff; 1875 if (s->dma_adc.ossfragshift < 4) 1876 s->dma_adc.ossfragshift = 4; 1877 if (s->dma_adc.ossfragshift > 15) 1878 s->dma_adc.ossfragshift = 15; 1879 if (s->dma_adc.ossmaxfrags < 4) 1880 s->dma_adc.ossmaxfrags = 4; 1881 } 1882 if (file->f_mode & FMODE_WRITE) { 1883 s->dma_dac2.ossfragshift = val & 0xffff; 1884 s->dma_dac2.ossmaxfrags = (val >> 16) & 0xffff; 1885 if (s->dma_dac2.ossfragshift < 4) 1886 s->dma_dac2.ossfragshift = 4; 1887 if (s->dma_dac2.ossfragshift > 15) 1888 s->dma_dac2.ossfragshift = 15; 1889 if (s->dma_dac2.ossmaxfrags < 4) 1890 s->dma_dac2.ossmaxfrags = 4; 1891 } 1892 return 0; 1893 1894 case SNDCTL_DSP_SUBDIVIDE: 1895 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) || 1896 (file->f_mode & FMODE_WRITE && s->dma_dac2.subdivision)) 1897 return -EINVAL; 1898 if (get_user(val, p)) 1899 return -EFAULT; 1900 if (val != 1 && val != 2 && val != 4) 1901 return -EINVAL; 1902 if (file->f_mode & FMODE_READ) 1903 s->dma_adc.subdivision = val; 1904 if (file->f_mode & FMODE_WRITE) 1905 s->dma_dac2.subdivision = val; 1906 return 0; 1907 1908 case SOUND_PCM_READ_RATE: 1909 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p); 1910 1911 case SOUND_PCM_READ_CHANNELS: 1912 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p); 1913 1914 case SOUND_PCM_READ_BITS: 1915 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ? 16 : 8, p); 1916 1917 case SOUND_PCM_WRITE_FILTER: 1918 case SNDCTL_DSP_SETSYNCRO: 1919 case SOUND_PCM_READ_FILTER: 1920 return -EINVAL; 1921 1922 } 1923 return mixdev_ioctl(s->codec, cmd, arg); 1924} 1925 1926static int es1371_open(struct inode *inode, struct file *file) 1927{ 1928 int minor = iminor(inode); 1929 DECLARE_WAITQUEUE(wait, current); 1930 unsigned long flags; 1931 struct list_head *list; 1932 struct es1371_state *s; 1933 1934 for (list = devs.next; ; list = list->next) { 1935 if (list == &devs) 1936 return -ENODEV; 1937 s = list_entry(list, struct es1371_state, devs); 1938 if (!((s->dev_audio ^ minor) & ~0xf)) 1939 break; 1940 } 1941 VALIDATE_STATE(s); 1942 file->private_data = s; 1943 /* wait for device to become free */ 1944 mutex_lock(&s->open_mutex); 1945 while (s->open_mode & file->f_mode) { 1946 if (file->f_flags & O_NONBLOCK) { 1947 mutex_unlock(&s->open_mutex); 1948 return -EBUSY; 1949 } 1950 add_wait_queue(&s->open_wait, &wait); 1951 __set_current_state(TASK_INTERRUPTIBLE); 1952 mutex_unlock(&s->open_mutex); 1953 schedule(); 1954 remove_wait_queue(&s->open_wait, &wait); 1955 set_current_state(TASK_RUNNING); 1956 if (signal_pending(current)) 1957 return -ERESTARTSYS; 1958 mutex_lock(&s->open_mutex); 1959 } 1960 if (file->f_mode & FMODE_READ) { 1961 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0; 1962 s->dma_adc.enabled = 1; 1963 set_adc_rate(s, 8000); 1964 } 1965 if (file->f_mode & FMODE_WRITE) { 1966 s->dma_dac2.ossfragshift = s->dma_dac2.ossmaxfrags = s->dma_dac2.subdivision = 0; 1967 s->dma_dac2.enabled = 1; 1968 set_dac2_rate(s, 8000); 1969 } 1970 spin_lock_irqsave(&s->lock, flags); 1971 if (file->f_mode & FMODE_READ) { 1972 s->sctrl &= ~SCTRL_R1FMT; 1973 if ((minor & 0xf) == SND_DEV_DSP16) 1974 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_R1FMT; 1975 else 1976 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_R1FMT; 1977 } 1978 if (file->f_mode & FMODE_WRITE) { 1979 s->sctrl &= ~SCTRL_P2FMT; 1980 if ((minor & 0xf) == SND_DEV_DSP16) 1981 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P2FMT; 1982 else 1983 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P2FMT; 1984 } 1985 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 1986 spin_unlock_irqrestore(&s->lock, flags); 1987 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE); 1988 mutex_unlock(&s->open_mutex); 1989 mutex_init(&s->sem); 1990 return nonseekable_open(inode, file); 1991} 1992 1993static int es1371_release(struct inode *inode, struct file *file) 1994{ 1995 struct es1371_state *s = (struct es1371_state *)file->private_data; 1996 1997 VALIDATE_STATE(s); 1998 lock_kernel(); 1999 if (file->f_mode & FMODE_WRITE) 2000 drain_dac2(s, file->f_flags & O_NONBLOCK); 2001 mutex_lock(&s->open_mutex); 2002 if (file->f_mode & FMODE_WRITE) { 2003 stop_dac2(s); 2004 dealloc_dmabuf(s, &s->dma_dac2); 2005 } 2006 if (file->f_mode & FMODE_READ) { 2007 stop_adc(s); 2008 dealloc_dmabuf(s, &s->dma_adc); 2009 } 2010 s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE)); 2011 mutex_unlock(&s->open_mutex); 2012 wake_up(&s->open_wait); 2013 unlock_kernel(); 2014 return 0; 2015} 2016 2017static /*const*/ struct file_operations es1371_audio_fops = { 2018 .owner = THIS_MODULE, 2019 .llseek = no_llseek, 2020 .read = es1371_read, 2021 .write = es1371_write, 2022 .poll = es1371_poll, 2023 .ioctl = es1371_ioctl, 2024 .mmap = es1371_mmap, 2025 .open = es1371_open, 2026 .release = es1371_release, 2027}; 2028 2029/* --------------------------------------------------------------------- */ 2030 2031static ssize_t es1371_write_dac(struct file *file, const char __user *buffer, size_t count, loff_t *ppos) 2032{ 2033 struct es1371_state *s = (struct es1371_state *)file->private_data; 2034 DECLARE_WAITQUEUE(wait, current); 2035 ssize_t ret = 0; 2036 unsigned long flags; 2037 unsigned swptr; 2038 int cnt; 2039 2040 VALIDATE_STATE(s); 2041 if (s->dma_dac1.mapped) 2042 return -ENXIO; 2043 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s))) 2044 return ret; 2045 if (!access_ok(VERIFY_READ, buffer, count)) 2046 return -EFAULT; 2047 add_wait_queue(&s->dma_dac1.wait, &wait); 2048 while (count > 0) { 2049 spin_lock_irqsave(&s->lock, flags); 2050 if (s->dma_dac1.count < 0) { 2051 s->dma_dac1.count = 0; 2052 s->dma_dac1.swptr = s->dma_dac1.hwptr; 2053 } 2054 swptr = s->dma_dac1.swptr; 2055 cnt = s->dma_dac1.dmasize-swptr; 2056 if (s->dma_dac1.count + cnt > s->dma_dac1.dmasize) 2057 cnt = s->dma_dac1.dmasize - s->dma_dac1.count; 2058 if (cnt <= 0) 2059 __set_current_state(TASK_INTERRUPTIBLE); 2060 spin_unlock_irqrestore(&s->lock, flags); 2061 if (cnt > count) 2062 cnt = count; 2063 if (cnt <= 0) { 2064 if (s->dma_dac1.enabled) 2065 start_dac1(s); 2066 if (file->f_flags & O_NONBLOCK) { 2067 if (!ret) 2068 ret = -EAGAIN; 2069 break; 2070 } 2071 schedule(); 2072 if (signal_pending(current)) { 2073 if (!ret) 2074 ret = -ERESTARTSYS; 2075 break; 2076 } 2077 continue; 2078 } 2079 if (copy_from_user(s->dma_dac1.rawbuf + swptr, buffer, cnt)) { 2080 if (!ret) 2081 ret = -EFAULT; 2082 break; 2083 } 2084 swptr = (swptr + cnt) % s->dma_dac1.dmasize; 2085 spin_lock_irqsave(&s->lock, flags); 2086 s->dma_dac1.swptr = swptr; 2087 s->dma_dac1.count += cnt; 2088 s->dma_dac1.endcleared = 0; 2089 spin_unlock_irqrestore(&s->lock, flags); 2090 count -= cnt; 2091 buffer += cnt; 2092 ret += cnt; 2093 if (s->dma_dac1.enabled) 2094 start_dac1(s); 2095 } 2096 remove_wait_queue(&s->dma_dac1.wait, &wait); 2097 set_current_state(TASK_RUNNING); 2098 return ret; 2099} 2100 2101/* No kernel lock - we have our own spinlock */ 2102static unsigned int es1371_poll_dac(struct file *file, struct poll_table_struct *wait) 2103{ 2104 struct es1371_state *s = (struct es1371_state *)file->private_data; 2105 unsigned long flags; 2106 unsigned int mask = 0; 2107 2108 VALIDATE_STATE(s); 2109 if (!s->dma_dac1.ready && prog_dmabuf_dac1(s)) 2110 return 0; 2111 poll_wait(file, &s->dma_dac1.wait, wait); 2112 spin_lock_irqsave(&s->lock, flags); 2113 es1371_update_ptr(s); 2114 if (s->dma_dac1.mapped) { 2115 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize) 2116 mask |= POLLOUT | POLLWRNORM; 2117 } else { 2118 if ((signed)s->dma_dac1.dmasize >= s->dma_dac1.count + (signed)s->dma_dac1.fragsize) 2119 mask |= POLLOUT | POLLWRNORM; 2120 } 2121 spin_unlock_irqrestore(&s->lock, flags); 2122 return mask; 2123} 2124 2125static int es1371_mmap_dac(struct file *file, struct vm_area_struct *vma) 2126{ 2127 struct es1371_state *s = (struct es1371_state *)file->private_data; 2128 int ret; 2129 unsigned long size; 2130 2131 VALIDATE_STATE(s); 2132 if (!(vma->vm_flags & VM_WRITE)) 2133 return -EINVAL; 2134 lock_kernel(); 2135 if ((ret = prog_dmabuf_dac1(s)) != 0) 2136 goto out; 2137 ret = -EINVAL; 2138 if (vma->vm_pgoff != 0) 2139 goto out; 2140 size = vma->vm_end - vma->vm_start; 2141 if (size > (PAGE_SIZE << s->dma_dac1.buforder)) 2142 goto out; 2143 ret = -EAGAIN; 2144 if (remap_pfn_range(vma, vma->vm_start, 2145 virt_to_phys(s->dma_dac1.rawbuf) >> PAGE_SHIFT, 2146 size, vma->vm_page_prot)) 2147 goto out; 2148 s->dma_dac1.mapped = 1; 2149 ret = 0; 2150out: 2151 unlock_kernel(); 2152 return ret; 2153} 2154 2155static int es1371_ioctl_dac(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) 2156{ 2157 struct es1371_state *s = (struct es1371_state *)file->private_data; 2158 unsigned long flags; 2159 audio_buf_info abinfo; 2160 count_info cinfo; 2161 int count; 2162 int val, ret; 2163 int __user *p = (int __user *)arg; 2164 2165 VALIDATE_STATE(s); 2166 switch (cmd) { 2167 case OSS_GETVERSION: 2168 return put_user(SOUND_VERSION, p); 2169 2170 case SNDCTL_DSP_SYNC: 2171 return drain_dac1(s, 0/*file->f_flags & O_NONBLOCK*/); 2172 2173 case SNDCTL_DSP_SETDUPLEX: 2174 return -EINVAL; 2175 2176 case SNDCTL_DSP_GETCAPS: 2177 return put_user(DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p); 2178 2179 case SNDCTL_DSP_RESET: 2180 stop_dac1(s); 2181 synchronize_irq(s->irq); 2182 s->dma_dac1.swptr = s->dma_dac1.hwptr = s->dma_dac1.count = s->dma_dac1.total_bytes = 0; 2183 return 0; 2184 2185 case SNDCTL_DSP_SPEED: 2186 if (get_user(val, p)) 2187 return -EFAULT; 2188 if (val >= 0) { 2189 stop_dac1(s); 2190 s->dma_dac1.ready = 0; 2191 set_dac1_rate(s, val); 2192 } 2193 return put_user(s->dac1rate, p); 2194 2195 case SNDCTL_DSP_STEREO: 2196 if (get_user(val, p)) 2197 return -EFAULT; 2198 stop_dac1(s); 2199 s->dma_dac1.ready = 0; 2200 spin_lock_irqsave(&s->lock, flags); 2201 if (val) 2202 s->sctrl |= SCTRL_P1SMB; 2203 else 2204 s->sctrl &= ~SCTRL_P1SMB; 2205 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 2206 spin_unlock_irqrestore(&s->lock, flags); 2207 return 0; 2208 2209 case SNDCTL_DSP_CHANNELS: 2210 if (get_user(val, p)) 2211 return -EFAULT; 2212 if (val != 0) { 2213 stop_dac1(s); 2214 s->dma_dac1.ready = 0; 2215 spin_lock_irqsave(&s->lock, flags); 2216 if (val >= 2) 2217 s->sctrl |= SCTRL_P1SMB; 2218 else 2219 s->sctrl &= ~SCTRL_P1SMB; 2220 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 2221 spin_unlock_irqrestore(&s->lock, flags); 2222 } 2223 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p); 2224 2225 case SNDCTL_DSP_GETFMTS: /* Returns a mask */ 2226 return put_user(AFMT_S16_LE|AFMT_U8, p); 2227 2228 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/ 2229 if (get_user(val, p)) 2230 return -EFAULT; 2231 if (val != AFMT_QUERY) { 2232 stop_dac1(s); 2233 s->dma_dac1.ready = 0; 2234 spin_lock_irqsave(&s->lock, flags); 2235 if (val == AFMT_S16_LE) 2236 s->sctrl |= SCTRL_P1SEB; 2237 else 2238 s->sctrl &= ~SCTRL_P1SEB; 2239 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 2240 spin_unlock_irqrestore(&s->lock, flags); 2241 } 2242 return put_user((s->sctrl & SCTRL_P1SEB) ? AFMT_S16_LE : AFMT_U8, p); 2243 2244 case SNDCTL_DSP_POST: 2245 return 0; 2246 2247 case SNDCTL_DSP_GETTRIGGER: 2248 return put_user((s->ctrl & CTRL_DAC1_EN) ? PCM_ENABLE_OUTPUT : 0, p); 2249 2250 case SNDCTL_DSP_SETTRIGGER: 2251 if (get_user(val, p)) 2252 return -EFAULT; 2253 if (val & PCM_ENABLE_OUTPUT) { 2254 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s))) 2255 return ret; 2256 s->dma_dac1.enabled = 1; 2257 start_dac1(s); 2258 } else { 2259 s->dma_dac1.enabled = 0; 2260 stop_dac1(s); 2261 } 2262 return 0; 2263 2264 case SNDCTL_DSP_GETOSPACE: 2265 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0) 2266 return val; 2267 spin_lock_irqsave(&s->lock, flags); 2268 es1371_update_ptr(s); 2269 abinfo.fragsize = s->dma_dac1.fragsize; 2270 count = s->dma_dac1.count; 2271 if (count < 0) 2272 count = 0; 2273 abinfo.bytes = s->dma_dac1.dmasize - count; 2274 abinfo.fragstotal = s->dma_dac1.numfrag; 2275 abinfo.fragments = abinfo.bytes >> s->dma_dac1.fragshift; 2276 spin_unlock_irqrestore(&s->lock, flags); 2277 return copy_to_user((void __user *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0; 2278 2279 case SNDCTL_DSP_NONBLOCK: 2280 file->f_flags |= O_NONBLOCK; 2281 return 0; 2282 2283 case SNDCTL_DSP_GETODELAY: 2284 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0) 2285 return val; 2286 spin_lock_irqsave(&s->lock, flags); 2287 es1371_update_ptr(s); 2288 count = s->dma_dac1.count; 2289 spin_unlock_irqrestore(&s->lock, flags); 2290 if (count < 0) 2291 count = 0; 2292 return put_user(count, p); 2293 2294 case SNDCTL_DSP_GETOPTR: 2295 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0) 2296 return val; 2297 spin_lock_irqsave(&s->lock, flags); 2298 es1371_update_ptr(s); 2299 cinfo.bytes = s->dma_dac1.total_bytes; 2300 count = s->dma_dac1.count; 2301 if (count < 0) 2302 count = 0; 2303 cinfo.blocks = count >> s->dma_dac1.fragshift; 2304 cinfo.ptr = s->dma_dac1.hwptr; 2305 if (s->dma_dac1.mapped) 2306 s->dma_dac1.count &= s->dma_dac1.fragsize-1; 2307 spin_unlock_irqrestore(&s->lock, flags); 2308 if (copy_to_user((void __user *)arg, &cinfo, sizeof(cinfo))) 2309 return -EFAULT; 2310 return 0; 2311 2312 case SNDCTL_DSP_GETBLKSIZE: 2313 if ((val = prog_dmabuf_dac1(s))) 2314 return val; 2315 return put_user(s->dma_dac1.fragsize, p); 2316 2317 case SNDCTL_DSP_SETFRAGMENT: 2318 if (get_user(val, p)) 2319 return -EFAULT; 2320 s->dma_dac1.ossfragshift = val & 0xffff; 2321 s->dma_dac1.ossmaxfrags = (val >> 16) & 0xffff; 2322 if (s->dma_dac1.ossfragshift < 4) 2323 s->dma_dac1.ossfragshift = 4; 2324 if (s->dma_dac1.ossfragshift > 15) 2325 s->dma_dac1.ossfragshift = 15; 2326 if (s->dma_dac1.ossmaxfrags < 4) 2327 s->dma_dac1.ossmaxfrags = 4; 2328 return 0; 2329 2330 case SNDCTL_DSP_SUBDIVIDE: 2331 if (s->dma_dac1.subdivision) 2332 return -EINVAL; 2333 if (get_user(val, p)) 2334 return -EFAULT; 2335 if (val != 1 && val != 2 && val != 4) 2336 return -EINVAL; 2337 s->dma_dac1.subdivision = val; 2338 return 0; 2339 2340 case SOUND_PCM_READ_RATE: 2341 return put_user(s->dac1rate, p); 2342 2343 case SOUND_PCM_READ_CHANNELS: 2344 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p); 2345 2346 case SOUND_PCM_READ_BITS: 2347 return put_user((s->sctrl & SCTRL_P1SEB) ? 16 : 8, p); 2348 2349 case SOUND_PCM_WRITE_FILTER: 2350 case SNDCTL_DSP_SETSYNCRO: 2351 case SOUND_PCM_READ_FILTER: 2352 return -EINVAL; 2353 2354 } 2355 return mixdev_ioctl(s->codec, cmd, arg); 2356} 2357 2358static int es1371_open_dac(struct inode *inode, struct file *file) 2359{ 2360 int minor = iminor(inode); 2361 DECLARE_WAITQUEUE(wait, current); 2362 unsigned long flags; 2363 struct list_head *list; 2364 struct es1371_state *s; 2365 2366 for (list = devs.next; ; list = list->next) { 2367 if (list == &devs) 2368 return -ENODEV; 2369 s = list_entry(list, struct es1371_state, devs); 2370 if (!((s->dev_dac ^ minor) & ~0xf)) 2371 break; 2372 } 2373 VALIDATE_STATE(s); 2374 /* we allow opening with O_RDWR, most programs do it although they will only write */ 2375 if (!(file->f_mode & FMODE_WRITE)) 2376 return -EINVAL; 2377 file->private_data = s; 2378 /* wait for device to become free */ 2379 mutex_lock(&s->open_mutex); 2380 while (s->open_mode & FMODE_DAC) { 2381 if (file->f_flags & O_NONBLOCK) { 2382 mutex_unlock(&s->open_mutex); 2383 return -EBUSY; 2384 } 2385 add_wait_queue(&s->open_wait, &wait); 2386 __set_current_state(TASK_INTERRUPTIBLE); 2387 mutex_unlock(&s->open_mutex); 2388 schedule(); 2389 remove_wait_queue(&s->open_wait, &wait); 2390 set_current_state(TASK_RUNNING); 2391 if (signal_pending(current)) 2392 return -ERESTARTSYS; 2393 mutex_lock(&s->open_mutex); 2394 } 2395 s->dma_dac1.ossfragshift = s->dma_dac1.ossmaxfrags = s->dma_dac1.subdivision = 0; 2396 s->dma_dac1.enabled = 1; 2397 set_dac1_rate(s, 8000); 2398 spin_lock_irqsave(&s->lock, flags); 2399 s->sctrl &= ~SCTRL_P1FMT; 2400 if ((minor & 0xf) == SND_DEV_DSP16) 2401 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P1FMT; 2402 else 2403 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P1FMT; 2404 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 2405 spin_unlock_irqrestore(&s->lock, flags); 2406 s->open_mode |= FMODE_DAC; 2407 mutex_unlock(&s->open_mutex); 2408 return nonseekable_open(inode, file); 2409} 2410 2411static int es1371_release_dac(struct inode *inode, struct file *file) 2412{ 2413 struct es1371_state *s = (struct es1371_state *)file->private_data; 2414 2415 VALIDATE_STATE(s); 2416 lock_kernel(); 2417 drain_dac1(s, file->f_flags & O_NONBLOCK); 2418 mutex_lock(&s->open_mutex); 2419 stop_dac1(s); 2420 dealloc_dmabuf(s, &s->dma_dac1); 2421 s->open_mode &= ~FMODE_DAC; 2422 mutex_unlock(&s->open_mutex); 2423 wake_up(&s->open_wait); 2424 unlock_kernel(); 2425 return 0; 2426} 2427 2428static /*const*/ struct file_operations es1371_dac_fops = { 2429 .owner = THIS_MODULE, 2430 .llseek = no_llseek, 2431 .write = es1371_write_dac, 2432 .poll = es1371_poll_dac, 2433 .ioctl = es1371_ioctl_dac, 2434 .mmap = es1371_mmap_dac, 2435 .open = es1371_open_dac, 2436 .release = es1371_release_dac, 2437}; 2438 2439/* --------------------------------------------------------------------- */ 2440 2441static ssize_t es1371_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos) 2442{ 2443 struct es1371_state *s = (struct es1371_state *)file->private_data; 2444 DECLARE_WAITQUEUE(wait, current); 2445 ssize_t ret; 2446 unsigned long flags; 2447 unsigned ptr; 2448 int cnt; 2449 2450 VALIDATE_STATE(s); 2451 if (!access_ok(VERIFY_WRITE, buffer, count)) 2452 return -EFAULT; 2453 if (count == 0) 2454 return 0; 2455 ret = 0; 2456 add_wait_queue(&s->midi.iwait, &wait); 2457 while (count > 0) { 2458 spin_lock_irqsave(&s->lock, flags); 2459 ptr = s->midi.ird; 2460 cnt = MIDIINBUF - ptr; 2461 if (s->midi.icnt < cnt) 2462 cnt = s->midi.icnt; 2463 if (cnt <= 0) 2464 __set_current_state(TASK_INTERRUPTIBLE); 2465 spin_unlock_irqrestore(&s->lock, flags); 2466 if (cnt > count) 2467 cnt = count; 2468 if (cnt <= 0) { 2469 if (file->f_flags & O_NONBLOCK) { 2470 if (!ret) 2471 ret = -EAGAIN; 2472 break; 2473 } 2474 schedule(); 2475 if (signal_pending(current)) { 2476 if (!ret) 2477 ret = -ERESTARTSYS; 2478 break; 2479 } 2480 continue; 2481 } 2482 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) { 2483 if (!ret) 2484 ret = -EFAULT; 2485 break; 2486 } 2487 ptr = (ptr + cnt) % MIDIINBUF; 2488 spin_lock_irqsave(&s->lock, flags); 2489 s->midi.ird = ptr; 2490 s->midi.icnt -= cnt; 2491 spin_unlock_irqrestore(&s->lock, flags); 2492 count -= cnt; 2493 buffer += cnt; 2494 ret += cnt; 2495 break; 2496 } 2497 __set_current_state(TASK_RUNNING); 2498 remove_wait_queue(&s->midi.iwait, &wait); 2499 return ret; 2500} 2501 2502static ssize_t es1371_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos) 2503{ 2504 struct es1371_state *s = (struct es1371_state *)file->private_data; 2505 DECLARE_WAITQUEUE(wait, current); 2506 ssize_t ret; 2507 unsigned long flags; 2508 unsigned ptr; 2509 int cnt; 2510 2511 VALIDATE_STATE(s); 2512 if (!access_ok(VERIFY_READ, buffer, count)) 2513 return -EFAULT; 2514 if (count == 0) 2515 return 0; 2516 ret = 0; 2517 add_wait_queue(&s->midi.owait, &wait); 2518 while (count > 0) { 2519 spin_lock_irqsave(&s->lock, flags); 2520 ptr = s->midi.owr; 2521 cnt = MIDIOUTBUF - ptr; 2522 if (s->midi.ocnt + cnt > MIDIOUTBUF) 2523 cnt = MIDIOUTBUF - s->midi.ocnt; 2524 if (cnt <= 0) { 2525 __set_current_state(TASK_INTERRUPTIBLE); 2526 es1371_handle_midi(s); 2527 } 2528 spin_unlock_irqrestore(&s->lock, flags); 2529 if (cnt > count) 2530 cnt = count; 2531 if (cnt <= 0) { 2532 if (file->f_flags & O_NONBLOCK) { 2533 if (!ret) 2534 ret = -EAGAIN; 2535 break; 2536 } 2537 schedule(); 2538 if (signal_pending(current)) { 2539 if (!ret) 2540 ret = -ERESTARTSYS; 2541 break; 2542 } 2543 continue; 2544 } 2545 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) { 2546 if (!ret) 2547 ret = -EFAULT; 2548 break; 2549 } 2550 ptr = (ptr + cnt) % MIDIOUTBUF; 2551 spin_lock_irqsave(&s->lock, flags); 2552 s->midi.owr = ptr; 2553 s->midi.ocnt += cnt; 2554 spin_unlock_irqrestore(&s->lock, flags); 2555 count -= cnt; 2556 buffer += cnt; 2557 ret += cnt; 2558 spin_lock_irqsave(&s->lock, flags); 2559 es1371_handle_midi(s); 2560 spin_unlock_irqrestore(&s->lock, flags); 2561 } 2562 __set_current_state(TASK_RUNNING); 2563 remove_wait_queue(&s->midi.owait, &wait); 2564 return ret; 2565} 2566 2567/* No kernel lock - we have our own spinlock */ 2568static unsigned int es1371_midi_poll(struct file *file, struct poll_table_struct *wait) 2569{ 2570 struct es1371_state *s = (struct es1371_state *)file->private_data; 2571 unsigned long flags; 2572 unsigned int mask = 0; 2573 2574 VALIDATE_STATE(s); 2575 if (file->f_mode & FMODE_WRITE) 2576 poll_wait(file, &s->midi.owait, wait); 2577 if (file->f_mode & FMODE_READ) 2578 poll_wait(file, &s->midi.iwait, wait); 2579 spin_lock_irqsave(&s->lock, flags); 2580 if (file->f_mode & FMODE_READ) { 2581 if (s->midi.icnt > 0) 2582 mask |= POLLIN | POLLRDNORM; 2583 } 2584 if (file->f_mode & FMODE_WRITE) { 2585 if (s->midi.ocnt < MIDIOUTBUF) 2586 mask |= POLLOUT | POLLWRNORM; 2587 } 2588 spin_unlock_irqrestore(&s->lock, flags); 2589 return mask; 2590} 2591 2592static int es1371_midi_open(struct inode *inode, struct file *file) 2593{ 2594 int minor = iminor(inode); 2595 DECLARE_WAITQUEUE(wait, current); 2596 unsigned long flags; 2597 struct list_head *list; 2598 struct es1371_state *s; 2599 2600 for (list = devs.next; ; list = list->next) { 2601 if (list == &devs) 2602 return -ENODEV; 2603 s = list_entry(list, struct es1371_state, devs); 2604 if (s->dev_midi == minor) 2605 break; 2606 } 2607 VALIDATE_STATE(s); 2608 file->private_data = s; 2609 /* wait for device to become free */ 2610 mutex_lock(&s->open_mutex); 2611 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) { 2612 if (file->f_flags & O_NONBLOCK) { 2613 mutex_unlock(&s->open_mutex); 2614 return -EBUSY; 2615 } 2616 add_wait_queue(&s->open_wait, &wait); 2617 __set_current_state(TASK_INTERRUPTIBLE); 2618 mutex_unlock(&s->open_mutex); 2619 schedule(); 2620 remove_wait_queue(&s->open_wait, &wait); 2621 set_current_state(TASK_RUNNING); 2622 if (signal_pending(current)) 2623 return -ERESTARTSYS; 2624 mutex_lock(&s->open_mutex); 2625 } 2626 spin_lock_irqsave(&s->lock, flags); 2627 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) { 2628 s->midi.ird = s->midi.iwr = s->midi.icnt = 0; 2629 s->midi.ord = s->midi.owr = s->midi.ocnt = 0; 2630 outb(UCTRL_CNTRL_SWR, s->io+ES1371_REG_UART_CONTROL); 2631 outb(0, s->io+ES1371_REG_UART_CONTROL); 2632 outb(0, s->io+ES1371_REG_UART_TEST); 2633 } 2634 if (file->f_mode & FMODE_READ) { 2635 s->midi.ird = s->midi.iwr = s->midi.icnt = 0; 2636 } 2637 if (file->f_mode & FMODE_WRITE) { 2638 s->midi.ord = s->midi.owr = s->midi.ocnt = 0; 2639 } 2640 s->ctrl |= CTRL_UART_EN; 2641 outl(s->ctrl, s->io+ES1371_REG_CONTROL); 2642 es1371_handle_midi(s); 2643 spin_unlock_irqrestore(&s->lock, flags); 2644 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE); 2645 mutex_unlock(&s->open_mutex); 2646 return nonseekable_open(inode, file); 2647} 2648 2649static int es1371_midi_release(struct inode *inode, struct file *file) 2650{ 2651 struct es1371_state *s = (struct es1371_state *)file->private_data; 2652 DECLARE_WAITQUEUE(wait, current); 2653 unsigned long flags; 2654 unsigned count, tmo; 2655 2656 VALIDATE_STATE(s); 2657 lock_kernel(); 2658 if (file->f_mode & FMODE_WRITE) { 2659 add_wait_queue(&s->midi.owait, &wait); 2660 for (;;) { 2661 __set_current_state(TASK_INTERRUPTIBLE); 2662 spin_lock_irqsave(&s->lock, flags); 2663 count = s->midi.ocnt; 2664 spin_unlock_irqrestore(&s->lock, flags); 2665 if (count <= 0) 2666 break; 2667 if (signal_pending(current)) 2668 break; 2669 if (file->f_flags & O_NONBLOCK) 2670 break; 2671 tmo = (count * HZ) / 3100; 2672 if (!schedule_timeout(tmo ? : 1) && tmo) 2673 printk(KERN_DEBUG PFX "midi timed out??\n"); 2674 } 2675 remove_wait_queue(&s->midi.owait, &wait); 2676 set_current_state(TASK_RUNNING); 2677 } 2678 mutex_lock(&s->open_mutex); 2679 s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE)); 2680 spin_lock_irqsave(&s->lock, flags); 2681 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) { 2682 s->ctrl &= ~CTRL_UART_EN; 2683 outl(s->ctrl, s->io+ES1371_REG_CONTROL); 2684 } 2685 spin_unlock_irqrestore(&s->lock, flags); 2686 mutex_unlock(&s->open_mutex); 2687 wake_up(&s->open_wait); 2688 unlock_kernel(); 2689 return 0; 2690} 2691 2692static /*const*/ struct file_operations es1371_midi_fops = { 2693 .owner = THIS_MODULE, 2694 .llseek = no_llseek, 2695 .read = es1371_midi_read, 2696 .write = es1371_midi_write, 2697 .poll = es1371_midi_poll, 2698 .open = es1371_midi_open, 2699 .release = es1371_midi_release, 2700}; 2701 2702/* --------------------------------------------------------------------- */ 2703 2704/* 2705 * for debugging purposes, we'll create a proc device that dumps the 2706 * CODEC chipstate 2707 */ 2708 2709#ifdef ES1371_DEBUG 2710static int proc_es1371_dump (char *buf, char **start, off_t fpos, int length, int *eof, void *data) 2711{ 2712 struct es1371_state *s; 2713 int cnt, len = 0; 2714 2715 if (list_empty(&devs)) 2716 return 0; 2717 s = list_entry(devs.next, struct es1371_state, devs); 2718 /* print out header */ 2719 len += sprintf(buf + len, "\t\tCreative ES137x Debug Dump-o-matic\n"); 2720 2721 /* print out CODEC state */ 2722 len += sprintf (buf + len, "AC97 CODEC state\n"); 2723 for (cnt=0; cnt <= 0x7e; cnt = cnt +2) 2724 len+= sprintf (buf + len, "reg:0x%02x val:0x%04x\n", cnt, rdcodec(s->codec, cnt)); 2725 2726 if (fpos >=len){ 2727 *start = buf; 2728 *eof =1; 2729 return 0; 2730 } 2731 *start = buf + fpos; 2732 if ((len -= fpos) > length) 2733 return length; 2734 *eof =1; 2735 return len; 2736 2737} 2738#endif /* ES1371_DEBUG */ 2739 2740/* --------------------------------------------------------------------- */ 2741 2742/* maximum number of devices; only used for command line params */ 2743#define NR_DEVICE 5 2744 2745static int spdif[NR_DEVICE]; 2746static int nomix[NR_DEVICE]; 2747static int amplifier[NR_DEVICE]; 2748 2749static unsigned int devindex; 2750 2751module_param_array(spdif, bool, NULL, 0); 2752MODULE_PARM_DESC(spdif, "if 1 the output is in S/PDIF digital mode"); 2753module_param_array(nomix, bool, NULL, 0); 2754MODULE_PARM_DESC(nomix, "if 1 no analog audio is mixed to the digital output"); 2755module_param_array(amplifier, bool, NULL, 0); 2756MODULE_PARM_DESC(amplifier, "Set to 1 if the machine needs the amp control enabling (many laptops)"); 2757 2758MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu"); 2759MODULE_DESCRIPTION("ES1371 AudioPCI97 Driver"); 2760MODULE_LICENSE("GPL"); 2761 2762 2763/* --------------------------------------------------------------------- */ 2764 2765static struct initvol { 2766 int mixch; 2767 int vol; 2768} initvol[] __devinitdata = { 2769 { SOUND_MIXER_WRITE_LINE, 0x4040 }, 2770 { SOUND_MIXER_WRITE_CD, 0x4040 }, 2771 { MIXER_WRITE(SOUND_MIXER_VIDEO), 0x4040 }, 2772 { SOUND_MIXER_WRITE_LINE1, 0x4040 }, 2773 { SOUND_MIXER_WRITE_PCM, 0x4040 }, 2774 { SOUND_MIXER_WRITE_VOLUME, 0x4040 }, 2775 { MIXER_WRITE(SOUND_MIXER_PHONEOUT), 0x4040 }, 2776 { SOUND_MIXER_WRITE_OGAIN, 0x4040 }, 2777 { MIXER_WRITE(SOUND_MIXER_PHONEIN), 0x4040 }, 2778 { SOUND_MIXER_WRITE_SPEAKER, 0x4040 }, 2779 { SOUND_MIXER_WRITE_MIC, 0x4040 }, 2780 { SOUND_MIXER_WRITE_RECLEV, 0x4040 }, 2781 { SOUND_MIXER_WRITE_IGAIN, 0x4040 } 2782}; 2783 2784static struct 2785{ 2786 short svid, sdid; 2787} amplifier_needed[] = 2788{ 2789 { 0x107B, 0x2150 }, /* Gateway Solo 2150 */ 2790 { 0x13BD, 0x100C }, /* Mebius PC-MJ100V */ 2791 { 0x1102, 0x5938 }, /* Targa Xtender 300 */ 2792 { 0x1102, 0x8938 }, /* IPC notebook */ 2793 { PCI_ANY_ID, PCI_ANY_ID } 2794}; 2795 2796#ifdef SUPPORT_JOYSTICK 2797 2798static int __devinit es1371_register_gameport(struct es1371_state *s) 2799{ 2800 struct gameport *gp; 2801 int gpio; 2802 2803 for (gpio = 0x218; gpio >= 0x200; gpio -= 0x08) 2804 if (request_region(gpio, JOY_EXTENT, "es1371")) 2805 break; 2806 2807 if (gpio < 0x200) { 2808 printk(KERN_ERR PFX "no free joystick address found\n"); 2809 return -EBUSY; 2810 } 2811 2812 s->gameport = gp = gameport_allocate_port(); 2813 if (!gp) { 2814 printk(KERN_ERR PFX "can not allocate memory for gameport\n"); 2815 release_region(gpio, JOY_EXTENT); 2816 return -ENOMEM; 2817 } 2818 2819 gameport_set_name(gp, "ESS1371 Gameport"); 2820 gameport_set_phys(gp, "isa%04x/gameport0", gpio); 2821 gp->dev.parent = &s->dev->dev; 2822 gp->io = gpio; 2823 2824 s->ctrl |= CTRL_JYSTK_EN | (((gpio >> 3) & CTRL_JOY_MASK) << CTRL_JOY_SHIFT); 2825 outl(s->ctrl, s->io + ES1371_REG_CONTROL); 2826 2827 gameport_register_port(gp); 2828 2829 return 0; 2830} 2831 2832static inline void es1371_unregister_gameport(struct es1371_state *s) 2833{ 2834 if (s->gameport) { 2835 int gpio = s->gameport->io; 2836 gameport_unregister_port(s->gameport); 2837 release_region(gpio, JOY_EXTENT); 2838 2839 } 2840} 2841 2842#else 2843static inline int es1371_register_gameport(struct es1371_state *s) { return -ENOSYS; } 2844static inline void es1371_unregister_gameport(struct es1371_state *s) { } 2845#endif /* SUPPORT_JOYSTICK */ 2846 2847 2848static int __devinit es1371_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid) 2849{ 2850 struct es1371_state *s; 2851 mm_segment_t fs; 2852 int i, val, res = -1; 2853 int idx; 2854 unsigned long tmo; 2855 signed long tmo2; 2856 unsigned int cssr; 2857 2858 if ((res=pci_enable_device(pcidev))) 2859 return res; 2860 2861 if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO)) 2862 return -ENODEV; 2863 if (pcidev->irq == 0) 2864 return -ENODEV; 2865 i = pci_set_dma_mask(pcidev, DMA_32BIT_MASK); 2866 if (i) { 2867 printk(KERN_WARNING "es1371: architecture does not support 32bit PCI busmaster DMA\n"); 2868 return i; 2869 } 2870 if (!(s = kzalloc(sizeof(struct es1371_state), GFP_KERNEL))) { 2871 printk(KERN_WARNING PFX "out of memory\n"); 2872 return -ENOMEM; 2873 } 2874 2875 s->codec = ac97_alloc_codec(); 2876 if(s->codec == NULL) 2877 goto err_codec; 2878 2879 init_waitqueue_head(&s->dma_adc.wait); 2880 init_waitqueue_head(&s->dma_dac1.wait); 2881 init_waitqueue_head(&s->dma_dac2.wait); 2882 init_waitqueue_head(&s->open_wait); 2883 init_waitqueue_head(&s->midi.iwait); 2884 init_waitqueue_head(&s->midi.owait); 2885 mutex_init(&s->open_mutex); 2886 spin_lock_init(&s->lock); 2887 s->magic = ES1371_MAGIC; 2888 s->dev = pcidev; 2889 s->io = pci_resource_start(pcidev, 0); 2890 s->irq = pcidev->irq; 2891 s->vendor = pcidev->vendor; 2892 s->device = pcidev->device; 2893 pci_read_config_byte(pcidev, PCI_REVISION_ID, &s->rev); 2894 s->codec->private_data = s; 2895 s->codec->id = 0; 2896 s->codec->codec_read = rdcodec; 2897 s->codec->codec_write = wrcodec; 2898 printk(KERN_INFO PFX "found chip, vendor id 0x%04x device id 0x%04x revision 0x%02x\n", 2899 s->vendor, s->device, s->rev); 2900 if (!request_region(s->io, ES1371_EXTENT, "es1371")) { 2901 printk(KERN_ERR PFX "io ports %#lx-%#lx in use\n", s->io, s->io+ES1371_EXTENT-1); 2902 res = -EBUSY; 2903 goto err_region; 2904 } 2905 if ((res=request_irq(s->irq, es1371_interrupt, IRQF_SHARED, "es1371",s))) { 2906 printk(KERN_ERR PFX "irq %u in use\n", s->irq); 2907 goto err_irq; 2908 } 2909 printk(KERN_INFO PFX "found es1371 rev %d at io %#lx irq %u\n", 2910 s->rev, s->io, s->irq); 2911 /* register devices */ 2912 if ((res=(s->dev_audio = register_sound_dsp(&es1371_audio_fops,-1)))<0) 2913 goto err_dev1; 2914 if ((res=(s->codec->dev_mixer = register_sound_mixer(&es1371_mixer_fops, -1))) < 0) 2915 goto err_dev2; 2916 if ((res=(s->dev_dac = register_sound_dsp(&es1371_dac_fops, -1))) < 0) 2917 goto err_dev3; 2918 if ((res=(s->dev_midi = register_sound_midi(&es1371_midi_fops, -1)))<0 ) 2919 goto err_dev4; 2920#ifdef ES1371_DEBUG 2921 /* initialize the debug proc device */ 2922 s->ps = create_proc_read_entry("es1371",0,NULL,proc_es1371_dump,NULL); 2923#endif /* ES1371_DEBUG */ 2924 2925 /* initialize codec registers */ 2926 s->ctrl = 0; 2927 2928 /* Check amplifier requirements */ 2929 2930 if (amplifier[devindex]) 2931 s->ctrl |= CTRL_GPIO_OUT0; 2932 else for(idx = 0; amplifier_needed[idx].svid != PCI_ANY_ID; idx++) 2933 { 2934 if(pcidev->subsystem_vendor == amplifier_needed[idx].svid && 2935 pcidev->subsystem_device == amplifier_needed[idx].sdid) 2936 { 2937 s->ctrl |= CTRL_GPIO_OUT0; /* turn internal amplifier on */ 2938 printk(KERN_INFO PFX "Enabling internal amplifier.\n"); 2939 } 2940 } 2941 2942 s->sctrl = 0; 2943 cssr = 0; 2944 s->spdif_volume = -1; 2945 /* check to see if s/pdif mode is being requested */ 2946 if (spdif[devindex]) { 2947 if (s->rev >= 4) { 2948 printk(KERN_INFO PFX "enabling S/PDIF output\n"); 2949 s->spdif_volume = 0; 2950 cssr |= STAT_EN_SPDIF; 2951 s->ctrl |= CTRL_SPDIFEN_B; 2952 if (nomix[devindex]) /* don't mix analog inputs to s/pdif output */ 2953 s->ctrl |= CTRL_RECEN_B; 2954 } else { 2955 printk(KERN_ERR PFX "revision %d does not support S/PDIF\n", s->rev); 2956 } 2957 } 2958 /* initialize the chips */ 2959 outl(s->ctrl, s->io+ES1371_REG_CONTROL); 2960 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL); 2961 outl(LEGACY_JFAST, s->io+ES1371_REG_LEGACY); 2962 pci_set_master(pcidev); /* enable bus mastering */ 2963 /* if we are a 5880 turn on the AC97 */ 2964 if (s->vendor == PCI_VENDOR_ID_ENSONIQ && 2965 ((s->device == PCI_DEVICE_ID_ENSONIQ_CT5880 && s->rev >= CT5880REV_CT5880_C) || 2966 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_CT5880_A) || 2967 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_ES1373_8))) { 2968 cssr |= CSTAT_5880_AC97_RST; 2969 outl(cssr, s->io+ES1371_REG_STATUS); 2970 /* need to delay around 20ms(bleech) to give 2971 some CODECs enough time to wakeup */ 2972 tmo = jiffies + (HZ / 50) + 1; 2973 for (;;) { 2974 tmo2 = tmo - jiffies; 2975 if (tmo2 <= 0) 2976 break; 2977 schedule_timeout(tmo2); 2978 } 2979 } 2980 /* AC97 warm reset to start the bitclk */ 2981 outl(s->ctrl | CTRL_SYNCRES, s->io+ES1371_REG_CONTROL); 2982 udelay(2); 2983 outl(s->ctrl, s->io+ES1371_REG_CONTROL); 2984 /* init the sample rate converter */ 2985 src_init(s); 2986 /* codec init */ 2987 if (!ac97_probe_codec(s->codec)) { 2988 res = -ENODEV; 2989 goto err_gp; 2990 } 2991 /* set default values */ 2992 2993 fs = get_fs(); 2994 set_fs(KERNEL_DS); 2995 val = SOUND_MASK_LINE; 2996 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val); 2997 for (i = 0; i < ARRAY_SIZE(initvol); i++) { 2998 val = initvol[i].vol; 2999 mixdev_ioctl(s->codec, initvol[i].mixch, (unsigned long)&val); 3000 } 3001 /* mute master and PCM when in S/PDIF mode */ 3002 if (s->spdif_volume != -1) { 3003 val = 0x0000; 3004 s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_VOLUME, (unsigned long)&val); 3005 s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_PCM, (unsigned long)&val); 3006 } 3007 set_fs(fs); 3008 /* turn on S/PDIF output driver if requested */ 3009 outl(cssr, s->io+ES1371_REG_STATUS); 3010 3011 es1371_register_gameport(s); 3012 3013 /* store it in the driver field */ 3014 pci_set_drvdata(pcidev, s); 3015 /* put it into driver list */ 3016 list_add_tail(&s->devs, &devs); 3017 /* increment devindex */ 3018 if (devindex < NR_DEVICE-1) 3019 devindex++; 3020 return 0; 3021 3022 err_gp: 3023#ifdef ES1371_DEBUG 3024 if (s->ps) 3025 remove_proc_entry("es1371", NULL); 3026#endif 3027 unregister_sound_midi(s->dev_midi); 3028 err_dev4: 3029 unregister_sound_dsp(s->dev_dac); 3030 err_dev3: 3031 unregister_sound_mixer(s->codec->dev_mixer); 3032 err_dev2: 3033 unregister_sound_dsp(s->dev_audio); 3034 err_dev1: 3035 printk(KERN_ERR PFX "cannot register misc device\n"); 3036 free_irq(s->irq, s); 3037 err_irq: 3038 release_region(s->io, ES1371_EXTENT); 3039 err_region: 3040 err_codec: 3041 ac97_release_codec(s->codec); 3042 kfree(s); 3043 return res; 3044} 3045 3046static void __devexit es1371_remove(struct pci_dev *dev) 3047{ 3048 struct es1371_state *s = pci_get_drvdata(dev); 3049 3050 if (!s) 3051 return; 3052 list_del(&s->devs); 3053#ifdef ES1371_DEBUG 3054 if (s->ps) 3055 remove_proc_entry("es1371", NULL); 3056#endif /* ES1371_DEBUG */ 3057 outl(0, s->io+ES1371_REG_CONTROL); /* switch everything off */ 3058 outl(0, s->io+ES1371_REG_SERIAL_CONTROL); /* clear serial interrupts */ 3059 synchronize_irq(s->irq); 3060 free_irq(s->irq, s); 3061 es1371_unregister_gameport(s); 3062 release_region(s->io, ES1371_EXTENT); 3063 unregister_sound_dsp(s->dev_audio); 3064 unregister_sound_mixer(s->codec->dev_mixer); 3065 unregister_sound_dsp(s->dev_dac); 3066 unregister_sound_midi(s->dev_midi); 3067 ac97_release_codec(s->codec); 3068 kfree(s); 3069 pci_set_drvdata(dev, NULL); 3070} 3071 3072static struct pci_device_id id_table[] = { 3073 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 3074 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 3075 { PCI_VENDOR_ID_ECTIVA, PCI_DEVICE_ID_ECTIVA_EV1938, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 3076 { 0, } 3077}; 3078 3079MODULE_DEVICE_TABLE(pci, id_table); 3080 3081static struct pci_driver es1371_driver = { 3082 .name = "es1371", 3083 .id_table = id_table, 3084 .probe = es1371_probe, 3085 .remove = __devexit_p(es1371_remove), 3086}; 3087 3088static int __init init_es1371(void) 3089{ 3090 printk(KERN_INFO PFX "version v0.32 time " __TIME__ " " __DATE__ "\n"); 3091 return pci_register_driver(&es1371_driver); 3092} 3093 3094static void __exit cleanup_es1371(void) 3095{ 3096 printk(KERN_INFO PFX "unloading\n"); 3097 pci_unregister_driver(&es1371_driver); 3098} 3099 3100module_init(init_es1371); 3101module_exit(cleanup_es1371); 3102 3103/* --------------------------------------------------------------------- */ 3104 3105#ifndef MODULE 3106 3107/* format is: es1371=[spdif,[nomix,[amplifier]]] */ 3108 3109static int __init es1371_setup(char *str) 3110{ 3111 static unsigned __initdata nr_dev = 0; 3112 3113 if (nr_dev >= NR_DEVICE) 3114 return 0; 3115 3116 (void) 3117 ((get_option(&str, &spdif[nr_dev]) == 2) 3118 && (get_option(&str, &nomix[nr_dev]) == 2) 3119 && (get_option(&str, &lifier[nr_dev]))); 3120 3121 nr_dev++; 3122 return 1; 3123} 3124 3125__setup("es1371=", es1371_setup); 3126 3127#endif /* MODULE */ 3128