1/* 2 ********************************************************************** 3 * hwaccess.h 4 * Copyright 1999, 2000 Creative Labs, Inc. 5 * 6 ********************************************************************** 7 * 8 * Date Author Summary of changes 9 * ---- ------ ------------------ 10 * October 20, 1999 Bertrand Lee base code release 11 * 12 ********************************************************************** 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public 25 * License along with this program; if not, write to the Free 26 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, 27 * USA. 28 * 29 ********************************************************************** 30 */ 31 32#ifndef _HWACCESS_H 33#define _HWACCESS_H 34 35#include <linux/fs.h> 36#include <linux/sound.h> 37#include <linux/soundcard.h> 38#include <linux/ac97_codec.h> 39#include <linux/pci.h> 40#include <linux/slab.h> 41#include <linux/sched.h> 42#include <asm/io.h> 43 44#include "efxmgr.h" 45#include "passthrough.h" 46#include "midi.h" 47 48#define EMUPAGESIZE 4096 /* don't change */ 49#define NUM_G 64 /* use all channels */ 50#define NUM_FXSENDS 4 /* don't change */ 51/* setting this to other than a power of two may break some applications */ 52#define MAXBUFSIZE 65536 53#define MAXPAGES 8192 54#define BUFMAXPAGES (MAXBUFSIZE / PAGE_SIZE) 55 56#define FLAGS_AVAILABLE 0x0001 57#define FLAGS_READY 0x0002 58 59struct memhandle 60{ 61 dma_addr_t dma_handle; 62 void *addr; 63 u32 size; 64}; 65 66#define DEBUG_LEVEL 2 67 68#ifdef EMU10K1_DEBUG 69# define DPD(level,x,y...) do {if(level <= DEBUG_LEVEL) printk( KERN_NOTICE "emu10k1: %s: %d: " x , __FILE__ , __LINE__ , y );} while(0) 70# define DPF(level,x) do {if(level <= DEBUG_LEVEL) printk( KERN_NOTICE "emu10k1: %s: %d: " x , __FILE__ , __LINE__ );} while(0) 71#else 72# define DPD(level,x,y...) do { } while (0) /* not debugging: nothing */ 73# define DPF(level,x) do { } while (0) 74#endif /* EMU10K1_DEBUG */ 75 76#define ERROR() DPF(1,"error\n") 77 78/* DATA STRUCTURES */ 79 80struct emu10k1_waveout 81{ 82 u32 send_routing[3]; 83 // audigy only: 84 u32 send_routing2[3]; 85 86 u32 send_dcba[3]; 87 // audigy only: 88 u32 send_hgfe[3]; 89}; 90#define ROUTE_PCM 0 91#define ROUTE_PT 1 92#define ROUTE_PCM1 2 93 94#define SEND_MONO 0 95#define SEND_LEFT 1 96#define SEND_RIGHT 2 97 98struct emu10k1_wavein 99{ 100 struct wiinst *ac97; 101 struct wiinst *mic; 102 struct wiinst *fx; 103 104 u8 recsrc; 105 u32 fxwc; 106}; 107 108#define CMD_READ 1 109#define CMD_WRITE 2 110 111struct mixer_private_ioctl { 112 u32 cmd; 113 u32 val[90]; 114}; 115 116/* bogus ioctls numbers to escape from OSS mixer limitations */ 117#define CMD_WRITEFN0 _IOW('D', 0, struct mixer_private_ioctl) 118#define CMD_READFN0 _IOR('D', 1, struct mixer_private_ioctl) 119#define CMD_WRITEPTR _IOW('D', 2, struct mixer_private_ioctl) 120#define CMD_READPTR _IOR('D', 3, struct mixer_private_ioctl) 121#define CMD_SETRECSRC _IOW('D', 4, struct mixer_private_ioctl) 122#define CMD_GETRECSRC _IOR('D', 5, struct mixer_private_ioctl) 123#define CMD_GETVOICEPARAM _IOR('D', 6, struct mixer_private_ioctl) 124#define CMD_SETVOICEPARAM _IOW('D', 7, struct mixer_private_ioctl) 125#define CMD_GETPATCH _IOR('D', 8, struct mixer_private_ioctl) 126#define CMD_GETGPR _IOR('D', 9, struct mixer_private_ioctl) 127#define CMD_GETCTLGPR _IOR('D', 10, struct mixer_private_ioctl) 128#define CMD_SETPATCH _IOW('D', 11, struct mixer_private_ioctl) 129#define CMD_SETGPR _IOW('D', 12, struct mixer_private_ioctl) 130#define CMD_SETCTLGPR _IOW('D', 13, struct mixer_private_ioctl) 131#define CMD_SETGPOUT _IOW('D', 14, struct mixer_private_ioctl) 132#define CMD_GETGPR2OSS _IOR('D', 15, struct mixer_private_ioctl) 133#define CMD_SETGPR2OSS _IOW('D', 16, struct mixer_private_ioctl) 134#define CMD_SETMCH_FX _IOW('D', 17, struct mixer_private_ioctl) 135#define CMD_SETPASSTHROUGH _IOW('D', 18, struct mixer_private_ioctl) 136#define CMD_PRIVATE3_VERSION _IOW('D', 19, struct mixer_private_ioctl) 137#define CMD_AC97_BOOST _IOW('D', 20, struct mixer_private_ioctl) 138 139//up this number when breaking compatibility 140#define PRIVATE3_VERSION 2 141 142struct emu10k1_card 143{ 144 struct list_head list; 145 146 struct memhandle virtualpagetable; 147 struct memhandle tankmem; 148 struct memhandle silentpage; 149 150 spinlock_t lock; 151 152 u8 voicetable[NUM_G]; 153 u16 emupagetable[MAXPAGES]; 154 155 struct list_head timers; 156 u16 timer_delay; 157 spinlock_t timer_lock; 158 159 struct pci_dev *pci_dev; 160 unsigned long iobase; 161 unsigned long length; 162 unsigned short model; 163 unsigned int irq; 164 165 int audio_dev; 166 int audio_dev1; 167 int midi_dev; 168#ifdef EMU10K1_SEQUENCER 169 int seq_dev; 170 struct emu10k1_mididevice *seq_mididev; 171#endif 172 173 struct ac97_codec *ac97; 174 int ac97_supported_mixers; 175 int ac97_stereo_mixers; 176 177 /* Number of first fx voice for multichannel output */ 178 u8 mchannel_fx; 179 struct emu10k1_waveout waveout; 180 struct emu10k1_wavein wavein; 181 struct emu10k1_mpuout *mpuout; 182 struct emu10k1_mpuin *mpuin; 183 184 struct mutex open_sem; 185 mode_t open_mode; 186 wait_queue_head_t open_wait; 187 188 u32 mpuacqcount; // Mpu acquire count 189 u32 has_toslink; // TOSLink detection 190 191 u8 chiprev; /* Chip revision */ 192 u8 is_audigy; 193 u8 is_aps; 194 195 struct patch_manager mgr; 196 struct pt_data pt; 197}; 198 199int emu10k1_addxmgr_alloc(u32, struct emu10k1_card *); 200void emu10k1_addxmgr_free(struct emu10k1_card *, int); 201 202int emu10k1_find_control_gpr(struct patch_manager *, const char *, const char *); 203void emu10k1_set_control_gpr(struct emu10k1_card *, int , s32, int ); 204 205void emu10k1_set_volume_gpr(struct emu10k1_card *, int, s32, int); 206 207 208#define VOL_6BIT 0x40 209#define VOL_5BIT 0x20 210#define VOL_4BIT 0x10 211 212#define TIMEOUT 16384 213 214u32 srToPitch(u32); 215 216extern struct list_head emu10k1_devs; 217 218/* Hardware Abstraction Layer access functions */ 219 220void emu10k1_writefn0(struct emu10k1_card *, u32, u32); 221void emu10k1_writefn0_2(struct emu10k1_card *, u32, u32, int); 222u32 emu10k1_readfn0(struct emu10k1_card *, u32); 223 224void emu10k1_timer_set(struct emu10k1_card *, u16); 225 226void sblive_writeptr(struct emu10k1_card *, u32, u32, u32); 227void sblive_writeptr_tag(struct emu10k1_card *, u32, ...); 228#define TAGLIST_END 0 229 230u32 sblive_readptr(struct emu10k1_card *, u32 , u32 ); 231 232void emu10k1_irq_enable(struct emu10k1_card *, u32); 233void emu10k1_irq_disable(struct emu10k1_card *, u32); 234void emu10k1_clear_stop_on_loop(struct emu10k1_card *, u32); 235 236/* AC97 Codec register access function */ 237u16 emu10k1_ac97_read(struct ac97_codec *, u8); 238void emu10k1_ac97_write(struct ac97_codec *, u8, u16); 239 240/* MPU access function*/ 241int emu10k1_mpu_write_data(struct emu10k1_card *, u8); 242int emu10k1_mpu_read_data(struct emu10k1_card *, u8 *); 243int emu10k1_mpu_reset(struct emu10k1_card *); 244int emu10k1_mpu_acquire(struct emu10k1_card *); 245int emu10k1_mpu_release(struct emu10k1_card *); 246 247#endif /* _HWACCESS_H */ 248