1/* 2 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Documentation: ARM DDI 0173B 11 */ 12#include <linux/module.h> 13#include <linux/delay.h> 14#include <linux/init.h> 15#include <linux/ioport.h> 16#include <linux/device.h> 17#include <linux/spinlock.h> 18#include <linux/interrupt.h> 19#include <linux/err.h> 20#include <linux/amba/bus.h> 21 22#include <asm/io.h> 23#include <asm/irq.h> 24#include <asm/sizes.h> 25 26#include <sound/driver.h> 27#include <sound/core.h> 28#include <sound/initval.h> 29#include <sound/ac97_codec.h> 30#include <sound/pcm.h> 31#include <sound/pcm_params.h> 32 33#include "aaci.h" 34#include "devdma.h" 35 36#define DRIVER_NAME "aaci-pl041" 37 38/* 39 * PM support is not complete. Turn it off. 40 */ 41#undef CONFIG_PM 42 43static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97) 44{ 45 u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num); 46 47 /* 48 * Ensure that the slot 1/2 RX registers are empty. 49 */ 50 v = readl(aaci->base + AACI_SLFR); 51 if (v & SLFR_2RXV) 52 readl(aaci->base + AACI_SL2RX); 53 if (v & SLFR_1RXV) 54 readl(aaci->base + AACI_SL1RX); 55 56 writel(maincr, aaci->base + AACI_MAINCR); 57} 58 59/* 60 * P29: 61 * The recommended use of programming the external codec through slot 1 62 * and slot 2 data is to use the channels during setup routines and the 63 * slot register at any other time. The data written into slot 1, slot 2 64 * and slot 12 registers is transmitted only when their corresponding 65 * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR 66 * register. 67 */ 68static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 69 unsigned short val) 70{ 71 struct aaci *aaci = ac97->private_data; 72 u32 v; 73 int timeout = 5000; 74 75 if (ac97->num >= 4) 76 return; 77 78 mutex_lock(&aaci->ac97_sem); 79 80 aaci_ac97_select_codec(aaci, ac97); 81 82 /* 83 * P54: You must ensure that AACI_SL2TX is always written 84 * to, if required, before data is written to AACI_SL1TX. 85 */ 86 writel(val << 4, aaci->base + AACI_SL2TX); 87 writel(reg << 12, aaci->base + AACI_SL1TX); 88 89 /* 90 * Wait for the transmission of both slots to complete. 91 */ 92 do { 93 v = readl(aaci->base + AACI_SLFR); 94 } while ((v & (SLFR_1TXB|SLFR_2TXB)) && timeout--); 95 96 if (!timeout) 97 dev_err(&aaci->dev->dev, 98 "timeout waiting for write to complete\n"); 99 100 mutex_unlock(&aaci->ac97_sem); 101} 102 103/* 104 * Read an AC'97 register. 105 */ 106static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) 107{ 108 struct aaci *aaci = ac97->private_data; 109 u32 v; 110 int timeout = 5000; 111 int retries = 10; 112 113 if (ac97->num >= 4) 114 return ~0; 115 116 mutex_lock(&aaci->ac97_sem); 117 118 aaci_ac97_select_codec(aaci, ac97); 119 120 /* 121 * Write the register address to slot 1. 122 */ 123 writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); 124 125 /* 126 * Wait for the transmission to complete. 127 */ 128 do { 129 v = readl(aaci->base + AACI_SLFR); 130 } while ((v & SLFR_1TXB) && timeout--); 131 132 if (!timeout) { 133 dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n"); 134 v = ~0; 135 goto out; 136 } 137 138 /* 139 * Give the AC'97 codec more than enough time 140 * to respond. (42us = ~2 frames at 48kHz.) 141 */ 142 udelay(42); 143 144 /* 145 * Wait for slot 2 to indicate data. 146 */ 147 timeout = 5000; 148 do { 149 cond_resched(); 150 v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV); 151 } while ((v != (SLFR_1RXV|SLFR_2RXV)) && timeout--); 152 153 if (!timeout) { 154 dev_err(&aaci->dev->dev, "timeout on RX valid\n"); 155 v = ~0; 156 goto out; 157 } 158 159 do { 160 v = readl(aaci->base + AACI_SL1RX) >> 12; 161 if (v == reg) { 162 v = readl(aaci->base + AACI_SL2RX) >> 4; 163 break; 164 } else if (--retries) { 165 dev_warn(&aaci->dev->dev, 166 "ac97 read back fail. retry\n"); 167 continue; 168 } else { 169 dev_warn(&aaci->dev->dev, 170 "wrong ac97 register read back (%x != %x)\n", 171 v, reg); 172 v = ~0; 173 } 174 } while (retries); 175 out: 176 mutex_unlock(&aaci->ac97_sem); 177 return v; 178} 179 180static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun) 181{ 182 u32 val; 183 int timeout = 5000; 184 185 do { 186 val = readl(aacirun->base + AACI_SR); 187 } while (val & (SR_TXB|SR_RXB) && timeout--); 188} 189 190 191 192/* 193 * Interrupt support. 194 */ 195static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask) 196{ 197 if (mask & ISR_ORINTR) { 198 dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel); 199 writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR); 200 } 201 202 if (mask & ISR_RXTOINTR) { 203 dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel); 204 writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR); 205 } 206 207 if (mask & ISR_RXINTR) { 208 struct aaci_runtime *aacirun = &aaci->capture; 209 void *ptr; 210 211 if (!aacirun->substream || !aacirun->start) { 212 dev_warn(&aaci->dev->dev, "RX interrupt???"); 213 writel(0, aacirun->base + AACI_IE); 214 return; 215 } 216 ptr = aacirun->ptr; 217 218 do { 219 unsigned int len = aacirun->fifosz; 220 u32 val; 221 222 if (aacirun->bytes <= 0) { 223 aacirun->bytes += aacirun->period; 224 aacirun->ptr = ptr; 225 spin_unlock(&aaci->lock); 226 snd_pcm_period_elapsed(aacirun->substream); 227 spin_lock(&aaci->lock); 228 } 229 if (!(aacirun->cr & CR_EN)) 230 break; 231 232 val = readl(aacirun->base + AACI_SR); 233 if (!(val & SR_RXHF)) 234 break; 235 if (!(val & SR_RXFF)) 236 len >>= 1; 237 238 aacirun->bytes -= len; 239 240 /* reading 16 bytes at a time */ 241 for( ; len > 0; len -= 16) { 242 asm( 243 "ldmia %1, {r0, r1, r2, r3}\n\t" 244 "stmia %0!, {r0, r1, r2, r3}" 245 : "+r" (ptr) 246 : "r" (aacirun->fifo) 247 : "r0", "r1", "r2", "r3", "cc"); 248 249 if (ptr >= aacirun->end) 250 ptr = aacirun->start; 251 } 252 } while(1); 253 aacirun->ptr = ptr; 254 } 255 256 if (mask & ISR_URINTR) { 257 dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel); 258 writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR); 259 } 260 261 if (mask & ISR_TXINTR) { 262 struct aaci_runtime *aacirun = &aaci->playback; 263 void *ptr; 264 265 if (!aacirun->substream || !aacirun->start) { 266 dev_warn(&aaci->dev->dev, "TX interrupt???"); 267 writel(0, aacirun->base + AACI_IE); 268 return; 269 } 270 271 ptr = aacirun->ptr; 272 do { 273 unsigned int len = aacirun->fifosz; 274 u32 val; 275 276 if (aacirun->bytes <= 0) { 277 aacirun->bytes += aacirun->period; 278 aacirun->ptr = ptr; 279 spin_unlock(&aaci->lock); 280 snd_pcm_period_elapsed(aacirun->substream); 281 spin_lock(&aaci->lock); 282 } 283 if (!(aacirun->cr & CR_EN)) 284 break; 285 286 val = readl(aacirun->base + AACI_SR); 287 if (!(val & SR_TXHE)) 288 break; 289 if (!(val & SR_TXFE)) 290 len >>= 1; 291 292 aacirun->bytes -= len; 293 294 /* writing 16 bytes at a time */ 295 for ( ; len > 0; len -= 16) { 296 asm( 297 "ldmia %0!, {r0, r1, r2, r3}\n\t" 298 "stmia %1, {r0, r1, r2, r3}" 299 : "+r" (ptr) 300 : "r" (aacirun->fifo) 301 : "r0", "r1", "r2", "r3", "cc"); 302 303 if (ptr >= aacirun->end) 304 ptr = aacirun->start; 305 } 306 } while (1); 307 308 aacirun->ptr = ptr; 309 } 310} 311 312static irqreturn_t aaci_irq(int irq, void *devid) 313{ 314 struct aaci *aaci = devid; 315 u32 mask; 316 int i; 317 318 spin_lock(&aaci->lock); 319 mask = readl(aaci->base + AACI_ALLINTS); 320 if (mask) { 321 u32 m = mask; 322 for (i = 0; i < 4; i++, m >>= 7) { 323 if (m & 0x7f) { 324 aaci_fifo_irq(aaci, i, m); 325 } 326 } 327 } 328 spin_unlock(&aaci->lock); 329 330 return mask ? IRQ_HANDLED : IRQ_NONE; 331} 332 333 334 335/* 336 * ALSA support. 337 */ 338 339struct aaci_stream { 340 unsigned char codec_idx; 341 unsigned char rate_idx; 342}; 343 344static struct aaci_stream aaci_streams[] = { 345 [ACSTREAM_FRONT] = { 346 .codec_idx = 0, 347 .rate_idx = AC97_RATES_FRONT_DAC, 348 }, 349 [ACSTREAM_SURROUND] = { 350 .codec_idx = 0, 351 .rate_idx = AC97_RATES_SURR_DAC, 352 }, 353 [ACSTREAM_LFE] = { 354 .codec_idx = 0, 355 .rate_idx = AC97_RATES_LFE_DAC, 356 }, 357}; 358 359static inline unsigned int aaci_rate_mask(struct aaci *aaci, int streamid) 360{ 361 struct aaci_stream *s = aaci_streams + streamid; 362 return aaci->ac97_bus->codec[s->codec_idx]->rates[s->rate_idx]; 363} 364 365static unsigned int rate_list[] = { 366 5512, 8000, 11025, 16000, 22050, 32000, 44100, 367 48000, 64000, 88200, 96000, 176400, 192000 368}; 369 370/* 371 * Double-rate rule: we can support double rate iff channels == 2 372 * (unimplemented) 373 */ 374static int 375aaci_rule_rate_by_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule) 376{ 377 struct aaci *aaci = rule->private; 378 unsigned int rate_mask = SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_5512; 379 struct snd_interval *c = hw_param_interval(p, SNDRV_PCM_HW_PARAM_CHANNELS); 380 381 switch (c->max) { 382 case 6: 383 rate_mask &= aaci_rate_mask(aaci, ACSTREAM_LFE); 384 case 4: 385 rate_mask &= aaci_rate_mask(aaci, ACSTREAM_SURROUND); 386 case 2: 387 rate_mask &= aaci_rate_mask(aaci, ACSTREAM_FRONT); 388 } 389 390 return snd_interval_list(hw_param_interval(p, rule->var), 391 ARRAY_SIZE(rate_list), rate_list, 392 rate_mask); 393} 394 395static struct snd_pcm_hardware aaci_hw_info = { 396 .info = SNDRV_PCM_INFO_MMAP | 397 SNDRV_PCM_INFO_MMAP_VALID | 398 SNDRV_PCM_INFO_INTERLEAVED | 399 SNDRV_PCM_INFO_BLOCK_TRANSFER | 400 SNDRV_PCM_INFO_RESUME, 401 402 /* 403 * ALSA doesn't support 18-bit or 20-bit packed into 32-bit 404 * words. It also doesn't support 12-bit at all. 405 */ 406 .formats = SNDRV_PCM_FMTBIT_S16_LE, 407 408 /* should this be continuous or knot? */ 409 .rates = SNDRV_PCM_RATE_CONTINUOUS, 410 .rate_max = 48000, 411 .rate_min = 4000, 412 .channels_min = 2, 413 .channels_max = 6, 414 .buffer_bytes_max = 64 * 1024, 415 .period_bytes_min = 256, 416 .period_bytes_max = PAGE_SIZE, 417 .periods_min = 4, 418 .periods_max = PAGE_SIZE / 16, 419}; 420 421static int __aaci_pcm_open(struct aaci *aaci, 422 struct snd_pcm_substream *substream, 423 struct aaci_runtime *aacirun) 424{ 425 struct snd_pcm_runtime *runtime = substream->runtime; 426 int ret; 427 428 aacirun->substream = substream; 429 runtime->private_data = aacirun; 430 runtime->hw = aaci_hw_info; 431 432 runtime->hw.fifo_size = aaci->fifosize * 2; 433 434 /* 435 * Add rule describing hardware rate dependency 436 * on the number of channels. 437 */ 438 ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 439 aaci_rule_rate_by_channels, aaci, 440 SNDRV_PCM_HW_PARAM_CHANNELS, 441 SNDRV_PCM_HW_PARAM_RATE, -1); 442 if (ret) 443 goto out; 444 445 ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED, 446 DRIVER_NAME, aaci); 447 if (ret) 448 goto out; 449 450 return 0; 451 452 out: 453 return ret; 454} 455 456 457/* 458 * Common ALSA stuff 459 */ 460static int aaci_pcm_close(struct snd_pcm_substream *substream) 461{ 462 struct aaci *aaci = substream->private_data; 463 struct aaci_runtime *aacirun = substream->runtime->private_data; 464 465 WARN_ON(aacirun->cr & CR_EN); 466 467 aacirun->substream = NULL; 468 free_irq(aaci->dev->irq[0], aaci); 469 470 return 0; 471} 472 473static int aaci_pcm_hw_free(struct snd_pcm_substream *substream) 474{ 475 struct aaci_runtime *aacirun = substream->runtime->private_data; 476 477 /* 478 * This must not be called with the device enabled. 479 */ 480 WARN_ON(aacirun->cr & CR_EN); 481 482 if (aacirun->pcm_open) 483 snd_ac97_pcm_close(aacirun->pcm); 484 aacirun->pcm_open = 0; 485 486 /* 487 * Clear out the DMA and any allocated buffers. 488 */ 489 devdma_hw_free(NULL, substream); 490 491 return 0; 492} 493 494static int aaci_pcm_hw_params(struct snd_pcm_substream *substream, 495 struct aaci_runtime *aacirun, 496 struct snd_pcm_hw_params *params) 497{ 498 int err; 499 500 aaci_pcm_hw_free(substream); 501 502 err = devdma_hw_alloc(NULL, substream, 503 params_buffer_bytes(params)); 504 if (err < 0) 505 goto out; 506 507 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 508 err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params), 509 params_channels(params), 510 aacirun->pcm->r[0].slots); 511 else 512 err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params), 513 params_channels(params), 514 aacirun->pcm->r[1].slots); 515 516 if (err) 517 goto out; 518 519 aacirun->pcm_open = 1; 520 521 out: 522 return err; 523} 524 525static int aaci_pcm_prepare(struct snd_pcm_substream *substream) 526{ 527 struct snd_pcm_runtime *runtime = substream->runtime; 528 struct aaci_runtime *aacirun = runtime->private_data; 529 530 aacirun->start = (void *)runtime->dma_area; 531 aacirun->end = aacirun->start + runtime->dma_bytes; 532 aacirun->ptr = aacirun->start; 533 aacirun->period = 534 aacirun->bytes = frames_to_bytes(runtime, runtime->period_size); 535 536 return 0; 537} 538 539static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream) 540{ 541 struct snd_pcm_runtime *runtime = substream->runtime; 542 struct aaci_runtime *aacirun = runtime->private_data; 543 ssize_t bytes = aacirun->ptr - aacirun->start; 544 545 return bytes_to_frames(runtime, bytes); 546} 547 548static int aaci_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma) 549{ 550 return devdma_mmap(NULL, substream, vma); 551} 552 553 554/* 555 * Playback specific ALSA stuff 556 */ 557static const u32 channels_to_txmask[] = { 558 [2] = CR_SL3 | CR_SL4, 559 [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8, 560 [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9, 561}; 562 563/* 564 * We can support two and four channel audio. Unfortunately 565 * six channel audio requires a non-standard channel ordering: 566 * 2 -> FL(3), FR(4) 567 * 4 -> FL(3), FR(4), SL(7), SR(8) 568 * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required) 569 * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual) 570 * This requires an ALSA configuration file to correct. 571 */ 572static unsigned int channel_list[] = { 2, 4, 6 }; 573 574static int 575aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule) 576{ 577 struct aaci *aaci = rule->private; 578 unsigned int chan_mask = 1 << 0, slots; 579 580 /* 581 * pcms[0] is the our 5.1 PCM instance. 582 */ 583 slots = aaci->ac97_bus->pcms[0].r[0].slots; 584 if (slots & (1 << AC97_SLOT_PCM_SLEFT)) { 585 chan_mask |= 1 << 1; 586 if (slots & (1 << AC97_SLOT_LFE)) 587 chan_mask |= 1 << 2; 588 } 589 590 return snd_interval_list(hw_param_interval(p, rule->var), 591 ARRAY_SIZE(channel_list), channel_list, 592 chan_mask); 593} 594 595static int aaci_pcm_open(struct snd_pcm_substream *substream) 596{ 597 struct aaci *aaci = substream->private_data; 598 int ret; 599 600 /* 601 * Add rule describing channel dependency. 602 */ 603 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 604 SNDRV_PCM_HW_PARAM_CHANNELS, 605 aaci_rule_channels, aaci, 606 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 607 if (ret) 608 return ret; 609 610 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 611 ret = __aaci_pcm_open(aaci, substream, &aaci->playback); 612 } else { 613 ret = __aaci_pcm_open(aaci, substream, &aaci->capture); 614 } 615 return ret; 616} 617 618static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream, 619 struct snd_pcm_hw_params *params) 620{ 621 struct aaci *aaci = substream->private_data; 622 struct aaci_runtime *aacirun = substream->runtime->private_data; 623 unsigned int channels = params_channels(params); 624 int ret; 625 626 WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) || 627 !channels_to_txmask[channels]); 628 629 ret = aaci_pcm_hw_params(substream, aacirun, params); 630 631 if (ret >= 0) { 632 aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16; 633 aacirun->cr |= channels_to_txmask[channels]; 634 635 aacirun->fifosz = aaci->fifosize * 4; 636 if (aacirun->cr & CR_COMPACT) 637 aacirun->fifosz >>= 1; 638 } 639 return ret; 640} 641 642static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun) 643{ 644 u32 ie; 645 646 ie = readl(aacirun->base + AACI_IE); 647 ie &= ~(IE_URIE|IE_TXIE); 648 writel(ie, aacirun->base + AACI_IE); 649 aacirun->cr &= ~CR_EN; 650 aaci_chan_wait_ready(aacirun); 651 writel(aacirun->cr, aacirun->base + AACI_TXCR); 652} 653 654static void aaci_pcm_playback_start(struct aaci_runtime *aacirun) 655{ 656 u32 ie; 657 658 aaci_chan_wait_ready(aacirun); 659 aacirun->cr |= CR_EN; 660 661 ie = readl(aacirun->base + AACI_IE); 662 ie |= IE_URIE | IE_TXIE; 663 writel(ie, aacirun->base + AACI_IE); 664 writel(aacirun->cr, aacirun->base + AACI_TXCR); 665} 666 667static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd) 668{ 669 struct aaci *aaci = substream->private_data; 670 struct aaci_runtime *aacirun = substream->runtime->private_data; 671 unsigned long flags; 672 int ret = 0; 673 674 spin_lock_irqsave(&aaci->lock, flags); 675 switch (cmd) { 676 case SNDRV_PCM_TRIGGER_START: 677 aaci_pcm_playback_start(aacirun); 678 break; 679 680 case SNDRV_PCM_TRIGGER_RESUME: 681 aaci_pcm_playback_start(aacirun); 682 break; 683 684 case SNDRV_PCM_TRIGGER_STOP: 685 aaci_pcm_playback_stop(aacirun); 686 break; 687 688 case SNDRV_PCM_TRIGGER_SUSPEND: 689 aaci_pcm_playback_stop(aacirun); 690 break; 691 692 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 693 break; 694 695 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 696 break; 697 698 default: 699 ret = -EINVAL; 700 } 701 spin_unlock_irqrestore(&aaci->lock, flags); 702 703 return ret; 704} 705 706static struct snd_pcm_ops aaci_playback_ops = { 707 .open = aaci_pcm_open, 708 .close = aaci_pcm_close, 709 .ioctl = snd_pcm_lib_ioctl, 710 .hw_params = aaci_pcm_playback_hw_params, 711 .hw_free = aaci_pcm_hw_free, 712 .prepare = aaci_pcm_prepare, 713 .trigger = aaci_pcm_playback_trigger, 714 .pointer = aaci_pcm_pointer, 715 .mmap = aaci_pcm_mmap, 716}; 717 718static int aaci_pcm_capture_hw_params(struct snd_pcm_substream *substream, 719 struct snd_pcm_hw_params *params) 720{ 721 struct aaci *aaci = substream->private_data; 722 struct aaci_runtime *aacirun = substream->runtime->private_data; 723 int ret; 724 725 ret = aaci_pcm_hw_params(substream, aacirun, params); 726 727 if (ret >= 0) { 728 aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16; 729 730 /* Line in record: slot 3 and 4 */ 731 aacirun->cr |= CR_SL3 | CR_SL4; 732 733 aacirun->fifosz = aaci->fifosize * 4; 734 735 if (aacirun->cr & CR_COMPACT) 736 aacirun->fifosz >>= 1; 737 } 738 return ret; 739} 740 741static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun) 742{ 743 u32 ie; 744 745 aaci_chan_wait_ready(aacirun); 746 747 ie = readl(aacirun->base + AACI_IE); 748 ie &= ~(IE_ORIE | IE_RXIE); 749 writel(ie, aacirun->base+AACI_IE); 750 751 aacirun->cr &= ~CR_EN; 752 753 writel(aacirun->cr, aacirun->base + AACI_RXCR); 754} 755 756static void aaci_pcm_capture_start(struct aaci_runtime *aacirun) 757{ 758 u32 ie; 759 760 aaci_chan_wait_ready(aacirun); 761 762#ifdef DEBUG 763 /* RX Timeout value: bits 28:17 in RXCR */ 764 aacirun->cr |= 0xf << 17; 765#endif 766 767 aacirun->cr |= CR_EN; 768 writel(aacirun->cr, aacirun->base + AACI_RXCR); 769 770 ie = readl(aacirun->base + AACI_IE); 771 ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full 772 writel(ie, aacirun->base + AACI_IE); 773} 774 775static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd) 776{ 777 struct aaci *aaci = substream->private_data; 778 struct aaci_runtime *aacirun = substream->runtime->private_data; 779 unsigned long flags; 780 int ret = 0; 781 782 spin_lock_irqsave(&aaci->lock, flags); 783 784 switch (cmd) { 785 case SNDRV_PCM_TRIGGER_START: 786 aaci_pcm_capture_start(aacirun); 787 break; 788 789 case SNDRV_PCM_TRIGGER_RESUME: 790 aaci_pcm_capture_start(aacirun); 791 break; 792 793 case SNDRV_PCM_TRIGGER_STOP: 794 aaci_pcm_capture_stop(aacirun); 795 break; 796 797 case SNDRV_PCM_TRIGGER_SUSPEND: 798 aaci_pcm_capture_stop(aacirun); 799 break; 800 801 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 802 break; 803 804 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 805 break; 806 807 default: 808 ret = -EINVAL; 809 } 810 811 spin_unlock_irqrestore(&aaci->lock, flags); 812 813 return ret; 814} 815 816static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream) 817{ 818 struct snd_pcm_runtime *runtime = substream->runtime; 819 struct aaci *aaci = substream->private_data; 820 821 aaci_pcm_prepare(substream); 822 823 /* allow changing of sample rate */ 824 aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */ 825 aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate); 826 aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate); 827 828 /* Record select: Mic: 0, Aux: 3, Line: 4 */ 829 aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404); 830 831 return 0; 832} 833 834static struct snd_pcm_ops aaci_capture_ops = { 835 .open = aaci_pcm_open, 836 .close = aaci_pcm_close, 837 .ioctl = snd_pcm_lib_ioctl, 838 .hw_params = aaci_pcm_capture_hw_params, 839 .hw_free = aaci_pcm_hw_free, 840 .prepare = aaci_pcm_capture_prepare, 841 .trigger = aaci_pcm_capture_trigger, 842 .pointer = aaci_pcm_pointer, 843 .mmap = aaci_pcm_mmap, 844}; 845 846/* 847 * Power Management. 848 */ 849#ifdef CONFIG_PM 850static int aaci_do_suspend(struct snd_card *card, unsigned int state) 851{ 852 struct aaci *aaci = card->private_data; 853 snd_power_change_state(card, SNDRV_CTL_POWER_D3cold); 854 snd_pcm_suspend_all(aaci->pcm); 855 return 0; 856} 857 858static int aaci_do_resume(struct snd_card *card, unsigned int state) 859{ 860 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 861 return 0; 862} 863 864static int aaci_suspend(struct amba_device *dev, pm_message_t state) 865{ 866 struct snd_card *card = amba_get_drvdata(dev); 867 return card ? aaci_do_suspend(card) : 0; 868} 869 870static int aaci_resume(struct amba_device *dev) 871{ 872 struct snd_card *card = amba_get_drvdata(dev); 873 return card ? aaci_do_resume(card) : 0; 874} 875#else 876#define aaci_do_suspend NULL 877#define aaci_do_resume NULL 878#define aaci_suspend NULL 879#define aaci_resume NULL 880#endif 881 882 883static struct ac97_pcm ac97_defs[] __devinitdata = { 884 [0] = { /* Front PCM */ 885 .exclusive = 1, 886 .r = { 887 [0] = { 888 .slots = (1 << AC97_SLOT_PCM_LEFT) | 889 (1 << AC97_SLOT_PCM_RIGHT) | 890 (1 << AC97_SLOT_PCM_CENTER) | 891 (1 << AC97_SLOT_PCM_SLEFT) | 892 (1 << AC97_SLOT_PCM_SRIGHT) | 893 (1 << AC97_SLOT_LFE), 894 }, 895 }, 896 }, 897 [1] = { /* PCM in */ 898 .stream = 1, 899 .exclusive = 1, 900 .r = { 901 [0] = { 902 .slots = (1 << AC97_SLOT_PCM_LEFT) | 903 (1 << AC97_SLOT_PCM_RIGHT), 904 }, 905 }, 906 }, 907 [2] = { /* Mic in */ 908 .stream = 1, 909 .exclusive = 1, 910 .r = { 911 [0] = { 912 .slots = (1 << AC97_SLOT_MIC), 913 }, 914 }, 915 } 916}; 917 918static struct snd_ac97_bus_ops aaci_bus_ops = { 919 .write = aaci_ac97_write, 920 .read = aaci_ac97_read, 921}; 922 923static int __devinit aaci_probe_ac97(struct aaci *aaci) 924{ 925 struct snd_ac97_template ac97_template; 926 struct snd_ac97_bus *ac97_bus; 927 struct snd_ac97 *ac97; 928 int ret; 929 930 /* 931 * Assert AACIRESET for 2us 932 */ 933 writel(0, aaci->base + AACI_RESET); 934 udelay(2); 935 writel(RESET_NRST, aaci->base + AACI_RESET); 936 937 /* 938 * Give the AC'97 codec more than enough time 939 * to wake up. (42us = ~2 frames at 48kHz.) 940 */ 941 udelay(42); 942 943 ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus); 944 if (ret) 945 goto out; 946 947 ac97_bus->clock = 48000; 948 aaci->ac97_bus = ac97_bus; 949 950 memset(&ac97_template, 0, sizeof(struct snd_ac97_template)); 951 ac97_template.private_data = aaci; 952 ac97_template.num = 0; 953 ac97_template.scaps = AC97_SCAP_SKIP_MODEM; 954 955 ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97); 956 if (ret) 957 goto out; 958 aaci->ac97 = ac97; 959 960 /* 961 * Disable AC97 PC Beep input on audio codecs. 962 */ 963 if (ac97_is_audio(ac97)) 964 snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e); 965 966 ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs); 967 if (ret) 968 goto out; 969 970 aaci->playback.pcm = &ac97_bus->pcms[0]; 971 aaci->capture.pcm = &ac97_bus->pcms[1]; 972 973 out: 974 return ret; 975} 976 977static void aaci_free_card(struct snd_card *card) 978{ 979 struct aaci *aaci = card->private_data; 980 if (aaci->base) 981 iounmap(aaci->base); 982} 983 984static struct aaci * __devinit aaci_init_card(struct amba_device *dev) 985{ 986 struct aaci *aaci; 987 struct snd_card *card; 988 989 card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 990 THIS_MODULE, sizeof(struct aaci)); 991 if (card == NULL) 992 return ERR_PTR(-ENOMEM); 993 994 card->private_free = aaci_free_card; 995 996 strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver)); 997 strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname)); 998 snprintf(card->longname, sizeof(card->longname), 999 "%s at 0x%016llx, irq %d", 1000 card->shortname, (unsigned long long)dev->res.start, 1001 dev->irq[0]); 1002 1003 aaci = card->private_data; 1004 mutex_init(&aaci->ac97_sem); 1005 spin_lock_init(&aaci->lock); 1006 aaci->card = card; 1007 aaci->dev = dev; 1008 1009 /* Set MAINCR to allow slot 1 and 2 data IO */ 1010 aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN | 1011 MAINCR_SL2RXEN | MAINCR_SL2TXEN; 1012 1013 return aaci; 1014} 1015 1016static int __devinit aaci_init_pcm(struct aaci *aaci) 1017{ 1018 struct snd_pcm *pcm; 1019 int ret; 1020 1021 ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm); 1022 if (ret == 0) { 1023 aaci->pcm = pcm; 1024 pcm->private_data = aaci; 1025 pcm->info_flags = 0; 1026 1027 strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name)); 1028 1029 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops); 1030 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops); 1031 } 1032 1033 return ret; 1034} 1035 1036static unsigned int __devinit aaci_size_fifo(struct aaci *aaci) 1037{ 1038 struct aaci_runtime *aacirun = &aaci->playback; 1039 int i; 1040 1041 writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR); 1042 1043 for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++) 1044 writel(0, aacirun->fifo); 1045 1046 writel(0, aacirun->base + AACI_TXCR); 1047 1048 /* 1049 * Re-initialise the AACI after the FIFO depth test, to 1050 * ensure that the FIFOs are empty. Unfortunately, merely 1051 * disabling the channel doesn't clear the FIFO. 1052 */ 1053 writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR); 1054 writel(aaci->maincr, aaci->base + AACI_MAINCR); 1055 1056 /* 1057 * If we hit 4096, we failed. Go back to the specified 1058 * fifo depth. 1059 */ 1060 if (i == 4096) 1061 i = 8; 1062 1063 return i; 1064} 1065 1066static int __devinit aaci_probe(struct amba_device *dev, void *id) 1067{ 1068 struct aaci *aaci; 1069 int ret, i; 1070 1071 ret = amba_request_regions(dev, NULL); 1072 if (ret) 1073 return ret; 1074 1075 aaci = aaci_init_card(dev); 1076 if (IS_ERR(aaci)) { 1077 ret = PTR_ERR(aaci); 1078 goto out; 1079 } 1080 1081 aaci->base = ioremap(dev->res.start, SZ_4K); 1082 if (!aaci->base) { 1083 ret = -ENOMEM; 1084 goto out; 1085 } 1086 1087 /* 1088 * Playback uses AACI channel 0 1089 */ 1090 aaci->playback.base = aaci->base + AACI_CSCH1; 1091 aaci->playback.fifo = aaci->base + AACI_DR1; 1092 1093 /* 1094 * Capture uses AACI channel 0 1095 */ 1096 aaci->capture.base = aaci->base + AACI_CSCH1; 1097 aaci->capture.fifo = aaci->base + AACI_DR1; 1098 1099 for (i = 0; i < 4; i++) { 1100 void __iomem *base = aaci->base + i * 0x14; 1101 1102 writel(0, base + AACI_IE); 1103 writel(0, base + AACI_TXCR); 1104 writel(0, base + AACI_RXCR); 1105 } 1106 1107 writel(0x1fff, aaci->base + AACI_INTCLR); 1108 writel(aaci->maincr, aaci->base + AACI_MAINCR); 1109 1110 ret = aaci_probe_ac97(aaci); 1111 if (ret) 1112 goto out; 1113 1114 /* 1115 * Size the FIFOs (must be multiple of 16). 1116 */ 1117 aaci->fifosize = aaci_size_fifo(aaci); 1118 if (aaci->fifosize & 15) { 1119 printk(KERN_WARNING "AACI: fifosize = %d not supported\n", 1120 aaci->fifosize); 1121 ret = -ENODEV; 1122 goto out; 1123 } 1124 1125 ret = aaci_init_pcm(aaci); 1126 if (ret) 1127 goto out; 1128 1129 snd_card_set_dev(aaci->card, &dev->dev); 1130 1131 ret = snd_card_register(aaci->card); 1132 if (ret == 0) { 1133 dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname, 1134 aaci->fifosize); 1135 amba_set_drvdata(dev, aaci->card); 1136 return ret; 1137 } 1138 1139 out: 1140 if (aaci) 1141 snd_card_free(aaci->card); 1142 amba_release_regions(dev); 1143 return ret; 1144} 1145 1146static int __devexit aaci_remove(struct amba_device *dev) 1147{ 1148 struct snd_card *card = amba_get_drvdata(dev); 1149 1150 amba_set_drvdata(dev, NULL); 1151 1152 if (card) { 1153 struct aaci *aaci = card->private_data; 1154 writel(0, aaci->base + AACI_MAINCR); 1155 1156 snd_card_free(card); 1157 amba_release_regions(dev); 1158 } 1159 1160 return 0; 1161} 1162 1163static struct amba_id aaci_ids[] = { 1164 { 1165 .id = 0x00041041, 1166 .mask = 0x000fffff, 1167 }, 1168 { 0, 0 }, 1169}; 1170 1171static struct amba_driver aaci_driver = { 1172 .drv = { 1173 .name = DRIVER_NAME, 1174 }, 1175 .probe = aaci_probe, 1176 .remove = __devexit_p(aaci_remove), 1177 .suspend = aaci_suspend, 1178 .resume = aaci_resume, 1179 .id_table = aaci_ids, 1180}; 1181 1182static int __init aaci_init(void) 1183{ 1184 return amba_driver_register(&aaci_driver); 1185} 1186 1187static void __exit aaci_exit(void) 1188{ 1189 amba_driver_unregister(&aaci_driver); 1190} 1191 1192module_init(aaci_init); 1193module_exit(aaci_exit); 1194 1195MODULE_LICENSE("GPL"); 1196MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver"); 1197