1#ifndef __SOUND_YMFPCI_H 2#define __SOUND_YMFPCI_H 3 4/* 5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz> 6 * Definitions for Yahama YMF724/740/744/754 chips 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 */ 24 25#include "pcm.h" 26#include "rawmidi.h" 27#include "ac97_codec.h" 28#include "timer.h" 29#include <linux/gameport.h> 30 31/* 32 * Direct registers 33 */ 34 35#define YMFREG(chip, reg) (chip->port + YDSXGR_##reg) 36 37#define YDSXGR_INTFLAG 0x0004 38#define YDSXGR_ACTIVITY 0x0006 39#define YDSXGR_GLOBALCTRL 0x0008 40#define YDSXGR_ZVCTRL 0x000A 41#define YDSXGR_TIMERCTRL 0x0010 42#define YDSXGR_TIMERCOUNT 0x0012 43#define YDSXGR_SPDIFOUTCTRL 0x0018 44#define YDSXGR_SPDIFOUTSTATUS 0x001C 45#define YDSXGR_EEPROMCTRL 0x0020 46#define YDSXGR_SPDIFINCTRL 0x0034 47#define YDSXGR_SPDIFINSTATUS 0x0038 48#define YDSXGR_DSPPROGRAMDL 0x0048 49#define YDSXGR_DLCNTRL 0x004C 50#define YDSXGR_GPIOININTFLAG 0x0050 51#define YDSXGR_GPIOININTENABLE 0x0052 52#define YDSXGR_GPIOINSTATUS 0x0054 53#define YDSXGR_GPIOOUTCTRL 0x0056 54#define YDSXGR_GPIOFUNCENABLE 0x0058 55#define YDSXGR_GPIOTYPECONFIG 0x005A 56#define YDSXGR_AC97CMDDATA 0x0060 57#define YDSXGR_AC97CMDADR 0x0062 58#define YDSXGR_PRISTATUSDATA 0x0064 59#define YDSXGR_PRISTATUSADR 0x0066 60#define YDSXGR_SECSTATUSDATA 0x0068 61#define YDSXGR_SECSTATUSADR 0x006A 62#define YDSXGR_SECCONFIG 0x0070 63#define YDSXGR_LEGACYOUTVOL 0x0080 64#define YDSXGR_LEGACYOUTVOLL 0x0080 65#define YDSXGR_LEGACYOUTVOLR 0x0082 66#define YDSXGR_NATIVEDACOUTVOL 0x0084 67#define YDSXGR_NATIVEDACOUTVOLL 0x0084 68#define YDSXGR_NATIVEDACOUTVOLR 0x0086 69#define YDSXGR_ZVOUTVOL 0x0088 70#define YDSXGR_ZVOUTVOLL 0x0088 71#define YDSXGR_ZVOUTVOLR 0x008A 72#define YDSXGR_SECADCOUTVOL 0x008C 73#define YDSXGR_SECADCOUTVOLL 0x008C 74#define YDSXGR_SECADCOUTVOLR 0x008E 75#define YDSXGR_PRIADCOUTVOL 0x0090 76#define YDSXGR_PRIADCOUTVOLL 0x0090 77#define YDSXGR_PRIADCOUTVOLR 0x0092 78#define YDSXGR_LEGACYLOOPVOL 0x0094 79#define YDSXGR_LEGACYLOOPVOLL 0x0094 80#define YDSXGR_LEGACYLOOPVOLR 0x0096 81#define YDSXGR_NATIVEDACLOOPVOL 0x0098 82#define YDSXGR_NATIVEDACLOOPVOLL 0x0098 83#define YDSXGR_NATIVEDACLOOPVOLR 0x009A 84#define YDSXGR_ZVLOOPVOL 0x009C 85#define YDSXGR_ZVLOOPVOLL 0x009E 86#define YDSXGR_ZVLOOPVOLR 0x009E 87#define YDSXGR_SECADCLOOPVOL 0x00A0 88#define YDSXGR_SECADCLOOPVOLL 0x00A0 89#define YDSXGR_SECADCLOOPVOLR 0x00A2 90#define YDSXGR_PRIADCLOOPVOL 0x00A4 91#define YDSXGR_PRIADCLOOPVOLL 0x00A4 92#define YDSXGR_PRIADCLOOPVOLR 0x00A6 93#define YDSXGR_NATIVEADCINVOL 0x00A8 94#define YDSXGR_NATIVEADCINVOLL 0x00A8 95#define YDSXGR_NATIVEADCINVOLR 0x00AA 96#define YDSXGR_NATIVEDACINVOL 0x00AC 97#define YDSXGR_NATIVEDACINVOLL 0x00AC 98#define YDSXGR_NATIVEDACINVOLR 0x00AE 99#define YDSXGR_BUF441OUTVOL 0x00B0 100#define YDSXGR_BUF441OUTVOLL 0x00B0 101#define YDSXGR_BUF441OUTVOLR 0x00B2 102#define YDSXGR_BUF441LOOPVOL 0x00B4 103#define YDSXGR_BUF441LOOPVOLL 0x00B4 104#define YDSXGR_BUF441LOOPVOLR 0x00B6 105#define YDSXGR_SPDIFOUTVOL 0x00B8 106#define YDSXGR_SPDIFOUTVOLL 0x00B8 107#define YDSXGR_SPDIFOUTVOLR 0x00BA 108#define YDSXGR_SPDIFLOOPVOL 0x00BC 109#define YDSXGR_SPDIFLOOPVOLL 0x00BC 110#define YDSXGR_SPDIFLOOPVOLR 0x00BE 111#define YDSXGR_ADCSLOTSR 0x00C0 112#define YDSXGR_RECSLOTSR 0x00C4 113#define YDSXGR_ADCFORMAT 0x00C8 114#define YDSXGR_RECFORMAT 0x00CC 115#define YDSXGR_P44SLOTSR 0x00D0 116#define YDSXGR_STATUS 0x0100 117#define YDSXGR_CTRLSELECT 0x0104 118#define YDSXGR_MODE 0x0108 119#define YDSXGR_SAMPLECOUNT 0x010C 120#define YDSXGR_NUMOFSAMPLES 0x0110 121#define YDSXGR_CONFIG 0x0114 122#define YDSXGR_PLAYCTRLSIZE 0x0140 123#define YDSXGR_RECCTRLSIZE 0x0144 124#define YDSXGR_EFFCTRLSIZE 0x0148 125#define YDSXGR_WORKSIZE 0x014C 126#define YDSXGR_MAPOFREC 0x0150 127#define YDSXGR_MAPOFEFFECT 0x0154 128#define YDSXGR_PLAYCTRLBASE 0x0158 129#define YDSXGR_RECCTRLBASE 0x015C 130#define YDSXGR_EFFCTRLBASE 0x0160 131#define YDSXGR_WORKBASE 0x0164 132#define YDSXGR_DSPINSTRAM 0x1000 133#define YDSXGR_CTRLINSTRAM 0x4000 134 135#define YDSXG_AC97READCMD 0x8000 136#define YDSXG_AC97WRITECMD 0x0000 137 138#define PCIR_DSXG_LEGACY 0x40 139#define PCIR_DSXG_ELEGACY 0x42 140#define PCIR_DSXG_CTRL 0x48 141#define PCIR_DSXG_PWRCTRL1 0x4a 142#define PCIR_DSXG_PWRCTRL2 0x4e 143#define PCIR_DSXG_FMBASE 0x60 144#define PCIR_DSXG_SBBASE 0x62 145#define PCIR_DSXG_MPU401BASE 0x64 146#define PCIR_DSXG_JOYBASE 0x66 147 148#define YDSXG_DSPLENGTH 0x0080 149#define YDSXG_CTRLLENGTH 0x3000 150 151#define YDSXG_DEFAULT_WORK_SIZE 0x0400 152 153#define YDSXG_PLAYBACK_VOICES 64 154#define YDSXG_CAPTURE_VOICES 2 155#define YDSXG_EFFECT_VOICES 5 156 157#define YMFPCI_LEGACY_SBEN (1 << 0) /* soundblaster enable */ 158#define YMFPCI_LEGACY_FMEN (1 << 1) /* OPL3 enable */ 159#define YMFPCI_LEGACY_JPEN (1 << 2) /* joystick enable */ 160#define YMFPCI_LEGACY_MEN (1 << 3) /* MPU401 enable */ 161#define YMFPCI_LEGACY_MIEN (1 << 4) /* MPU RX irq enable */ 162#define YMFPCI_LEGACY_IOBITS (1 << 5) /* i/o bits range, 0 = 16bit, 1 =10bit */ 163#define YMFPCI_LEGACY_SDMA (3 << 6) /* SB DMA select */ 164#define YMFPCI_LEGACY_SBIRQ (7 << 8) /* SB IRQ select */ 165#define YMFPCI_LEGACY_MPUIRQ (7 << 11) /* MPU IRQ select */ 166#define YMFPCI_LEGACY_SIEN (1 << 14) /* serialized IRQ */ 167#define YMFPCI_LEGACY_LAD (1 << 15) /* legacy audio disable */ 168 169#define YMFPCI_LEGACY2_FMIO (3 << 0) /* OPL3 i/o address (724/740) */ 170#define YMFPCI_LEGACY2_SBIO (3 << 2) /* SB i/o address (724/740) */ 171#define YMFPCI_LEGACY2_MPUIO (3 << 4) /* MPU401 i/o address (724/740) */ 172#define YMFPCI_LEGACY2_JSIO (3 << 6) /* joystick i/o address (724/740) */ 173#define YMFPCI_LEGACY2_MAIM (1 << 8) /* MPU401 ack intr mask */ 174#define YMFPCI_LEGACY2_SMOD (3 << 11) /* SB DMA mode */ 175#define YMFPCI_LEGACY2_SBVER (3 << 13) /* SB version select */ 176#define YMFPCI_LEGACY2_IMOD (1 << 15) /* legacy IRQ mode */ 177/* SIEN:IMOD 0:0 = legacy irq, 0:1 = INTA, 1:0 = serialized IRQ */ 178 179#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 180#define SUPPORT_JOYSTICK 181#endif 182 183/* 184 * 185 */ 186 187struct snd_ymfpci_playback_bank { 188 u32 format; 189 u32 loop_default; 190 u32 base; /* 32-bit address */ 191 u32 loop_start; /* 32-bit offset */ 192 u32 loop_end; /* 32-bit offset */ 193 u32 loop_frac; /* 8-bit fraction - loop_start */ 194 u32 delta_end; /* pitch delta end */ 195 u32 lpfK_end; 196 u32 eg_gain_end; 197 u32 left_gain_end; 198 u32 right_gain_end; 199 u32 eff1_gain_end; 200 u32 eff2_gain_end; 201 u32 eff3_gain_end; 202 u32 lpfQ; 203 u32 status; 204 u32 num_of_frames; 205 u32 loop_count; 206 u32 start; 207 u32 start_frac; 208 u32 delta; 209 u32 lpfK; 210 u32 eg_gain; 211 u32 left_gain; 212 u32 right_gain; 213 u32 eff1_gain; 214 u32 eff2_gain; 215 u32 eff3_gain; 216 u32 lpfD1; 217 u32 lpfD2; 218 }; 219 220struct snd_ymfpci_capture_bank { 221 u32 base; /* 32-bit address */ 222 u32 loop_end; /* 32-bit offset */ 223 u32 start; /* 32-bit offset */ 224 u32 num_of_loops; /* counter */ 225}; 226 227struct snd_ymfpci_effect_bank { 228 u32 base; /* 32-bit address */ 229 u32 loop_end; /* 32-bit offset */ 230 u32 start; /* 32-bit offset */ 231 u32 temp; 232}; 233 234struct snd_ymfpci_pcm; 235struct snd_ymfpci; 236 237enum snd_ymfpci_voice_type { 238 YMFPCI_PCM, 239 YMFPCI_SYNTH, 240 YMFPCI_MIDI 241}; 242 243struct snd_ymfpci_voice { 244 struct snd_ymfpci *chip; 245 int number; 246 unsigned int use: 1, 247 pcm: 1, 248 synth: 1, 249 midi: 1; 250 struct snd_ymfpci_playback_bank *bank; 251 dma_addr_t bank_addr; 252 void (*interrupt)(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice); 253 struct snd_ymfpci_pcm *ypcm; 254}; 255 256enum snd_ymfpci_pcm_type { 257 PLAYBACK_VOICE, 258 CAPTURE_REC, 259 CAPTURE_AC97, 260 EFFECT_DRY_LEFT, 261 EFFECT_DRY_RIGHT, 262 EFFECT_EFF1, 263 EFFECT_EFF2, 264 EFFECT_EFF3 265}; 266 267struct snd_ymfpci_pcm { 268 struct snd_ymfpci *chip; 269 enum snd_ymfpci_pcm_type type; 270 struct snd_pcm_substream *substream; 271 struct snd_ymfpci_voice *voices[2]; /* playback only */ 272 unsigned int running: 1, 273 use_441_slot: 1, 274 output_front: 1, 275 output_rear: 1, 276 swap_rear: 1; 277 unsigned int update_pcm_vol; 278 u32 period_size; /* cached from runtime->period_size */ 279 u32 buffer_size; /* cached from runtime->buffer_size */ 280 u32 period_pos; 281 u32 last_pos; 282 u32 capture_bank_number; 283 u32 shift; 284}; 285 286struct snd_ymfpci { 287 int irq; 288 289 unsigned int device_id; /* PCI device ID */ 290 unsigned char rev; /* PCI revision */ 291 unsigned long reg_area_phys; 292 void __iomem *reg_area_virt; 293 struct resource *res_reg_area; 294 struct resource *fm_res; 295 struct resource *mpu_res; 296 297 unsigned short old_legacy_ctrl; 298#ifdef SUPPORT_JOYSTICK 299 struct gameport *gameport; 300#endif 301 302 struct snd_dma_buffer work_ptr; 303 304 unsigned int bank_size_playback; 305 unsigned int bank_size_capture; 306 unsigned int bank_size_effect; 307 unsigned int work_size; 308 309 void *bank_base_playback; 310 void *bank_base_capture; 311 void *bank_base_effect; 312 void *work_base; 313 dma_addr_t bank_base_playback_addr; 314 dma_addr_t bank_base_capture_addr; 315 dma_addr_t bank_base_effect_addr; 316 dma_addr_t work_base_addr; 317 struct snd_dma_buffer ac3_tmp_base; 318 319 u32 *ctrl_playback; 320 struct snd_ymfpci_playback_bank *bank_playback[YDSXG_PLAYBACK_VOICES][2]; 321 struct snd_ymfpci_capture_bank *bank_capture[YDSXG_CAPTURE_VOICES][2]; 322 struct snd_ymfpci_effect_bank *bank_effect[YDSXG_EFFECT_VOICES][2]; 323 324 int start_count; 325 326 u32 active_bank; 327 struct snd_ymfpci_voice voices[64]; 328 int src441_used; 329 330 struct snd_ac97_bus *ac97_bus; 331 struct snd_ac97 *ac97; 332 struct snd_rawmidi *rawmidi; 333 struct snd_timer *timer; 334 335 struct pci_dev *pci; 336 struct snd_card *card; 337 struct snd_pcm *pcm; 338 struct snd_pcm *pcm2; 339 struct snd_pcm *pcm_spdif; 340 struct snd_pcm *pcm_4ch; 341 struct snd_pcm_substream *capture_substream[YDSXG_CAPTURE_VOICES]; 342 struct snd_pcm_substream *effect_substream[YDSXG_EFFECT_VOICES]; 343 struct snd_kcontrol *ctl_vol_recsrc; 344 struct snd_kcontrol *ctl_vol_adcrec; 345 struct snd_kcontrol *ctl_vol_spdifrec; 346 unsigned short spdif_bits, spdif_pcm_bits; 347 struct snd_kcontrol *spdif_pcm_ctl; 348 int mode_dup4ch; 349 int rear_opened; 350 int spdif_opened; 351 struct snd_ymfpci_pcm_mixer { 352 u16 left; 353 u16 right; 354 struct snd_kcontrol *ctl; 355 } pcm_mixer[32]; 356 357 spinlock_t reg_lock; 358 spinlock_t voice_lock; 359 wait_queue_head_t interrupt_sleep; 360 atomic_t interrupt_sleep_count; 361 struct snd_info_entry *proc_entry; 362 const struct firmware *dsp_microcode; 363 const struct firmware *controller_microcode; 364 365#ifdef CONFIG_PM 366 u32 *saved_regs; 367 u32 saved_ydsxgr_mode; 368#endif 369}; 370 371int snd_ymfpci_create(struct snd_card *card, 372 struct pci_dev *pci, 373 unsigned short old_legacy_ctrl, 374 struct snd_ymfpci ** rcodec); 375void snd_ymfpci_free_gameport(struct snd_ymfpci *chip); 376 377int snd_ymfpci_suspend(struct pci_dev *pci, pm_message_t state); 378int snd_ymfpci_resume(struct pci_dev *pci); 379 380int snd_ymfpci_pcm(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm); 381int snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm); 382int snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm); 383int snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm); 384int snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch); 385int snd_ymfpci_timer(struct snd_ymfpci *chip, int device); 386 387#endif /* __SOUND_YMFPCI_H */ 388