1/* 2 * include/linux/spi/spidev.h 3 * 4 * Copyright (C) 2006 SWAPP 5 * Andrea Paterniani <a.paterniani@swapp-eng.it> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22#ifndef SPIDEV_H 23#define SPIDEV_H 24 25 26/* User space versions of kernel symbols for SPI clocking modes, 27 * matching <linux/spi/spi.h> 28 */ 29 30#define SPI_CPHA 0x01 31#define SPI_CPOL 0x02 32 33#define SPI_MODE_0 (0|0) 34#define SPI_MODE_1 (0|SPI_CPHA) 35#define SPI_MODE_2 (SPI_CPOL|0) 36#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) 37 38 39/*---------------------------------------------------------------------------*/ 40 41/* IOCTL commands */ 42 43#define SPI_IOC_MAGIC 'k' 44 45/** 46 * struct spi_ioc_transfer - describes a single SPI transfer 47 * @tx_buf: Holds pointer to userspace buffer with transmit data, or null. 48 * If no data is provided, zeroes are shifted out. 49 * @rx_buf: Holds pointer to userspace buffer for receive data, or null. 50 * @len: Length of tx and rx buffers, in bytes. 51 * @speed_hz: Temporary override of the device's bitrate. 52 * @bits_per_word: Temporary override of the device's wordsize. 53 * @delay_usecs: If nonzero, how long to delay after the last bit transfer 54 * before optionally deselecting the device before the next transfer. 55 * @cs_change: True to deselect device before starting the next transfer. 56 * 57 * This structure is mapped directly to the kernel spi_transfer structure; 58 * the fields have the same meanings, except of course that the pointers 59 * are in a different address space (and may be of different sizes in some 60 * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel). 61 * Zero-initialize the structure, including currently unused fields, to 62 * accomodate potential future updates. 63 * 64 * SPI_IOC_MESSAGE gives userspace the equivalent of kernel spi_sync(). 65 * Pass it an array of related transfers, they'll execute together. 66 * Each transfer may be half duplex (either direction) or full duplex. 67 * 68 * struct spi_ioc_transfer mesg[4]; 69 * ... 70 * status = ioctl(fd, SPI_IOC_MESSAGE(4), mesg); 71 * 72 * So for example one transfer might send a nine bit command (right aligned 73 * in a 16-bit word), the next could read a block of 8-bit data before 74 * terminating that command by temporarily deselecting the chip; the next 75 * could send a different nine bit command (re-selecting the chip), and the 76 * last transfer might write some register values. 77 */ 78struct spi_ioc_transfer { 79 __u64 tx_buf; 80 __u64 rx_buf; 81 82 __u32 len; 83 __u32 speed_hz; 84 85 __u16 delay_usecs; 86 __u8 bits_per_word; 87 __u8 cs_change; 88 __u32 pad; 89 90 /* If the contents of 'struct spi_ioc_transfer' ever change 91 * incompatibly, then the ioctl number (currently 0) must change; 92 * ioctls with constant size fields get a bit more in the way of 93 * error checking than ones (like this) where that field varies. 94 * 95 * NOTE: struct layout is the same in 64bit and 32bit userspace. 96 */ 97}; 98 99/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */ 100#define SPI_MSGSIZE(N) \ 101 ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ 102 ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) 103#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) 104 105 106/* Read / Write of SPI mode (SPI_MODE_0..SPI_MODE_3) */ 107#define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, __u8) 108#define SPI_IOC_WR_MODE _IOW(SPI_IOC_MAGIC, 1, __u8) 109 110/* Read / Write SPI bit justification */ 111#define SPI_IOC_RD_LSB_FIRST _IOR(SPI_IOC_MAGIC, 2, __u8) 112#define SPI_IOC_WR_LSB_FIRST _IOW(SPI_IOC_MAGIC, 2, __u8) 113 114/* Read / Write SPI device word length (1..N) */ 115#define SPI_IOC_RD_BITS_PER_WORD _IOR(SPI_IOC_MAGIC, 3, __u8) 116#define SPI_IOC_WR_BITS_PER_WORD _IOW(SPI_IOC_MAGIC, 3, __u8) 117 118/* Read / Write SPI device default max speed hz */ 119#define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, __u32) 120#define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, __u32) 121 122 123 124#endif /* SPIDEV_H */ 125