1/* 2 * ds17287rtc.h - register definitions for the ds1728[57] RTC / CMOS RAM 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * (C) 2003 Guido Guenther <agx@sigxcpu.org> 9 */ 10#ifndef __LINUX_DS17287RTC_H 11#define __LINUX_DS17287RTC_H 12 13#include <linux/rtc.h> /* get the user-level API */ 14#include <linux/spinlock.h> /* spinlock_t */ 15#include <linux/mc146818rtc.h> 16 17/* Register A */ 18#define DS_REGA_DV2 0x40 /* countdown chain */ 19#define DS_REGA_DV1 0x20 /* oscillator enable */ 20#define DS_REGA_DV0 0x10 /* bank select */ 21 22/* bank 1 registers */ 23#define DS_B1_MODEL 0x40 /* model number byte */ 24#define DS_B1_SN1 0x41 /* serial number byte 1 */ 25#define DS_B1_SN2 0x42 /* serial number byte 2 */ 26#define DS_B1_SN3 0x43 /* serial number byte 3 */ 27#define DS_B1_SN4 0x44 /* serial number byte 4 */ 28#define DS_B1_SN5 0x45 /* serial number byte 5 */ 29#define DS_B1_SN6 0x46 /* serial number byte 6 */ 30#define DS_B1_CRC 0x47 /* CRC byte */ 31#define DS_B1_CENTURY 0x48 /* Century byte */ 32#define DS_B1_DALARM 0x49 /* date alarm */ 33#define DS_B1_XCTRL4A 0x4a /* extendec control register 4a */ 34#define DS_B1_XCTRL4B 0x4b /* extendec control register 4b */ 35#define DS_B1_RTCADDR2 0x4e /* rtc address 2 */ 36#define DS_B1_RTCADDR3 0x4f /* rtc address 3 */ 37#define DS_B1_RAMLSB 0x50 /* extended ram LSB */ 38#define DS_B1_RAMMSB 0x51 /* extended ram MSB */ 39#define DS_B1_RAMDPORT 0x53 /* extended ram data port */ 40 41/* register details */ 42/* extended control register 4a */ 43#define DS_XCTRL4A_VRT2 0x80 /* valid ram and time */ 44#define DS_XCTRL4A_INCR 0x40 /* increment progress status */ 45#define DS_XCTRL4A_BME 0x20 /* burst mode enable */ 46#define DS_XCTRL4A_PAB 0x08 /* power active bar ctrl */ 47#define DS_XCTRL4A_RF 0x04 /* ram clear flag */ 48#define DS_XCTRL4A_WF 0x02 /* wake up alarm flag */ 49#define DS_XCTRL4A_KF 0x01 /* kickstart flag */ 50 51/* interrupt causes */ 52#define DS_XCTRL4A_IFS (DS_XCTRL4A_RF|DS_XCTRL4A_WF|DS_XCTRL4A_KF) 53 54/* extended control register 4b */ 55#define DS_XCTRL4B_ABE 0x80 /* auxiliary battery enable */ 56#define DS_XCTRL4B_E32K 0x40 /* enable 32.768 kHz Output */ 57#define DS_XCTRL4B_CS 0x20 /* crystal select */ 58#define DS_XCTRL4B_RCE 0x10 /* ram clear enable */ 59#define DS_XCTRL4B_PRS 0x08 /* PAB resec select */ 60#define DS_XCTRL4B_RIE 0x04 /* ram clear interrupt enable */ 61#define DS_XCTRL4B_WFE 0x02 /* wake up alarm interrupt enable */ 62#define DS_XCTRL4B_KFE 0x01 /* kickstart interrupt enable */ 63 64/* interrupt enable bits */ 65#define DS_XCTRL4B_IFES (DS_XCTRL4B_RIE|DS_XCTRL4B_WFE|DS_XCTRL4B_KFE) 66 67#endif /* __LINUX_DS17287RTC_H */ 68