1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2002, 2004 by Ralf Baechle 7 */ 8#ifndef _ASM_WAR_H 9#define _ASM_WAR_H 10 11 12/* 13 * Another R4600 erratum. Due to the lack of errata information the exact 14 * technical details aren't known. I've experimentally found that disabling 15 * interrupts during indexed I-cache flushes seems to be sufficient to deal 16 * with the issue. 17 * 18 * #define R4600_V1_INDEX_ICACHEOP_WAR 1 19 */ 20 21/* 22 * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: 23 * 24 * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, 25 * Hit_Invalidate_D and Create_Dirty_Excl_D should only be 26 * executed if there is no other dcache activity. If the dcache is 27 * accessed for another instruction immeidately preceding when these 28 * cache instructions are executing, it is possible that the dcache 29 * tag match outputs used by these cache instructions will be 30 * incorrect. These cache instructions should be preceded by at least 31 * four instructions that are not any kind of load or store 32 * instruction. 33 * 34 * This is not allowed: lw 35 * nop 36 * nop 37 * nop 38 * cache Hit_Writeback_Invalidate_D 39 * 40 * This is allowed: lw 41 * nop 42 * nop 43 * nop 44 * nop 45 * cache Hit_Writeback_Invalidate_D 46 * 47 * #define R4600_V1_HIT_CACHEOP_WAR 1 48 */ 49 50 51/* 52 * Writeback and invalidate the primary cache dcache before DMA. 53 * 54 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, 55 * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only 56 * operate correctly if the internal data cache refill buffer is empty. These 57 * CACHE instructions should be separated from any potential data cache miss 58 * by a load instruction to an uncached address to empty the response buffer." 59 * (Revision 2.0 device errata from IDT available on http://www.idt.com/ 60 * in .pdf format.) 61 * 62 * #define R4600_V2_HIT_CACHEOP_WAR 1 63 */ 64 65/* 66 * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. 67 */ 68#ifdef CONFIG_SGI_IP22 69 70#define R4600_V1_INDEX_ICACHEOP_WAR 1 71#define R4600_V1_HIT_CACHEOP_WAR 1 72#define R4600_V2_HIT_CACHEOP_WAR 1 73 74#endif 75 76/* 77 * But the RM200C seems to have been shipped only with V2.0 R4600s 78 */ 79#ifdef CONFIG_SNI_RM 80 81#define R4600_V2_HIT_CACHEOP_WAR 1 82 83#endif 84 85#ifdef CONFIG_CPU_R5432 86 87#define R5432_CP0_INTERRUPT_WAR 1 88 89#endif 90 91#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || defined(CONFIG_SB1_PASS_2_WORKAROUNDS) 92 93#define BCM1250_M3_WAR 1 94 95#define SIBYTE_1956_WAR 1 96 97#endif 98 99#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ 100 defined(CONFIG_MIPS_SEAD) 101#define MIPS4K_ICACHE_REFILL_WAR 1 102#endif 103 104#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ 105 defined(CONFIG_MIPS_SEAD) 106#define MIPS_CACHE_SYNC_WAR 1 107#endif 108 109#ifdef CONFIG_CPU_TX49XX 110#define TX49XX_ICACHE_INDEX_INV_WAR 1 111#endif 112 113/* 114 * On the RM9000 there is a problem which makes the CreateDirtyExclusive 115 * cache operation unusable on SMP systems. 116 */ 117#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \ 118 defined(CONFIG_BASLER_EXCITE) 119#define RM9000_CDEX_SMP_WAR 1 120#endif 121 122/* 123 * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra 124 * opposes it being called that) where invalid instructions in the same 125 * I-cache line worth of instructions being fetched may case spurious 126 * exceptions. 127 */ 128#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MOMENCO_JAGUAR_ATX) || \ 129 defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) || \ 130 defined(CONFIG_MOMENCO_OCELOT) || defined(CONFIG_MOMENCO_OCELOT_3) || \ 131 defined(CONFIG_MOMENCO_OCELOT_C) || defined(CONFIG_PMC_YOSEMITE) || \ 132 defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC) 133#define ICACHE_REFILLS_WORKAROUND_WAR 1 134#endif 135 136 137/* 138 * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that 139 * may cause ll / sc and lld / scd sequences to execute non-atomically. 140 */ 141#ifdef CONFIG_SGI_IP27 142#define R10000_LLSC_WAR 1 143#endif 144 145/* 146 * Workarounds default to off 147 */ 148#ifndef ICACHE_REFILLS_WORKAROUND_WAR 149#define ICACHE_REFILLS_WORKAROUND_WAR 0 150#endif 151#ifndef R4600_V1_INDEX_ICACHEOP_WAR 152#define R4600_V1_INDEX_ICACHEOP_WAR 0 153#endif 154#ifndef R4600_V1_HIT_CACHEOP_WAR 155#define R4600_V1_HIT_CACHEOP_WAR 0 156#endif 157#ifndef R4600_V2_HIT_CACHEOP_WAR 158#define R4600_V2_HIT_CACHEOP_WAR 0 159#endif 160#ifndef R5432_CP0_INTERRUPT_WAR 161#define R5432_CP0_INTERRUPT_WAR 0 162#endif 163#ifndef BCM1250_M3_WAR 164#define BCM1250_M3_WAR 0 165#endif 166#ifndef SIBYTE_1956_WAR 167#define SIBYTE_1956_WAR 0 168#endif 169#ifndef MIPS4K_ICACHE_REFILL_WAR 170#define MIPS4K_ICACHE_REFILL_WAR 0 171#endif 172#ifndef MIPS_CACHE_SYNC_WAR 173#define MIPS_CACHE_SYNC_WAR 0 174#endif 175#ifndef TX49XX_ICACHE_INDEX_INV_WAR 176#define TX49XX_ICACHE_INDEX_INV_WAR 0 177#endif 178#ifndef RM9000_CDEX_SMP_WAR 179#define RM9000_CDEX_SMP_WAR 0 180#endif 181#ifndef R10000_LLSC_WAR 182#define R10000_LLSC_WAR 0 183#endif 184 185#endif /* _ASM_WAR_H */ 186