1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * SCD Constants and Macros File: sb1250_scd.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the System Control and Debug module on the 1250. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2004,2005 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 ********************************************************************* */ 31 32#ifndef _SB1250_SCD_H 33#define _SB1250_SCD_H 34 35#include "sb1250_defs.h" 36 37/* ********************************************************************* 38 * System control/debug registers 39 ********************************************************************* */ 40 41/* 42 * System Revision Register (Table 4-1) 43 */ 44 45#define M_SYS_RESERVED _SB_MAKEMASK(8,0) 46 47#define S_SYS_REVISION _SB_MAKE64(8) 48#define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) 49#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) 50#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) 51 52#define K_SYS_REVISION_BCM1250_PASS1 0x01 53 54#define K_SYS_REVISION_BCM1250_PASS2 0x03 55#define K_SYS_REVISION_BCM1250_A1 0x03 /* Pass 2.0 WB */ 56#define K_SYS_REVISION_BCM1250_A2 0x04 /* Pass 2.0 FC */ 57#define K_SYS_REVISION_BCM1250_A3 0x05 /* Pass 2.1 FC */ 58#define K_SYS_REVISION_BCM1250_A4 0x06 /* Pass 2.1 WB */ 59#define K_SYS_REVISION_BCM1250_A6 0x07 /* OR 0x04 (A2) w/WID != 0 */ 60#define K_SYS_REVISION_BCM1250_A8 0x0b /* A8/A10 */ 61#define K_SYS_REVISION_BCM1250_A9 0x08 62#define K_SYS_REVISION_BCM1250_A10 K_SYS_REVISION_BCM1250_A8 63 64#define K_SYS_REVISION_BCM1250_PASS2_2 0x10 65#define K_SYS_REVISION_BCM1250_B0 K_SYS_REVISION_BCM1250_B1 66#define K_SYS_REVISION_BCM1250_B1 0x10 67#define K_SYS_REVISION_BCM1250_B2 0x11 68 69#define K_SYS_REVISION_BCM1250_C0 0x20 70#define K_SYS_REVISION_BCM1250_C1 0x21 71#define K_SYS_REVISION_BCM1250_C2 0x22 72#define K_SYS_REVISION_BCM1250_C3 0x23 73 74#if SIBYTE_HDR_FEATURE_CHIP(1250) 75#define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 76#define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 77#define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 78#define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 79#define K_SYS_REVISION_BCM1250_PASS3 K_SYS_REVISION_BCM1250_C0 80#endif /* 1250 */ 81 82#define K_SYS_REVISION_BCM112x_A1 0x20 83#define K_SYS_REVISION_BCM112x_A2 0x21 84#define K_SYS_REVISION_BCM112x_A3 0x22 85#define K_SYS_REVISION_BCM112x_A4 0x23 86#define K_SYS_REVISION_BCM112x_B0 0x30 87 88#define K_SYS_REVISION_BCM1480_S0 0x01 89#define K_SYS_REVISION_BCM1480_A1 0x02 90#define K_SYS_REVISION_BCM1480_A2 0x03 91#define K_SYS_REVISION_BCM1480_A3 0x04 92#define K_SYS_REVISION_BCM1480_B0 0x11 93 94/*Cache size - 23:20 of revision register*/ 95#define S_SYS_L2C_SIZE _SB_MAKE64(20) 96#define M_SYS_L2C_SIZE _SB_MAKEMASK(4,S_SYS_L2C_SIZE) 97#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x,S_SYS_L2C_SIZE) 98#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE) 99 100#define K_SYS_L2C_SIZE_1MB 0 101#define K_SYS_L2C_SIZE_512KB 5 102#define K_SYS_L2C_SIZE_256KB 2 103#define K_SYS_L2C_SIZE_128KB 1 104 105#define K_SYS_L2C_SIZE_BCM1250 K_SYS_L2C_SIZE_512KB 106#define K_SYS_L2C_SIZE_BCM1125 K_SYS_L2C_SIZE_256KB 107#define K_SYS_L2C_SIZE_BCM1122 K_SYS_L2C_SIZE_128KB 108 109 110/* Number of CPU cores, bits 27:24 of revision register*/ 111#define S_SYS_NUM_CPUS _SB_MAKE64(24) 112#define M_SYS_NUM_CPUS _SB_MAKEMASK(4,S_SYS_NUM_CPUS) 113#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x,S_SYS_NUM_CPUS) 114#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS) 115 116 117#define S_SYS_PART _SB_MAKE64(16) 118#define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) 119#define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) 120#define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) 121 122#define K_SYS_PART_SB1250 0x1250 123#define K_SYS_PART_BCM1120 0x1121 124#define K_SYS_PART_BCM1125 0x1123 125#define K_SYS_PART_BCM1125H 0x1124 126#define K_SYS_PART_BCM1122 0x1113 127 128 129/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ 130#define S_SYS_SOC_TYPE _SB_MAKE64(16) 131#define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) 132#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) 133#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) 134 135#define K_SYS_SOC_TYPE_BCM1250 0x0 136#define K_SYS_SOC_TYPE_BCM1120 0x1 137#define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ 138#define K_SYS_SOC_TYPE_BCM1125 0x3 139#define K_SYS_SOC_TYPE_BCM1125H 0x4 140#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ 141#define K_SYS_SOC_TYPE_BCM1x80 0x6 142#define K_SYS_SOC_TYPE_BCM1x55 0x7 143 144/* 145 * Calculate correct SOC type given a copy of system revision register. 146 * 147 * (For the assembler version, sysrev and dest may be the same register. 148 * Also, it clobbers AT.) 149 */ 150#ifdef __ASSEMBLER__ 151#define SYS_SOC_TYPE(dest, sysrev) \ 152 .set push ; \ 153 .set reorder ; \ 154 dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ 155 andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ 156 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ 157 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ 158 b 992f ; \ 159991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ 160992: \ 161 .set pop 162#else 163#define SYS_SOC_TYPE(sysrev) \ 164 ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ 165 || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ 166 ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) 167#endif 168 169#define S_SYS_WID _SB_MAKE64(32) 170#define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) 171#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) 172#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) 173 174/* 175 * System Manufacturing Register 176 * Register: SCD_SYSTEM_MANUF 177 */ 178 179#if SIBYTE_HDR_FEATURE_1250_112x 180/* Wafer ID: bits 31:0 */ 181#define S_SYS_WAFERID1_200 _SB_MAKE64(0) 182#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) 183#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) 184#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) 185 186#define S_SYS_BIN _SB_MAKE64(32) 187#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) 188#define V_SYS_BIN(x) _SB_MAKEVALUE(x,S_SYS_BIN) 189#define G_SYS_BIN(x) _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) 190 191/* Wafer ID: bits 39:36 */ 192#define S_SYS_WAFERID2_200 _SB_MAKE64(36) 193#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) 194#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) 195#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) 196 197/* Wafer ID: bits 39:0 */ 198#define S_SYS_WAFERID_300 _SB_MAKE64(0) 199#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) 200#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) 201#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) 202 203#define S_SYS_XPOS _SB_MAKE64(40) 204#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) 205#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) 206#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) 207 208#define S_SYS_YPOS _SB_MAKE64(46) 209#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) 210#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) 211#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) 212#endif 213 214 215/* 216 * System Config Register (Table 4-2) 217 * Register: SCD_SYSTEM_CFG 218 */ 219 220#if SIBYTE_HDR_FEATURE_1250_112x 221#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) 222#define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) 223#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) 224#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) 225 226#define S_SYS_PLL_DIV _SB_MAKE64(7) 227#define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) 228#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) 229#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) 230 231#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) 232#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) 233#define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) 234#define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) 235#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 236 237#define S_SYS_BOOT_MODE _SB_MAKE64(17) 238#define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) 239#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) 240#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) 241#define K_SYS_BOOT_MODE_ROM32 0 242#define K_SYS_BOOT_MODE_ROM8 1 243#define K_SYS_BOOT_MODE_SMBUS_SMALL 2 244#define K_SYS_BOOT_MODE_SMBUS_BIG 3 245 246#define M_SYS_PCI_HOST _SB_MAKEMASK1(19) 247#define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) 248#define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) 249#define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) 250#define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) 251#define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) 252#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) 253 254#define S_SYS_CONFIG 26 255#define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) 256#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) 257#define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) 258 259/* The following bits are writeable by JTAG only. */ 260 261#define M_SYS_CLKSTOP _SB_MAKEMASK1(32) 262#define M_SYS_CLKSTEP _SB_MAKEMASK1(33) 263 264#define S_SYS_CLKCOUNT 34 265#define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) 266#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) 267#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) 268 269#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) 270 271#define S_SYS_PLL_IREF 43 272#define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) 273 274#define S_SYS_PLL_VCO 45 275#define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) 276 277#define S_SYS_PLL_VREG 47 278#define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) 279 280#define M_SYS_MEM_RESET _SB_MAKEMASK1(49) 281#define M_SYS_L2C_RESET _SB_MAKEMASK1(50) 282#define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) 283#define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) 284#define M_SYS_SCD_RESET _SB_MAKEMASK1(53) 285 286/* End of bits writable by JTAG only. */ 287 288#define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) 289#define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) 290 291#define M_SYS_UNICPU0 _SB_MAKEMASK1(56) 292#define M_SYS_UNICPU1 _SB_MAKEMASK1(57) 293 294#define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) 295#define M_SYS_EXT_RESET _SB_MAKEMASK1(59) 296#define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) 297 298#define M_SYS_MISR_MODE _SB_MAKEMASK1(61) 299#define M_SYS_MISR_RESET _SB_MAKEMASK1(62) 300 301#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 302#define M_SYS_SW_FLAG _SB_MAKEMASK1(63) 303#endif /* 1250 PASS2 || 112x PASS1 */ 304 305#endif 306 307 308/* 309 * Mailbox Registers (Table 4-3) 310 * Registers: SCD_MBOX_CPU_x 311 */ 312 313#define S_MBOX_INT_3 0 314#define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) 315#define S_MBOX_INT_2 16 316#define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) 317#define S_MBOX_INT_1 32 318#define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) 319#define S_MBOX_INT_0 48 320#define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) 321 322/* 323 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) 324 * Registers: SCD_WDOG_INIT_CNT_x 325 */ 326 327#define V_SCD_WDOG_FREQ 1000000 328 329#define S_SCD_WDOG_INIT 0 330#define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) 331 332#define S_SCD_WDOG_CNT 0 333#define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) 334 335#define S_SCD_WDOG_ENABLE 0 336#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) 337 338#define S_SCD_WDOG_RESET_TYPE 2 339#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE) 340#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE) 341#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE) 342 343#define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ 344#define K_SCD_WDOG_RESET_SOFT 1 345#define K_SCD_WDOG_RESET_CPU0 3 346#define K_SCD_WDOG_RESET_CPU1 5 347#define K_SCD_WDOG_RESET_BOTH_CPUS 7 348 349/* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */ 350#if SIBYTE_HDR_FEATURE(1250, PASS3) 351#define S_SCD_WDOG_HAS_RESET 8 352#define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET) 353#endif 354 355 356/* 357 * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) 358 */ 359 360#define V_SCD_TIMER_FREQ 1000000 361 362#define S_SCD_TIMER_INIT 0 363#define M_SCD_TIMER_INIT _SB_MAKEMASK(23,S_SCD_TIMER_INIT) 364#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 365#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 366 367#define V_SCD_TIMER_WIDTH 23 368#define S_SCD_TIMER_CNT 0 369#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT) 370#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 371#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) 372 373#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) 374#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) 375#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE 376 377/* 378 * System Performance Counters 379 */ 380 381#define S_SPC_CFG_SRC0 0 382#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 383#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 384#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) 385 386#define S_SPC_CFG_SRC1 8 387#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) 388#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) 389#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) 390 391#define S_SPC_CFG_SRC2 16 392#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) 393#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) 394#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) 395 396#define S_SPC_CFG_SRC3 24 397#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) 398#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) 399#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) 400 401#if SIBYTE_HDR_FEATURE_1250_112x 402#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 403#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) 404#endif 405 406 407/* 408 * Bus Watcher 409 */ 410 411#define S_SCD_BERR_TID 8 412#define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) 413#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) 414#define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) 415 416#define S_SCD_BERR_RID 18 417#define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) 418#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) 419#define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) 420 421#define S_SCD_BERR_DCODE 22 422#define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) 423#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) 424#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) 425 426#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) 427 428 429#define S_SCD_L2ECC_CORR_D 0 430#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) 431#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) 432#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) 433 434#define S_SCD_L2ECC_BAD_D 8 435#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) 436#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) 437#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) 438 439#define S_SCD_L2ECC_CORR_T 16 440#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) 441#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) 442#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) 443 444#define S_SCD_L2ECC_BAD_T 24 445#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) 446#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) 447#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) 448 449#define S_SCD_MEM_ECC_CORR 0 450#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) 451#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) 452#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) 453 454#define S_SCD_MEM_ECC_BAD 8 455#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) 456#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) 457#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) 458 459#define S_SCD_MEM_BUSERR 16 460#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) 461#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) 462#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) 463 464 465/* 466 * Address Trap Registers 467 */ 468 469#if SIBYTE_HDR_FEATURE_1250_112x 470#define M_ATRAP_INDEX _SB_MAKEMASK(4,0) 471#define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 472 473#define S_ATRAP_CFG_CNT 0 474#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) 475#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) 476#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) 477 478#define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 479#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 480#define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) 481#define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) 482#define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 483 484#define S_ATRAP_CFG_AGENTID 8 485#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) 486#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) 487#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) 488 489#define K_BUS_AGENT_CPU0 0 490#define K_BUS_AGENT_CPU1 1 491#define K_BUS_AGENT_IOB0 2 492#define K_BUS_AGENT_IOB1 3 493#define K_BUS_AGENT_SCD 4 494#define K_BUS_AGENT_L2C 6 495#define K_BUS_AGENT_MC 7 496 497#define S_ATRAP_CFG_CATTR 12 498#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) 499#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) 500#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) 501 502#define K_ATRAP_CFG_CATTR_IGNORE 0 503#define K_ATRAP_CFG_CATTR_UNC 1 504#define K_ATRAP_CFG_CATTR_CACHEABLE 2 505#define K_ATRAP_CFG_CATTR_NONCOH 3 506#define K_ATRAP_CFG_CATTR_COHERENT 4 507#define K_ATRAP_CFG_CATTR_NOTUNC 5 508#define K_ATRAP_CFG_CATTR_NOTNONCOH 6 509#define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 510 511#endif /* 1250/112x */ 512 513/* 514 * Trace Buffer Config register 515 */ 516 517#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) 518#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) 519#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) 520#define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) 521#define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) 522#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) 523#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) 524#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) 525#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 526 SIBYTE_HDR_FEATURE_CHIP(1480) 527#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) 528#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 529 530/* 531 * This field is the same on the 1250/112x and 1480, just located in 532 * a slightly different place in the register. 533 */ 534#if SIBYTE_HDR_FEATURE_1250_112x 535#define S_SCD_TRACE_CFG_CUR_ADDR 10 536#else 537#if SIBYTE_HDR_FEATURE_CHIP(1480) 538#define S_SCD_TRACE_CFG_CUR_ADDR 24 539#endif /* 1480 */ 540#endif /* 1250/112x */ 541 542#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) 543#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 544#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 545 546/* 547 * Trace Event registers 548 */ 549 550#define S_SCD_TREVT_ADDR_MATCH 0 551#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) 552#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) 553#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) 554 555#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) 556#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) 557#define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) 558#define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) 559#define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) 560#define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) 561#define M_SCD_TREVT_READ _SB_MAKEMASK1(11) 562 563#define S_SCD_TREVT_REQID 12 564#define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) 565#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) 566#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) 567 568#define S_SCD_TREVT_RESPID 16 569#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) 570#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) 571#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) 572 573#define S_SCD_TREVT_DATAID 20 574#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) 575#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) 576#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) 577 578#define S_SCD_TREVT_COUNT 24 579#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) 580#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) 581#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) 582 583/* 584 * Trace Sequence registers 585 */ 586 587#define S_SCD_TRSEQ_EVENT4 0 588#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) 589#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) 590#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) 591 592#define S_SCD_TRSEQ_EVENT3 4 593#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) 594#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) 595#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) 596 597#define S_SCD_TRSEQ_EVENT2 8 598#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) 599#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) 600#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) 601 602#define S_SCD_TRSEQ_EVENT1 12 603#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) 604#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) 605#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) 606 607#define K_SCD_TRSEQ_E0 0 608#define K_SCD_TRSEQ_E1 1 609#define K_SCD_TRSEQ_E2 2 610#define K_SCD_TRSEQ_E3 3 611#define K_SCD_TRSEQ_E0_E1 4 612#define K_SCD_TRSEQ_E1_E2 5 613#define K_SCD_TRSEQ_E2_E3 6 614#define K_SCD_TRSEQ_E0_E1_E2 7 615#define K_SCD_TRSEQ_E0_E1_E2_E3 8 616#define K_SCD_TRSEQ_E0E1 9 617#define K_SCD_TRSEQ_E0E1E2 10 618#define K_SCD_TRSEQ_E0E1E2E3 11 619#define K_SCD_TRSEQ_E0E1_E2 12 620#define K_SCD_TRSEQ_E0E1_E2E3 13 621#define K_SCD_TRSEQ_E0E1_E2_E3 14 622#define K_SCD_TRSEQ_IGNORED 15 623 624#define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ 625 V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ 626 V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ 627 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) 628 629#define S_SCD_TRSEQ_FUNCTION 16 630#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) 631#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) 632#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) 633 634#define K_SCD_TRSEQ_FUNC_NOP 0 635#define K_SCD_TRSEQ_FUNC_START 1 636#define K_SCD_TRSEQ_FUNC_STOP 2 637#define K_SCD_TRSEQ_FUNC_FREEZE 3 638 639#define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) 640#define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) 641#define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) 642#define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) 643 644#define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) 645#define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) 646#define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) 647#define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) 648#define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) 649#define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23) 650#define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24) 651 652#endif 653