1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 2002 by Ralf Baechle 7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. 8 * Copyright (C) 2002 Maciej W. Rozycki 9 */ 10#ifndef _ASM_PGTABLE_BITS_H 11#define _ASM_PGTABLE_BITS_H 12 13 14/* 15 * Note that we shift the lower 32bits of each EntryLo[01] entry 16 * 6 bits to the left. That way we can convert the PFN into the 17 * physical address by a single 'and' operation and gain 6 additional 18 * bits for storing information which isn't present in a normal 19 * MIPS page table. 20 * 21 * Similar to the Alpha port, we need to keep track of the ref 22 * and mod bits in software. We have a software "yeah you can read 23 * from this page" bit, and a hardware one which actually lets the 24 * process read from the page. On the same token we have a software 25 * writable bit and the real hardware one which actually lets the 26 * process write to the page, this keeps a mod bit via the hardware 27 * dirty bit. 28 * 29 * Certain revisions of the R4000 and R5000 have a bug where if a 30 * certain sequence occurs in the last 3 instructions of an executable 31 * page, and the following page is not mapped, the cpu can do 32 * unpredictable things. The code (when it is written) to deal with 33 * this problem will be in the update_mmu_cache() code for the r4k. 34 */ 35#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) 36 37#define _PAGE_PRESENT (1<<6) /* implemented in software */ 38#define _PAGE_READ (1<<7) /* implemented in software */ 39#define _PAGE_WRITE (1<<8) /* implemented in software */ 40#define _PAGE_ACCESSED (1<<9) /* implemented in software */ 41#define _PAGE_MODIFIED (1<<10) /* implemented in software */ 42#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */ 43 44#define _PAGE_R4KBUG (1<<0) 45#define _PAGE_GLOBAL (1<<0) 46#define _PAGE_VALID (1<<1) 47#define _PAGE_SILENT_READ (1<<1) /* synonym */ 48#define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */ 49#define _PAGE_SILENT_WRITE (1<<2) 50#define _CACHE_MASK (7<<3) 51 52/* MIPS32 defines only values 2 and 3. The rest are implementation 53 * dependent. 54 */ 55#define _CACHE_UNCACHED (2<<3) 56#define _CACHE_CACHABLE_NONCOHERENT (3<<3) 57#define _CACHE_CACHABLE_COW (3<<3) /* Au1x */ 58 59#else 60 61#define _PAGE_PRESENT (1<<0) /* implemented in software */ 62#define _PAGE_READ (1<<1) /* implemented in software */ 63#define _PAGE_WRITE (1<<2) /* implemented in software */ 64#define _PAGE_ACCESSED (1<<3) /* implemented in software */ 65#define _PAGE_MODIFIED (1<<4) /* implemented in software */ 66#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */ 67 68#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 69 70#define _PAGE_GLOBAL (1<<8) 71#define _PAGE_VALID (1<<9) 72#define _PAGE_SILENT_READ (1<<9) /* synonym */ 73#define _PAGE_DIRTY (1<<10) /* The MIPS dirty bit */ 74#define _PAGE_SILENT_WRITE (1<<10) 75#define _CACHE_UNCACHED (1<<11) 76#define _CACHE_MASK (1<<11) 77#define _CACHE_CACHABLE_NONCOHERENT 0 78 79#else 80#define _PAGE_R4KBUG (1<<5) 81#define _PAGE_GLOBAL (1<<6) 82#define _PAGE_VALID (1<<7) 83#define _PAGE_SILENT_READ (1<<7) /* synonym */ 84#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ 85#define _PAGE_SILENT_WRITE (1<<8) 86#define _CACHE_MASK (7<<9) 87 88#ifdef CONFIG_CPU_SB1 89 90/* No penalty for being coherent on the SB1, so just 91 use it for "noncoherent" spaces, too. Shouldn't hurt. */ 92 93#define _CACHE_UNCACHED (2<<9) 94#define _CACHE_CACHABLE_COW (5<<9) 95#define _CACHE_CACHABLE_NONCOHERENT (5<<9) 96#define _CACHE_UNCACHED_ACCELERATED (7<<9) 97 98#elif defined(CONFIG_CPU_RM9000) 99 100#define _CACHE_WT (0 << 9) 101#define _CACHE_WTWA (1 << 9) 102#define _CACHE_UC_B (2 << 9) 103#define _CACHE_WB (3 << 9) 104#define _CACHE_CWBEA (4 << 9) 105#define _CACHE_CWB (5 << 9) 106#define _CACHE_UCNB (6 << 9) 107#define _CACHE_FPC (7 << 9) 108 109#define _CACHE_UNCACHED _CACHE_UC_B 110#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB 111 112#else 113 114#define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */ 115#define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ 116#define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ 117#define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */ 118#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */ 119#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */ 120#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */ 121#define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */ 122 123#endif 124#endif 125#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */ 126 127#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) 128#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) 129 130#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) 131 132#ifdef CONFIG_MIPS_UNCACHED 133#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED 134#elif defined(CONFIG_DMA_NONCOHERENT) 135#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT 136#elif defined(CONFIG_CPU_RM9000) 137#define PAGE_CACHABLE_DEFAULT _CACHE_CWB 138#else 139#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW 140#endif 141 142#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) 143#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3) 144#else 145#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9) 146#endif 147 148#endif /* _ASM_PGTABLE_BITS_H */ 149