1/* 2 * Alchemy Semi PB1000 Referrence Board 3 * 4 * Copyright 2001 MontaVista Software Inc. 5 * Author: MontaVista Software, Inc. 6 * ppopov@mvista.com or source@mvista.com 7 * 8 * ######################################################################## 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 22 * 23 * ######################################################################## 24 * 25 * 26 */ 27#ifndef __ASM_PB1000_H 28#define __ASM_PB1000_H 29 30/* PCMCIA PB1000 specific defines */ 31#define PCMCIA_MAX_SOCK 1 32#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 33 34#define PB1000_PCR 0xBE000000 35 #define PCR_SLOT_0_VPP0 (1<<0) 36 #define PCR_SLOT_0_VPP1 (1<<1) 37 #define PCR_SLOT_0_VCC0 (1<<2) 38 #define PCR_SLOT_0_VCC1 (1<<3) 39 #define PCR_SLOT_0_RST (1<<4) 40 41 #define PCR_SLOT_1_VPP0 (1<<8) 42 #define PCR_SLOT_1_VPP1 (1<<9) 43 #define PCR_SLOT_1_VCC0 (1<<10) 44 #define PCR_SLOT_1_VCC1 (1<<11) 45 #define PCR_SLOT_1_RST (1<<12) 46 47#define PB1000_MDR 0xBE000004 48 #define MDR_PI (1<<5) /* pcmcia int latch */ 49 #define MDR_EPI (1<<14) /* enable pcmcia int */ 50 #define MDR_CPI (1<<15) /* clear pcmcia int */ 51 52#define PB1000_ACR1 0xBE000008 53 #define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */ 54 #define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */ 55 #define ACR1_SLOT_0_READY (1<<2) /* ready */ 56 #define ACR1_SLOT_0_STATUS (1<<3) /* status change */ 57 #define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */ 58 #define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */ 59 #define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */ 60 #define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */ 61 #define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */ 62 #define ACR1_SLOT_1_READY (1<<10) /* ready */ 63 #define ACR1_SLOT_1_STATUS (1<<11) /* status change */ 64 #define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */ 65 #define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */ 66 #define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */ 67 68#define CPLD_AUX0 0xBE00000C 69#define CPLD_AUX1 0xBE000010 70#define CPLD_AUX2 0xBE000014 71 72/* Voltage levels */ 73 74/* VPPEN1 - VPPEN0 */ 75#define VPP_GND ((0<<1) | (0<<0)) 76#define VPP_5V ((1<<1) | (0<<0)) 77#define VPP_3V ((0<<1) | (1<<0)) 78#define VPP_12V ((0<<1) | (1<<0)) 79#define VPP_HIZ ((1<<1) | (1<<0)) 80 81/* VCCEN1 - VCCEN0 */ 82#define VCC_3V ((0<<1) | (1<<0)) 83#define VCC_5V ((1<<1) | (0<<0)) 84#define VCC_HIZ ((0<<1) | (0<<0)) 85 86/* VPP/VCC */ 87#define SET_VCC_VPP(VCC, VPP, SLOT)\ 88 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 89 90 91/* PCI PB1000 specific defines */ 92/* The reason these defines are here instead of au1000.h is because 93 * the Au1000 does not have a PCI bus controller so the PCI implementation 94 * on the some of the older Pb1000 boards was very board specific. 95 */ 96#define PCI_CONFIG_BASE 0xBA020000 /* the only external slot */ 97 98#define SDRAM_DEVID 0xBA010000 99#define SDRAM_CMD 0xBA010004 100#define SDRAM_CLASS 0xBA010008 101#define SDRAM_MISC 0xBA01000C 102#define SDRAM_MBAR 0xBA010010 103 104#define PCI_IO_DATA_PORT 0xBA800000 105 106#define PCI_IO_ADDR 0xBE00001C 107#define PCI_INT_ACK 0xBBC00000 108#define PCI_IO_READ 0xBBC00020 109#define PCI_IO_WRITE 0xBBC00030 110 111#define PCI_BRIDGE_CONFIG 0xBE000018 112 113#define PCI_IO_START 0x10000000 114#define PCI_IO_END 0x1000ffff 115#define PCI_MEM_START 0x18000000 116#define PCI_MEM_END 0x18ffffff 117 118#define PCI_FIRST_DEVFN 0 119#define PCI_LAST_DEVFN 1 120 121static inline u8 au_pci_io_readb(u32 addr) 122{ 123 writel(addr, PCI_IO_ADDR); 124 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG); 125 return (readl(PCI_IO_DATA_PORT) & 0xff); 126} 127 128static inline u16 au_pci_io_readw(u32 addr) 129{ 130 writel(addr, PCI_IO_ADDR); 131 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG); 132 return (readl(PCI_IO_DATA_PORT) & 0xffff); 133} 134 135static inline u32 au_pci_io_readl(u32 addr) 136{ 137 writel(addr, PCI_IO_ADDR); 138 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff), PCI_BRIDGE_CONFIG); 139 return readl(PCI_IO_DATA_PORT); 140} 141 142static inline void au_pci_io_writeb(u8 val, u32 addr) 143{ 144 writel(addr, PCI_IO_ADDR); 145 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG); 146 writel(val, PCI_IO_DATA_PORT); 147} 148 149static inline void au_pci_io_writew(u16 val, u32 addr) 150{ 151 writel(addr, PCI_IO_ADDR); 152 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG); 153 writel(val, PCI_IO_DATA_PORT); 154} 155 156static inline void au_pci_io_writel(u32 val, u32 addr) 157{ 158 writel(addr, PCI_IO_ADDR); 159 writel(readl(PCI_BRIDGE_CONFIG) & 0xffffcfff, PCI_BRIDGE_CONFIG); 160 writel(val, PCI_IO_DATA_PORT); 161} 162 163static inline void set_sdram_extbyte(void) 164{ 165 writel(readl(PCI_BRIDGE_CONFIG) & 0xffffff00, PCI_BRIDGE_CONFIG); 166} 167 168static inline void set_slot_extbyte(void) 169{ 170 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG); 171} 172#endif /* __ASM_PB1000_H */ 173