1/*
2 * Lowlevel hardware stuff for the MIPS based Cobalt microservers.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License.  See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1997 Cobalt Microserver
9 * Copyright (C) 1997, 2003 Ralf Baechle
10 * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv)
11 */
12#ifndef __ASM_COBALT_H
13#define __ASM_COBALT_H
14
15#include <irq.h>
16
17/*
18 * i8259 legacy interrupts used on Cobalt:
19 *
20 *     8  - RTC
21 *     9  - PCI
22 *    14  - IDE0
23 *    15  - IDE1
24 */
25#define COBALT_QUBE_SLOT_IRQ	9
26
27/*
28 * CPU IRQs  are 16 ... 23
29 */
30#define COBALT_CPU_IRQ		MIPS_CPU_IRQ_BASE
31
32#define COBALT_GALILEO_IRQ	(COBALT_CPU_IRQ + 2)
33#define COBALT_RAQ_SCSI_IRQ	(COBALT_CPU_IRQ + 3)
34#define COBALT_ETH0_IRQ		(COBALT_CPU_IRQ + 3)
35#define COBALT_QUBE1_ETH0_IRQ	(COBALT_CPU_IRQ + 4)
36#define COBALT_ETH1_IRQ		(COBALT_CPU_IRQ + 4)
37#define COBALT_SERIAL_IRQ	(COBALT_CPU_IRQ + 5)
38#define COBALT_SCSI_IRQ         (COBALT_CPU_IRQ + 5)
39#define COBALT_VIA_IRQ		(COBALT_CPU_IRQ + 6)	/* Chained to VIA ISA bridge */
40
41/*
42 * PCI configuration space manifest constants.  These are wired into
43 * the board layout according to the PCI spec to enable the software
44 * to probe the hardware configuration space in a well defined manner.
45 *
46 * The PCI_DEVSHFT() macro transforms these values into numbers
47 * suitable for passing as the dev parameter to the various
48 * pcibios_read/write_config routines.
49 */
50#define COBALT_PCICONF_CPU      0x06
51#define COBALT_PCICONF_ETH0     0x07
52#define COBALT_PCICONF_RAQSCSI  0x08
53#define COBALT_PCICONF_VIA      0x09
54#define COBALT_PCICONF_PCISLOT  0x0A
55#define COBALT_PCICONF_ETH1     0x0C
56
57
58/*
59 * The Cobalt board id information.  The boards have an ID number wired
60 * into the VIA that is available in the high nibble of register 94.
61 * This register is available in the VIA configuration space through the
62 * interface routines qube_pcibios_read/write_config. See cobalt/pci.c
63 */
64#define VIA_COBALT_BRD_ID_REG  0x94
65#define VIA_COBALT_BRD_REG_to_ID(reg)  ((unsigned char) (reg) >> 4)
66#define COBALT_BRD_ID_QUBE1    0x3
67#define COBALT_BRD_ID_RAQ1     0x4
68#define COBALT_BRD_ID_QUBE2    0x5
69#define COBALT_BRD_ID_RAQ2     0x6
70
71extern int cobalt_board_id;
72
73#define COBALT_LED_PORT		(*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
74# define COBALT_LED_BAR_LEFT	(1 << 0)	/* Qube */
75# define COBALT_LED_BAR_RIGHT	(1 << 1)	/* Qube */
76# define COBALT_LED_WEB		(1 << 2)	/* RaQ */
77# define COBALT_LED_POWER_OFF	(1 << 3)	/* RaQ */
78# define COBALT_LED_RESET	0x0f
79
80#define COBALT_KEY_PORT		((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK)
81# define COBALT_KEY_CLEAR	(1 << 1)
82# define COBALT_KEY_LEFT	(1 << 2)
83# define COBALT_KEY_UP		(1 << 3)
84# define COBALT_KEY_DOWN	(1 << 4)
85# define COBALT_KEY_RIGHT	(1 << 5)
86# define COBALT_KEY_ENTER	(1 << 6)
87# define COBALT_KEY_SELECT	(1 << 7)
88# define COBALT_KEY_MASK	0xfe
89
90#define COBALT_UART		((volatile unsigned char *) CKSEG1ADDR(0x1c800000))
91
92#endif /* __ASM_COBALT_H */
93