1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle 7 * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle 8 */ 9#ifndef _ASM_IRQ_H 10#define _ASM_IRQ_H 11 12#include <linux/linkage.h> 13 14#include <asm/mipsmtregs.h> 15 16#include <irq.h> 17 18#ifdef CONFIG_I8259 19static inline int irq_canonicalize(int irq) 20{ 21 return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq); 22} 23#else 24#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ 25#endif 26 27#ifdef CONFIG_MIPS_MT_SMTC 28/* 29 * Clear interrupt mask handling "backstop" if irq_hwmask 30 * entry so indicates. This implies that the ack() or end() 31 * functions will take over re-enabling the low-level mask. 32 * Otherwise it will be done on return from exception. 33 */ 34#define __DO_IRQ_SMTC_HOOK(irq) \ 35do { \ 36 if (irq_hwmask[irq] & 0x0000ff00) \ 37 write_c0_tccontext(read_c0_tccontext() & \ 38 ~(irq_hwmask[irq] & 0x0000ff00)); \ 39} while (0) 40#else 41#define __DO_IRQ_SMTC_HOOK(irq) do { } while (0) 42#endif 43 44/* 45 * do_IRQ handles all normal device IRQ's (the special 46 * SMP cross-CPU interrupts have their own specific 47 * handlers). 48 * 49 * Ideally there should be away to get this into kernel/irq/handle.c to 50 * avoid the overhead of a call for just a tiny function ... 51 */ 52#define do_IRQ(irq) \ 53do { \ 54 irq_enter(); \ 55 __DO_IRQ_SMTC_HOOK(irq); \ 56 generic_handle_irq(irq); \ 57 irq_exit(); \ 58} while (0) 59 60extern void arch_init_irq(void); 61extern void spurious_interrupt(void); 62 63#ifdef CONFIG_MIPS_MT_SMTC 64struct irqaction; 65 66extern unsigned long irq_hwmask[]; 67extern int setup_irq_smtc(unsigned int irq, struct irqaction * new, 68 unsigned long hwmask); 69#endif /* CONFIG_MIPS_MT_SMTC */ 70 71extern int allocate_irqno(void); 72extern void alloc_legacy_irqno(void); 73extern void free_irqno(unsigned int irq); 74 75/* 76 * Before R2 the timer and performance counter interrupts were both fixed to 77 * IE7. Since R2 their number has to be read from the c0_intctl register. 78 */ 79#define CP0_LEGACY_COMPARE_IRQ 7 80 81extern int cp0_compare_irq; 82extern int cp0_perfcount_irq; 83 84#endif /* _ASM_IRQ_H */ 85