1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2000 Harald Koerfgen 7 */ 8 9#ifndef __ASM_IP32_INTS_H 10#define __ASM_IP32_INTS_H 11 12/* 13 * This list reflects the assignment of interrupt numbers to 14 * interrupting events. Order is fairly irrelevant to handling 15 * priority. This differs from irix. 16 */ 17 18/* CPU */ 19#define IP32_R4K_TIMER_IRQ 0 20 21/* MACE */ 22#define MACE_VID_IN1_IRQ 1 23#define MACE_VID_IN2_IRQ 2 24#define MACE_VID_OUT_IRQ 3 25#define MACE_ETHERNET_IRQ 4 26/* SUPERIO, MISC, and AUDIO are MACEISA */ 27#define MACE_PCI_BRIDGE_IRQ 8 28 29/* MACEPCI */ 30#define MACEPCI_SCSI0_IRQ 9 31#define MACEPCI_SCSI1_IRQ 10 32#define MACEPCI_SLOT0_IRQ 11 33#define MACEPCI_SLOT1_IRQ 12 34#define MACEPCI_SLOT2_IRQ 13 35#define MACEPCI_SHARED0_IRQ 14 36#define MACEPCI_SHARED1_IRQ 15 37#define MACEPCI_SHARED2_IRQ 16 38 39/* CRIME */ 40#define CRIME_GBE0_IRQ 17 41#define CRIME_GBE1_IRQ 18 42#define CRIME_GBE2_IRQ 19 43#define CRIME_GBE3_IRQ 20 44#define CRIME_CPUERR_IRQ 21 45#define CRIME_MEMERR_IRQ 22 46#define CRIME_RE_EMPTY_E_IRQ 23 47#define CRIME_RE_FULL_E_IRQ 24 48#define CRIME_RE_IDLE_E_IRQ 25 49#define CRIME_RE_EMPTY_L_IRQ 26 50#define CRIME_RE_FULL_L_IRQ 27 51#define CRIME_RE_IDLE_L_IRQ 28 52#define CRIME_SOFT0_IRQ 29 53#define CRIME_SOFT1_IRQ 30 54#define CRIME_SOFT2_IRQ 31 55#define CRIME_SYSCORERR_IRQ CRIME_SOFT2_IRQ 56#define CRIME_VICE_IRQ 32 57 58/* MACEISA */ 59#define MACEISA_AUDIO_SW_IRQ 33 60#define MACEISA_AUDIO_SC_IRQ 34 61#define MACEISA_AUDIO1_DMAT_IRQ 35 62#define MACEISA_AUDIO1_OF_IRQ 36 63#define MACEISA_AUDIO2_DMAT_IRQ 37 64#define MACEISA_AUDIO2_MERR_IRQ 38 65#define MACEISA_AUDIO3_DMAT_IRQ 39 66#define MACEISA_AUDIO3_MERR_IRQ 40 67#define MACEISA_RTC_IRQ 41 68#define MACEISA_KEYB_IRQ 42 69/* MACEISA_KEYB_POLL is not an IRQ */ 70#define MACEISA_MOUSE_IRQ 44 71/* MACEISA_MOUSE_POLL is not an IRQ */ 72#define MACEISA_TIMER0_IRQ 46 73#define MACEISA_TIMER1_IRQ 47 74#define MACEISA_TIMER2_IRQ 48 75#define MACEISA_PARALLEL_IRQ 49 76#define MACEISA_PAR_CTXA_IRQ 50 77#define MACEISA_PAR_CTXB_IRQ 51 78#define MACEISA_PAR_MERR_IRQ 52 79#define MACEISA_SERIAL1_IRQ 53 80#define MACEISA_SERIAL1_TDMAT_IRQ 54 81#define MACEISA_SERIAL1_TDMAPR_IRQ 55 82#define MACEISA_SERIAL1_TDMAME_IRQ 56 83#define MACEISA_SERIAL1_RDMAT_IRQ 57 84#define MACEISA_SERIAL1_RDMAOR_IRQ 58 85#define MACEISA_SERIAL2_IRQ 59 86#define MACEISA_SERIAL2_TDMAT_IRQ 60 87#define MACEISA_SERIAL2_TDMAPR_IRQ 61 88#define MACEISA_SERIAL2_TDMAME_IRQ 62 89#define MACEISA_SERIAL2_RDMAT_IRQ 63 90#define MACEISA_SERIAL2_RDMAOR_IRQ 64 91 92#define IP32_IRQ_MAX MACEISA_SERIAL2_RDMAOR_IRQ 93 94#endif /* __ASM_IP32_INTS_H */ 95