1/* 2 * cpu.h: Values of the PRId register used to match up 3 * various MIPS cpu types. 4 * 5 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) 6 * Copyright (C) 2004 Maciej W. Rozycki 7 */ 8#ifndef _ASM_CPU_H 9#define _ASM_CPU_H 10 11/* Assigned Company values for bits 23:16 of the PRId Register 12 (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from 13 MTI, the PRId register is defined in this (backwards compatible) 14 way: 15 16 +----------------+----------------+----------------+----------------+ 17 | Company Options| Company ID | Processor ID | Revision | 18 +----------------+----------------+----------------+----------------+ 19 31 24 23 16 15 8 7 20 21 I don't have docs for all the previous processors, but my impression is 22 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 23 spec. 24*/ 25 26#define PRID_COMP_LEGACY 0x000000 27#define PRID_COMP_MIPS 0x010000 28#define PRID_COMP_BROADCOM 0x020000 29#define PRID_COMP_ALCHEMY 0x030000 30#define PRID_COMP_SIBYTE 0x040000 31#define PRID_COMP_SANDCRAFT 0x050000 32#define PRID_COMP_PHILIPS 0x060000 33#define PRID_COMP_TOSHIBA 0x070000 34#define PRID_COMP_LSI 0x080000 35#define PRID_COMP_LEXRA 0x0b0000 36 37 38/* 39 * Assigned values for the product ID register. In order to detect a 40 * certain CPU type exactly eventually additional registers may need to 41 * be examined. These are valid when 23:16 == PRID_COMP_LEGACY 42 */ 43#define PRID_IMP_R2000 0x0100 44#define PRID_IMP_AU1_REV1 0x0100 45#define PRID_IMP_AU1_REV2 0x0200 46#define PRID_IMP_R3000 0x0200 /* Same as R2000A */ 47#define PRID_IMP_R6000 0x0300 /* Same as R3000A */ 48#define PRID_IMP_R4000 0x0400 49#define PRID_IMP_R6000A 0x0600 50#define PRID_IMP_R10000 0x0900 51#define PRID_IMP_R4300 0x0b00 52#define PRID_IMP_VR41XX 0x0c00 53#define PRID_IMP_R12000 0x0e00 54#define PRID_IMP_R14000 0x0f00 55#define PRID_IMP_R8000 0x1000 56#define PRID_IMP_PR4450 0x1200 57#define PRID_IMP_R4600 0x2000 58#define PRID_IMP_R4700 0x2100 59#define PRID_IMP_TX39 0x2200 60#define PRID_IMP_R4640 0x2200 61#define PRID_IMP_R4650 0x2200 /* Same as R4640 */ 62#define PRID_IMP_R5000 0x2300 63#define PRID_IMP_TX49 0x2d00 64#define PRID_IMP_SONIC 0x2400 65#define PRID_IMP_MAGIC 0x2500 66#define PRID_IMP_RM7000 0x2700 67#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ 68#define PRID_IMP_RM9000 0x3400 69#define PRID_IMP_R5432 0x5400 70#define PRID_IMP_R5500 0x5500 71 72#define PRID_IMP_UNKNOWN 0xff00 73 74/* 75 * These are the PRID's for when 23:16 == PRID_COMP_MIPS 76 */ 77 78#define PRID_IMP_4KC 0x8000 79#define PRID_IMP_5KC 0x8100 80#define PRID_IMP_20KC 0x8200 81#define PRID_IMP_4KEC 0x8400 82#define PRID_IMP_4KSC 0x8600 83#define PRID_IMP_25KF 0x8800 84#define PRID_IMP_5KE 0x8900 85#define PRID_IMP_4KECR2 0x9000 86#define PRID_IMP_4KEMPR2 0x9100 87#define PRID_IMP_4KSD 0x9200 88#define PRID_IMP_24K 0x9300 89#define PRID_IMP_34K 0x9500 90#define PRID_IMP_24KE 0x9600 91#define PRID_IMP_74K 0x9700 92#define PRID_IMP_BCM4710 0x4000 93#define PRID_IMP_BCM3302 0x9000 94#define PRID_IMP_BCM3303 0x9100 95 96#define PRID_COPT_MASK 0xff000000 97#define PRID_COMP_MASK 0x00ff0000 98#define PRID_IMP_MASK 0x0000ff00 99#define PRID_REV_MASK 0x000000ff 100 101#define BCM330X(id) \ 102 (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \ 103 || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303))) 104 105 106/* 107 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 108 */ 109 110#define PRID_IMP_SB1 0x0100 111#define PRID_IMP_SB1A 0x1100 112 113/* 114 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT 115 */ 116 117#define PRID_IMP_SR71000 0x0400 118 119/* 120 * Definitions for 7:0 on legacy processors 121 */ 122 123 124#define PRID_REV_TX4927 0x0022 125#define PRID_REV_TX4937 0x0030 126#define PRID_REV_R4400 0x0040 127#define PRID_REV_R3000A 0x0030 128#define PRID_REV_R3000 0x0020 129#define PRID_REV_R2000A 0x0010 130#define PRID_REV_TX3912 0x0010 131#define PRID_REV_TX3922 0x0030 132#define PRID_REV_TX3927 0x0040 133#define PRID_REV_VR4111 0x0050 134#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ 135#define PRID_REV_VR4121 0x0060 136#define PRID_REV_VR4122 0x0070 137#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 138#define PRID_REV_VR4130 0x0080 139 140/* 141 * Older processors used to encode processor version and revision in two 142 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores 143 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as 144 * the patch number. *ARGH* 145 */ 146#define PRID_REV_ENCODE_44(ver, rev) \ 147 ((ver) << 4 | (rev)) 148#define PRID_REV_ENCODE_332(ver, rev, patch) \ 149 ((ver) << 5 | (rev) << 2 | (patch)) 150 151/* 152 * FPU implementation/revision register (CP1 control register 0). 153 * 154 * +---------------------------------+----------------+----------------+ 155 * | 0 | Implementation | Revision | 156 * +---------------------------------+----------------+----------------+ 157 * 31 16 15 8 7 0 158 */ 159 160#define FPIR_IMP_NONE 0x0000 161 162#define CPU_UNKNOWN 0 163#define CPU_R2000 1 164#define CPU_R3000 2 165#define CPU_R3000A 3 166#define CPU_R3041 4 167#define CPU_R3051 5 168#define CPU_R3052 6 169#define CPU_R3081 7 170#define CPU_R3081E 8 171#define CPU_R4000PC 9 172#define CPU_R4000SC 10 173#define CPU_R4000MC 11 174#define CPU_R4200 12 175#define CPU_R4400PC 13 176#define CPU_R4400SC 14 177#define CPU_R4400MC 15 178#define CPU_R4600 16 179#define CPU_R6000 17 180#define CPU_R6000A 18 181#define CPU_R8000 19 182#define CPU_R10000 20 183#define CPU_R12000 21 184#define CPU_R4300 22 185#define CPU_R4650 23 186#define CPU_R4700 24 187#define CPU_R5000 25 188#define CPU_R5000A 26 189#define CPU_R4640 27 190#define CPU_NEVADA 28 191#define CPU_RM7000 29 192#define CPU_R5432 30 193#define CPU_4KC 31 194#define CPU_5KC 32 195#define CPU_R4310 33 196#define CPU_SB1 34 197#define CPU_TX3912 35 198#define CPU_TX3922 36 199#define CPU_TX3927 37 200#define CPU_AU1000 38 201#define CPU_4KEC 39 202#define CPU_4KSC 40 203#define CPU_VR41XX 41 204#define CPU_R5500 42 205#define CPU_TX49XX 43 206#define CPU_AU1500 44 207#define CPU_20KC 45 208#define CPU_VR4111 46 209#define CPU_VR4121 47 210#define CPU_VR4122 48 211#define CPU_VR4131 49 212#define CPU_VR4181 50 213#define CPU_VR4181A 51 214#define CPU_AU1100 52 215#define CPU_SR71000 53 216#define CPU_RM9000 54 217#define CPU_25KF 55 218#define CPU_VR4133 56 219#define CPU_AU1550 57 220#define CPU_24K 58 221#define CPU_AU1200 59 222#define CPU_34K 60 223#define CPU_PR4450 61 224#define CPU_SB1A 62 225#define CPU_74K 63 226#define CPU_R14000 64 227#define CPU_BCM4710 65 228#define CPU_BCM3302 66 229#define CPU_LAST 66 230 231/* 232 * ISA Level encodings 233 * 234 */ 235#define MIPS_CPU_ISA_I 0x00000001 236#define MIPS_CPU_ISA_II 0x00000002 237#define MIPS_CPU_ISA_III 0x00000004 238#define MIPS_CPU_ISA_IV 0x00000008 239#define MIPS_CPU_ISA_V 0x00000010 240#define MIPS_CPU_ISA_M32R1 0x00000020 241#define MIPS_CPU_ISA_M32R2 0x00000040 242#define MIPS_CPU_ISA_M64R1 0x00000080 243#define MIPS_CPU_ISA_M64R2 0x00000100 244 245#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ 246 MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) 247#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 248 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) 249 250/* 251 * CPU Option encodings 252 */ 253#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ 254#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */ 255#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ 256#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ 257#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ 258#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */ 259#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */ 260#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */ 261#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */ 262#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */ 263#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */ 264#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */ 265#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */ 266#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */ 267#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */ 268#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ 269#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ 270#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ 271#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */ 272#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ 273#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ 274#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ 275 276/* 277 * CPU ASE encodings 278 */ 279#define MIPS_ASE_MIPS16 0x00000001 /* code compression */ 280#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ 281#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ 282#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ 283#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ 284#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ 285 286 287#endif /* _ASM_CPU_H */ 288