1/* $Id: pgtable.h,v 1.1.1.1 2007/08/03 18:53:36 Exp $ 2 * pgtable.h: SpitFire page table operations. 3 * 4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8#ifndef _SPARC64_PGTABLE_H 9#define _SPARC64_PGTABLE_H 10 11/* This file contains the functions and defines necessary to modify and use 12 * the SpitFire page tables. 13 */ 14 15#include <asm-generic/pgtable-nopud.h> 16 17#include <linux/compiler.h> 18#include <linux/const.h> 19#include <asm/types.h> 20#include <asm/spitfire.h> 21#include <asm/asi.h> 22#include <asm/system.h> 23#include <asm/page.h> 24#include <asm/processor.h> 25 26/* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB). 27 * The page copy blockops can use 0x2000000 to 0x4000000. 28 * The TSB is mapped in the 0x4000000 to 0x6000000 range. 29 * The PROM resides in an area spanning 0xf0000000 to 0x100000000. 30 * The vmalloc area spans 0x100000000 to 0x200000000. 31 * Since modules need to be in the lowest 32-bits of the address space, 32 * we place them right before the OBP area from 0x10000000 to 0xf0000000. 33 * There is a single static kernel PMD which maps from 0x0 to address 34 * 0x400000000. 35 */ 36#define TLBTEMP_BASE _AC(0x0000000002000000,UL) 37#define TSBMAP_BASE _AC(0x0000000004000000,UL) 38#define MODULES_VADDR _AC(0x0000000010000000,UL) 39#define MODULES_LEN _AC(0x00000000e0000000,UL) 40#define MODULES_END _AC(0x00000000f0000000,UL) 41#define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) 42#define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) 43#define VMALLOC_START _AC(0x0000000100000000,UL) 44#define VMALLOC_END _AC(0x0000000200000000,UL) 45 46/* 47 * Given a virtual address, the lowest PAGE_SHIFT bits determine offset 48 * into the page; the next higher PAGE_SHIFT-3 bits determine the pte# 49 * in the proper pagetable (the -3 is from the 8 byte ptes, and each page 50 * table is a single page long). The next higher PMD_BITS determine pmd# 51 * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2) 52 * since the pmd entries are 4 bytes, and each pmd page is a single page 53 * long). Finally, the higher few bits determine pgde#. 54 */ 55 56/* PMD_SHIFT determines the size of the area a second-level page 57 * table can map 58 */ 59#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) 60#define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 61#define PMD_MASK (~(PMD_SIZE-1)) 62#define PMD_BITS (PAGE_SHIFT - 2) 63 64/* PGDIR_SHIFT determines what a third-level page table entry can map */ 65#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS) 66#define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 67#define PGDIR_MASK (~(PGDIR_SIZE-1)) 68#define PGDIR_BITS (PAGE_SHIFT - 2) 69 70#ifndef __ASSEMBLY__ 71 72#include <linux/sched.h> 73 74/* Entries per page directory level. */ 75#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) 76#define PTRS_PER_PMD (1UL << PMD_BITS) 77#define PTRS_PER_PGD (1UL << PGDIR_BITS) 78 79/* Kernel has a separate 44bit address space. */ 80#define FIRST_USER_ADDRESS 0 81 82#define pte_ERROR(e) __builtin_trap() 83#define pmd_ERROR(e) __builtin_trap() 84#define pgd_ERROR(e) __builtin_trap() 85 86#endif /* !(__ASSEMBLY__) */ 87 88/* PTE bits which are the same in SUN4U and SUN4V format. */ 89#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ 90#define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ 91 92/* SUN4U pte bits... */ 93#define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ 94#define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ 95#define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ 96#define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ 97#define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ 98#define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ 99#define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ 100#define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ 101#define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ 102#define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ 103#define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ 104#define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ 105#define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ 106#define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ 107#define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ 108#define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ 109#define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ 110#define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */ 111#define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ 112#define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ 113#define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ 114#define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ 115#define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ 116#define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ 117#define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ 118#define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ 119#define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ 120#define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ 121 122/* SUN4V pte bits... */ 123#define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ 124#define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ 125#define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ 126#define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ 127#define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ 128#define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ 129#define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ 130#define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ 131#define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ 132#define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ 133#define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ 134#define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ 135#define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ 136#define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ 137#define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ 138#define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */ 139#define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ 140#define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ 141#define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ 142#define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ 143#define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ 144#define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ 145#define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ 146#define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ 147#define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ 148#define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ 149#define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ 150 151#if PAGE_SHIFT == 13 152#define _PAGE_SZBITS_4U _PAGE_SZ8K_4U 153#define _PAGE_SZBITS_4V _PAGE_SZ8K_4V 154#elif PAGE_SHIFT == 16 155#define _PAGE_SZBITS_4U _PAGE_SZ64K_4U 156#define _PAGE_SZBITS_4V _PAGE_SZ64K_4V 157#elif PAGE_SHIFT == 19 158#define _PAGE_SZBITS_4U _PAGE_SZ512K_4U 159#define _PAGE_SZBITS_4V _PAGE_SZ512K_4V 160#elif PAGE_SHIFT == 22 161#define _PAGE_SZBITS_4U _PAGE_SZ4MB_4U 162#define _PAGE_SZBITS_4V _PAGE_SZ4MB_4V 163#else 164#error Wrong PAGE_SHIFT specified 165#endif 166 167#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB) 168#define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U 169#define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V 170#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K) 171#define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U 172#define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V 173#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K) 174#define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U 175#define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V 176#endif 177 178/* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ 179#define __P000 __pgprot(0) 180#define __P001 __pgprot(0) 181#define __P010 __pgprot(0) 182#define __P011 __pgprot(0) 183#define __P100 __pgprot(0) 184#define __P101 __pgprot(0) 185#define __P110 __pgprot(0) 186#define __P111 __pgprot(0) 187 188#define __S000 __pgprot(0) 189#define __S001 __pgprot(0) 190#define __S010 __pgprot(0) 191#define __S011 __pgprot(0) 192#define __S100 __pgprot(0) 193#define __S101 __pgprot(0) 194#define __S110 __pgprot(0) 195#define __S111 __pgprot(0) 196 197#ifndef __ASSEMBLY__ 198 199extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); 200 201extern unsigned long pte_sz_bits(unsigned long size); 202 203extern pgprot_t PAGE_KERNEL; 204extern pgprot_t PAGE_KERNEL_LOCKED; 205extern pgprot_t PAGE_COPY; 206extern pgprot_t PAGE_SHARED; 207 208extern unsigned long _PAGE_IE; 209extern unsigned long _PAGE_E; 210extern unsigned long _PAGE_CACHE; 211 212extern unsigned long pg_iobits; 213extern unsigned long _PAGE_ALL_SZ_BITS; 214extern unsigned long _PAGE_SZBITS; 215 216extern struct page *mem_map_zero; 217#define ZERO_PAGE(vaddr) (mem_map_zero) 218 219/* PFNs are real physical page numbers. However, mem_map only begins to record 220 * per-page information starting at pfn_base. This is to handle systems where 221 * the first physical page in the machine is at some huge physical address, 222 * such as 4GB. This is common on a partitioned E10000, for example. 223 */ 224static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 225{ 226 unsigned long paddr = pfn << PAGE_SHIFT; 227 unsigned long sz_bits; 228 229 sz_bits = 0UL; 230 if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) { 231 __asm__ __volatile__( 232 "\n661: sethi %%uhi(%1), %0\n" 233 " sllx %0, 32, %0\n" 234 " .section .sun4v_2insn_patch, \"ax\"\n" 235 " .word 661b\n" 236 " mov %2, %0\n" 237 " nop\n" 238 " .previous\n" 239 : "=r" (sz_bits) 240 : "i" (_PAGE_SZBITS_4U), "i" (_PAGE_SZBITS_4V)); 241 } 242 return __pte(paddr | sz_bits | pgprot_val(prot)); 243} 244#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 245 246/* This one can be done with two shifts. */ 247static inline unsigned long pte_pfn(pte_t pte) 248{ 249 unsigned long ret; 250 251 __asm__ __volatile__( 252 "\n661: sllx %1, %2, %0\n" 253 " srlx %0, %3, %0\n" 254 " .section .sun4v_2insn_patch, \"ax\"\n" 255 " .word 661b\n" 256 " sllx %1, %4, %0\n" 257 " srlx %0, %5, %0\n" 258 " .previous\n" 259 : "=r" (ret) 260 : "r" (pte_val(pte)), 261 "i" (21), "i" (21 + PAGE_SHIFT), 262 "i" (8), "i" (8 + PAGE_SHIFT)); 263 264 return ret; 265} 266#define pte_page(x) pfn_to_page(pte_pfn(x)) 267 268static inline pte_t pte_modify(pte_t pte, pgprot_t prot) 269{ 270 unsigned long mask, tmp; 271 272 /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347) 273 * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8) 274 * 275 * Even if we use negation tricks the result is still a 6 276 * instruction sequence, so don't try to play fancy and just 277 * do the most straightforward implementation. 278 * 279 * Note: We encode this into 3 sun4v 2-insn patch sequences. 280 */ 281 282 __asm__ __volatile__( 283 "\n661: sethi %%uhi(%2), %1\n" 284 " sethi %%hi(%2), %0\n" 285 "\n662: or %1, %%ulo(%2), %1\n" 286 " or %0, %%lo(%2), %0\n" 287 "\n663: sllx %1, 32, %1\n" 288 " or %0, %1, %0\n" 289 " .section .sun4v_2insn_patch, \"ax\"\n" 290 " .word 661b\n" 291 " sethi %%uhi(%3), %1\n" 292 " sethi %%hi(%3), %0\n" 293 " .word 662b\n" 294 " or %1, %%ulo(%3), %1\n" 295 " or %0, %%lo(%3), %0\n" 296 " .word 663b\n" 297 " sllx %1, 32, %1\n" 298 " or %0, %1, %0\n" 299 " .previous\n" 300 : "=r" (mask), "=r" (tmp) 301 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | 302 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U | 303 _PAGE_SZBITS_4U), 304 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 305 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V | 306 _PAGE_SZBITS_4V)); 307 308 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); 309} 310 311static inline pte_t pgoff_to_pte(unsigned long off) 312{ 313 off <<= PAGE_SHIFT; 314 315 __asm__ __volatile__( 316 "\n661: or %0, %2, %0\n" 317 " .section .sun4v_1insn_patch, \"ax\"\n" 318 " .word 661b\n" 319 " or %0, %3, %0\n" 320 " .previous\n" 321 : "=r" (off) 322 : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V)); 323 324 return __pte(off); 325} 326 327static inline pgprot_t pgprot_noncached(pgprot_t prot) 328{ 329 unsigned long val = pgprot_val(prot); 330 331 __asm__ __volatile__( 332 "\n661: andn %0, %2, %0\n" 333 " or %0, %3, %0\n" 334 " .section .sun4v_2insn_patch, \"ax\"\n" 335 " .word 661b\n" 336 " andn %0, %4, %0\n" 337 " or %0, %5, %0\n" 338 " .previous\n" 339 : "=r" (val) 340 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), 341 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V)); 342 343 return __pgprot(val); 344} 345/* Various pieces of code check for platform support by ifdef testing 346 * on "pgprot_noncached". That's broken and should be fixed, but for 347 * now... 348 */ 349#define pgprot_noncached pgprot_noncached 350 351#ifdef CONFIG_HUGETLB_PAGE 352static inline pte_t pte_mkhuge(pte_t pte) 353{ 354 unsigned long mask; 355 356 __asm__ __volatile__( 357 "\n661: sethi %%uhi(%1), %0\n" 358 " sllx %0, 32, %0\n" 359 " .section .sun4v_2insn_patch, \"ax\"\n" 360 " .word 661b\n" 361 " mov %2, %0\n" 362 " nop\n" 363 " .previous\n" 364 : "=r" (mask) 365 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); 366 367 return __pte(pte_val(pte) | mask); 368} 369#endif 370 371static inline pte_t pte_mkdirty(pte_t pte) 372{ 373 unsigned long val = pte_val(pte), tmp; 374 375 __asm__ __volatile__( 376 "\n661: or %0, %3, %0\n" 377 " nop\n" 378 "\n662: nop\n" 379 " nop\n" 380 " .section .sun4v_2insn_patch, \"ax\"\n" 381 " .word 661b\n" 382 " sethi %%uhi(%4), %1\n" 383 " sllx %1, 32, %1\n" 384 " .word 662b\n" 385 " or %1, %%lo(%4), %1\n" 386 " or %0, %1, %0\n" 387 " .previous\n" 388 : "=r" (val), "=r" (tmp) 389 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 390 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 391 392 return __pte(val); 393} 394 395static inline pte_t pte_mkclean(pte_t pte) 396{ 397 unsigned long val = pte_val(pte), tmp; 398 399 __asm__ __volatile__( 400 "\n661: andn %0, %3, %0\n" 401 " nop\n" 402 "\n662: nop\n" 403 " nop\n" 404 " .section .sun4v_2insn_patch, \"ax\"\n" 405 " .word 661b\n" 406 " sethi %%uhi(%4), %1\n" 407 " sllx %1, 32, %1\n" 408 " .word 662b\n" 409 " or %1, %%lo(%4), %1\n" 410 " andn %0, %1, %0\n" 411 " .previous\n" 412 : "=r" (val), "=r" (tmp) 413 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 414 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 415 416 return __pte(val); 417} 418 419static inline pte_t pte_mkwrite(pte_t pte) 420{ 421 unsigned long val = pte_val(pte), mask; 422 423 __asm__ __volatile__( 424 "\n661: mov %1, %0\n" 425 " nop\n" 426 " .section .sun4v_2insn_patch, \"ax\"\n" 427 " .word 661b\n" 428 " sethi %%uhi(%2), %0\n" 429 " sllx %0, 32, %0\n" 430 " .previous\n" 431 : "=r" (mask) 432 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 433 434 return __pte(val | mask); 435} 436 437static inline pte_t pte_wrprotect(pte_t pte) 438{ 439 unsigned long val = pte_val(pte), tmp; 440 441 __asm__ __volatile__( 442 "\n661: andn %0, %3, %0\n" 443 " nop\n" 444 "\n662: nop\n" 445 " nop\n" 446 " .section .sun4v_2insn_patch, \"ax\"\n" 447 " .word 661b\n" 448 " sethi %%uhi(%4), %1\n" 449 " sllx %1, 32, %1\n" 450 " .word 662b\n" 451 " or %1, %%lo(%4), %1\n" 452 " andn %0, %1, %0\n" 453 " .previous\n" 454 : "=r" (val), "=r" (tmp) 455 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), 456 "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); 457 458 return __pte(val); 459} 460 461static inline pte_t pte_mkold(pte_t pte) 462{ 463 unsigned long mask; 464 465 __asm__ __volatile__( 466 "\n661: mov %1, %0\n" 467 " nop\n" 468 " .section .sun4v_2insn_patch, \"ax\"\n" 469 " .word 661b\n" 470 " sethi %%uhi(%2), %0\n" 471 " sllx %0, 32, %0\n" 472 " .previous\n" 473 : "=r" (mask) 474 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 475 476 mask |= _PAGE_R; 477 478 return __pte(pte_val(pte) & ~mask); 479} 480 481static inline pte_t pte_mkyoung(pte_t pte) 482{ 483 unsigned long mask; 484 485 __asm__ __volatile__( 486 "\n661: mov %1, %0\n" 487 " nop\n" 488 " .section .sun4v_2insn_patch, \"ax\"\n" 489 " .word 661b\n" 490 " sethi %%uhi(%2), %0\n" 491 " sllx %0, 32, %0\n" 492 " .previous\n" 493 : "=r" (mask) 494 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 495 496 mask |= _PAGE_R; 497 498 return __pte(pte_val(pte) | mask); 499} 500 501static inline unsigned long pte_young(pte_t pte) 502{ 503 unsigned long mask; 504 505 __asm__ __volatile__( 506 "\n661: mov %1, %0\n" 507 " nop\n" 508 " .section .sun4v_2insn_patch, \"ax\"\n" 509 " .word 661b\n" 510 " sethi %%uhi(%2), %0\n" 511 " sllx %0, 32, %0\n" 512 " .previous\n" 513 : "=r" (mask) 514 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 515 516 return (pte_val(pte) & mask); 517} 518 519static inline unsigned long pte_dirty(pte_t pte) 520{ 521 unsigned long mask; 522 523 __asm__ __volatile__( 524 "\n661: mov %1, %0\n" 525 " nop\n" 526 " .section .sun4v_2insn_patch, \"ax\"\n" 527 " .word 661b\n" 528 " sethi %%uhi(%2), %0\n" 529 " sllx %0, 32, %0\n" 530 " .previous\n" 531 : "=r" (mask) 532 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); 533 534 return (pte_val(pte) & mask); 535} 536 537static inline unsigned long pte_write(pte_t pte) 538{ 539 unsigned long mask; 540 541 __asm__ __volatile__( 542 "\n661: mov %1, %0\n" 543 " nop\n" 544 " .section .sun4v_2insn_patch, \"ax\"\n" 545 " .word 661b\n" 546 " sethi %%uhi(%2), %0\n" 547 " sllx %0, 32, %0\n" 548 " .previous\n" 549 : "=r" (mask) 550 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 551 552 return (pte_val(pte) & mask); 553} 554 555static inline unsigned long pte_exec(pte_t pte) 556{ 557 unsigned long mask; 558 559 __asm__ __volatile__( 560 "\n661: sethi %%hi(%1), %0\n" 561 " .section .sun4v_1insn_patch, \"ax\"\n" 562 " .word 661b\n" 563 " mov %2, %0\n" 564 " .previous\n" 565 : "=r" (mask) 566 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); 567 568 return (pte_val(pte) & mask); 569} 570 571static inline unsigned long pte_read(pte_t pte) 572{ 573 unsigned long mask; 574 575 __asm__ __volatile__( 576 "\n661: mov %1, %0\n" 577 " nop\n" 578 " .section .sun4v_2insn_patch, \"ax\"\n" 579 " .word 661b\n" 580 " sethi %%uhi(%2), %0\n" 581 " sllx %0, 32, %0\n" 582 " .previous\n" 583 : "=r" (mask) 584 : "i" (_PAGE_READ_4U), "i" (_PAGE_READ_4V)); 585 586 return (pte_val(pte) & mask); 587} 588 589static inline unsigned long pte_file(pte_t pte) 590{ 591 unsigned long val = pte_val(pte); 592 593 __asm__ __volatile__( 594 "\n661: and %0, %2, %0\n" 595 " .section .sun4v_1insn_patch, \"ax\"\n" 596 " .word 661b\n" 597 " and %0, %3, %0\n" 598 " .previous\n" 599 : "=r" (val) 600 : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V)); 601 602 return val; 603} 604 605static inline unsigned long pte_present(pte_t pte) 606{ 607 unsigned long val = pte_val(pte); 608 609 __asm__ __volatile__( 610 "\n661: and %0, %2, %0\n" 611 " .section .sun4v_1insn_patch, \"ax\"\n" 612 " .word 661b\n" 613 " and %0, %3, %0\n" 614 " .previous\n" 615 : "=r" (val) 616 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); 617 618 return val; 619} 620 621#define pmd_set(pmdp, ptep) \ 622 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL)) 623#define pud_set(pudp, pmdp) \ 624 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL)) 625#define __pmd_page(pmd) \ 626 ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL))) 627#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 628#define pud_page_vaddr(pud) \ 629 ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL))) 630#define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) 631#define pmd_none(pmd) (!pmd_val(pmd)) 632#define pmd_bad(pmd) (0) 633#define pmd_present(pmd) (pmd_val(pmd) != 0U) 634#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U) 635#define pud_none(pud) (!pud_val(pud)) 636#define pud_bad(pud) (0) 637#define pud_present(pud) (pud_val(pud) != 0U) 638#define pud_clear(pudp) (pud_val(*(pudp)) = 0U) 639 640/* Same in both SUN4V and SUN4U. */ 641#define pte_none(pte) (!pte_val(pte)) 642 643/* to find an entry in a page-table-directory. */ 644#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 645#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 646 647/* to find an entry in a kernel page-table-directory */ 648#define pgd_offset_k(address) pgd_offset(&init_mm, address) 649 650/* Find an entry in the second-level page table.. */ 651#define pmd_offset(pudp, address) \ 652 ((pmd_t *) pud_page_vaddr(*(pudp)) + \ 653 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))) 654 655/* Find an entry in the third-level page table.. */ 656#define pte_index(dir, address) \ 657 ((pte_t *) __pmd_page(*(dir)) + \ 658 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) 659#define pte_offset_kernel pte_index 660#define pte_offset_map pte_index 661#define pte_offset_map_nested pte_index 662#define pte_unmap(pte) do { } while (0) 663#define pte_unmap_nested(pte) do { } while (0) 664 665/* Actual page table PTE updates. */ 666extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig); 667 668static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte) 669{ 670 pte_t orig = *ptep; 671 672 *ptep = pte; 673 674 /* It is more efficient to let flush_tlb_kernel_range() 675 * handle init_mm tlb flushes. 676 * 677 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U 678 * and SUN4V pte layout, so this inline test is fine. 679 */ 680 if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID)) 681 tlb_batch_add(mm, addr, ptep, orig); 682} 683 684#define pte_clear(mm,addr,ptep) \ 685 set_pte_at((mm), (addr), (ptep), __pte(0UL)) 686 687#ifdef DCACHE_ALIASING_POSSIBLE 688#define __HAVE_ARCH_MOVE_PTE 689#define move_pte(pte, prot, old_addr, new_addr) \ 690({ \ 691 pte_t newpte = (pte); \ 692 if (tlb_type != hypervisor && pte_present(pte)) { \ 693 unsigned long this_pfn = pte_pfn(pte); \ 694 \ 695 if (pfn_valid(this_pfn) && \ 696 (((old_addr) ^ (new_addr)) & (1 << 13))) \ 697 flush_dcache_page_all(current->mm, \ 698 pfn_to_page(this_pfn)); \ 699 } \ 700 newpte; \ 701}) 702#endif 703 704extern pgd_t swapper_pg_dir[2048]; 705extern pmd_t swapper_low_pmd_dir[2048]; 706 707extern void paging_init(void); 708extern unsigned long find_ecache_flush_span(unsigned long size); 709 710/* These do nothing with the way I have things setup. */ 711#define mmu_lockarea(vaddr, len) (vaddr) 712#define mmu_unlockarea(vaddr, len) do { } while(0) 713 714struct vm_area_struct; 715extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); 716 717/* Encode and de-code a swap entry */ 718#define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) 719#define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) 720#define __swp_entry(type, offset) \ 721 ( (swp_entry_t) \ 722 { \ 723 (((long)(type) << PAGE_SHIFT) | \ 724 ((long)(offset) << (PAGE_SHIFT + 8UL))) \ 725 } ) 726#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 727#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 728 729/* File offset in PTE support. */ 730extern unsigned long pte_file(pte_t); 731#define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT) 732extern pte_t pgoff_to_pte(unsigned long); 733#define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL) 734 735extern unsigned long *sparc64_valid_addr_bitmap; 736 737/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ 738#define kern_addr_valid(addr) \ 739 (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap)) 740 741extern int page_in_phys_avail(unsigned long paddr); 742 743extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, 744 unsigned long pfn, 745 unsigned long size, pgprot_t prot); 746 747/* 748 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in 749 * its high 4 bits. These macros/functions put it there or get it from there. 750 */ 751#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) 752#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) 753#define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) 754 755#include <asm-generic/pgtable.h> 756 757/* We provide our own get_unmapped_area to cope with VA holes and 758 * SHM area cache aliasing for userland. 759 */ 760#define HAVE_ARCH_UNMAPPED_AREA 761#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 762 763/* We provide a special get_unmapped_area for framebuffer mmaps to try and use 764 * the largest alignment possible such that larget PTEs can be used. 765 */ 766extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, 767 unsigned long, unsigned long, 768 unsigned long); 769#define HAVE_ARCH_FB_UNMAPPED_AREA 770 771extern void pgtable_cache_init(void); 772extern void sun4v_register_fault_status(void); 773extern void sun4v_ktsb_register(void); 774 775extern unsigned long cmdline_memory_size; 776 777#endif /* !(__ASSEMBLY__) */ 778 779#endif /* !(_SPARC64_PGTABLE_H) */ 780