1/* $Id: pcic.h,v 1.1.1.1 2007/08/03 18:53:36 Exp $ 2 * pcic.h: JavaEngine 1 specific PCI definitions. 3 * 4 * Copyright (C) 1998 V. Roganov and G. Raiko 5 */ 6 7#ifndef __SPARC_PCIC_H 8#define __SPARC_PCIC_H 9 10#ifndef __ASSEMBLY__ 11 12#include <linux/types.h> 13#include <linux/smp.h> 14#include <linux/pci.h> 15#include <linux/ioport.h> 16#include <asm/pbm.h> 17 18struct linux_pcic { 19 void __iomem *pcic_regs; 20 unsigned long pcic_io; 21 void __iomem *pcic_config_space_addr; 22 void __iomem *pcic_config_space_data; 23 struct resource pcic_res_regs; 24 struct resource pcic_res_io; 25 struct resource pcic_res_cfg_addr; 26 struct resource pcic_res_cfg_data; 27 struct linux_pbm_info pbm; 28 struct pcic_ca2irq *pcic_imap; 29 int pcic_imdim; 30}; 31 32extern int pcic_probe(void); 33/* Erm... MJ redefined pcibios_present() so that it does not work early. */ 34extern int pcic_present(void); 35extern void sun4m_pci_init_IRQ(void); 36 37#endif 38 39/* Size of PCI I/O space which we relocate. */ 40#define PCI_SPACE_SIZE 0x1000000 /* 16 MB */ 41 42/* PCIC Register Set. */ 43#define PCI_DIAGNOSTIC_0 0x40 /* 32 bits */ 44#define PCI_SIZE_0 0x44 /* 32 bits */ 45#define PCI_SIZE_1 0x48 /* 32 bits */ 46#define PCI_SIZE_2 0x4c /* 32 bits */ 47#define PCI_SIZE_3 0x50 /* 32 bits */ 48#define PCI_SIZE_4 0x54 /* 32 bits */ 49#define PCI_SIZE_5 0x58 /* 32 bits */ 50#define PCI_PIO_CONTROL 0x60 /* 8 bits */ 51#define PCI_DVMA_CONTROL 0x62 /* 8 bits */ 52#define PCI_DVMA_CONTROL_INACTIVITY_REQ (1<<0) 53#define PCI_DVMA_CONTROL_IOTLB_ENABLE (1<<0) 54#define PCI_DVMA_CONTROL_IOTLB_DISABLE 0 55#define PCI_DVMA_CONTROL_INACTIVITY_ACK (1<<4) 56#define PCI_INTERRUPT_CONTROL 0x63 /* 8 bits */ 57#define PCI_CPU_INTERRUPT_PENDING 0x64 /* 32 bits */ 58#define PCI_DIAGNOSTIC_1 0x68 /* 16 bits */ 59#define PCI_SOFTWARE_INT_CLEAR 0x6a /* 16 bits */ 60#define PCI_SOFTWARE_INT_SET 0x6e /* 16 bits */ 61#define PCI_SYS_INT_PENDING 0x70 /* 32 bits */ 62#define PCI_SYS_INT_PENDING_PIO 0x40000000 63#define PCI_SYS_INT_PENDING_DMA 0x20000000 64#define PCI_SYS_INT_PENDING_PCI 0x10000000 65#define PCI_SYS_INT_PENDING_APSR 0x08000000 66#define PCI_SYS_INT_TARGET_MASK 0x74 /* 32 bits */ 67#define PCI_SYS_INT_TARGET_MASK_CLEAR 0x78 /* 32 bits */ 68#define PCI_SYS_INT_TARGET_MASK_SET 0x7c /* 32 bits */ 69#define PCI_SYS_INT_PENDING_CLEAR 0x83 /* 8 bits */ 70#define PCI_SYS_INT_PENDING_CLEAR_ALL 0x80 71#define PCI_SYS_INT_PENDING_CLEAR_PIO 0x40 72#define PCI_SYS_INT_PENDING_CLEAR_DMA 0x20 73#define PCI_SYS_INT_PENDING_CLEAR_PCI 0x10 74#define PCI_IOTLB_CONTROL 0x84 /* 8 bits */ 75#define PCI_INT_SELECT_LO 0x88 /* 16 bits */ 76#define PCI_ARBITRATION_SELECT 0x8a /* 16 bits */ 77#define PCI_INT_SELECT_HI 0x8c /* 16 bits */ 78#define PCI_HW_INT_OUTPUT 0x8e /* 16 bits */ 79#define PCI_IOTLB_RAM_INPUT 0x90 /* 32 bits */ 80#define PCI_IOTLB_CAM_INPUT 0x94 /* 32 bits */ 81#define PCI_IOTLB_RAM_OUTPUT 0x98 /* 32 bits */ 82#define PCI_IOTLB_CAM_OUTPUT 0x9c /* 32 bits */ 83#define PCI_SMBAR0 0xa0 /* 8 bits */ 84#define PCI_MSIZE0 0xa1 /* 8 bits */ 85#define PCI_PMBAR0 0xa2 /* 8 bits */ 86#define PCI_SMBAR1 0xa4 /* 8 bits */ 87#define PCI_MSIZE1 0xa5 /* 8 bits */ 88#define PCI_PMBAR1 0xa6 /* 8 bits */ 89#define PCI_SIBAR 0xa8 /* 8 bits */ 90#define PCI_SIBAR_ADDRESS_MASK 0xf 91#define PCI_ISIZE 0xa9 /* 8 bits */ 92#define PCI_ISIZE_16M 0xf 93#define PCI_ISIZE_32M 0xe 94#define PCI_ISIZE_64M 0xc 95#define PCI_ISIZE_128M 0x8 96#define PCI_ISIZE_256M 0x0 97#define PCI_PIBAR 0xaa /* 8 bits */ 98#define PCI_CPU_COUNTER_LIMIT_HI 0xac /* 32 bits */ 99#define PCI_CPU_COUNTER_LIMIT_LO 0xb0 /* 32 bits */ 100#define PCI_CPU_COUNTER_LIMIT 0xb4 /* 32 bits */ 101#define PCI_SYS_LIMIT 0xb8 /* 32 bits */ 102#define PCI_SYS_COUNTER 0xbc /* 32 bits */ 103#define PCI_SYS_COUNTER_OVERFLOW (1<<31) /* Limit reached */ 104#define PCI_SYS_LIMIT_PSEUDO 0xc0 /* 32 bits */ 105#define PCI_USER_TIMER_CONTROL 0xc4 /* 8 bits */ 106#define PCI_USER_TIMER_CONFIG 0xc5 /* 8 bits */ 107#define PCI_COUNTER_IRQ 0xc6 /* 8 bits */ 108#define PCI_COUNTER_IRQ_SET(sys_irq, cpu_irq) ((((sys_irq) & 0xf) << 4) | \ 109 ((cpu_irq) & 0xf)) 110#define PCI_COUNTER_IRQ_SYS(v) (((v) >> 4) & 0xf) 111#define PCI_COUNTER_IRQ_CPU(v) ((v) & 0xf) 112#define PCI_PIO_ERROR_COMMAND 0xc7 /* 8 bits */ 113#define PCI_PIO_ERROR_ADDRESS 0xc8 /* 32 bits */ 114#define PCI_IOTLB_ERROR_ADDRESS 0xcc /* 32 bits */ 115#define PCI_SYS_STATUS 0xd0 /* 8 bits */ 116#define PCI_SYS_STATUS_RESET_ENABLE (1<<0) 117#define PCI_SYS_STATUS_RESET (1<<1) 118#define PCI_SYS_STATUS_WATCHDOG_RESET (1<<4) 119#define PCI_SYS_STATUS_PCI_RESET (1<<5) 120#define PCI_SYS_STATUS_PCI_RESET_ENABLE (1<<6) 121#define PCI_SYS_STATUS_PCI_SATTELITE_MODE (1<<7) 122 123#endif /* !(__SPARC_PCIC_H) */ 124