1/* 2 * Copyright (C) 1999 Niibe Yutaka 3 * Copyright (C) 2003 - 2006 Paul Mundt 4 * 5 * ASID handling idea taken from MIPS implementation. 6 */ 7#ifndef __ASM_SH_MMU_CONTEXT_H 8#define __ASM_SH_MMU_CONTEXT_H 9#ifdef __KERNEL__ 10 11#include <asm/cpu/mmu_context.h> 12#include <asm/tlbflush.h> 13#include <asm/uaccess.h> 14#include <asm/io.h> 15#include <asm-generic/mm_hooks.h> 16 17/* 18 * The MMU "context" consists of two things: 19 * (a) TLB cache version (or round, cycle whatever expression you like) 20 * (b) ASID (Address Space IDentifier) 21 */ 22 23#define MMU_CONTEXT_ASID_MASK 0x000000ff 24#define MMU_CONTEXT_VERSION_MASK 0xffffff00 25#define MMU_CONTEXT_FIRST_VERSION 0x00000100 26#define NO_CONTEXT 0 27 28/* ASID is 8-bit value, so it can't be 0x100 */ 29#define MMU_NO_ASID 0x100 30 31#define cpu_context(cpu, mm) ((mm)->context.id[cpu]) 32#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & \ 33 MMU_CONTEXT_ASID_MASK) 34#define asid_cache(cpu) (cpu_data[cpu].asid_cache) 35 36/* 37 * Virtual Page Number mask 38 */ 39#define MMU_VPN_MASK 0xfffff000 40 41#ifdef CONFIG_MMU 42/* 43 * Get MMU context if needed. 44 */ 45static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu) 46{ 47 unsigned long asid = asid_cache(cpu); 48 49 /* Check if we have old version of context. */ 50 if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0) 51 /* It's up to date, do nothing */ 52 return; 53 54 /* It's old, we need to get new context with new version. */ 55 if (!(++asid & MMU_CONTEXT_ASID_MASK)) { 56 /* 57 * We exhaust ASID of this version. 58 * Flush all TLB and start new cycle. 59 */ 60 flush_tlb_all(); 61 62 /* 63 * Fix version; Note that we avoid version #0 64 * to distingush NO_CONTEXT. 65 */ 66 if (!asid) 67 asid = MMU_CONTEXT_FIRST_VERSION; 68 } 69 70 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 71} 72 73/* 74 * Initialize the context related info for a new mm_struct 75 * instance. 76 */ 77static inline int init_new_context(struct task_struct *tsk, 78 struct mm_struct *mm) 79{ 80 int i; 81 82 for (i = 0; i < num_online_cpus(); i++) 83 cpu_context(i, mm) = NO_CONTEXT; 84 85 return 0; 86} 87 88/* 89 * Destroy context related info for an mm_struct that is about 90 * to be put to rest. 91 */ 92static inline void destroy_context(struct mm_struct *mm) 93{ 94 /* Do nothing */ 95} 96 97static inline void set_asid(unsigned long asid) 98{ 99 unsigned long __dummy; 100 101 __asm__ __volatile__ ("mov.l %2, %0\n\t" 102 "and %3, %0\n\t" 103 "or %1, %0\n\t" 104 "mov.l %0, %2" 105 : "=&r" (__dummy) 106 : "r" (asid), "m" (__m(MMU_PTEH)), 107 "r" (0xffffff00)); 108} 109 110static inline unsigned long get_asid(void) 111{ 112 unsigned long asid; 113 114 __asm__ __volatile__ ("mov.l %1, %0" 115 : "=r" (asid) 116 : "m" (__m(MMU_PTEH))); 117 asid &= MMU_CONTEXT_ASID_MASK; 118 return asid; 119} 120 121/* 122 * After we have set current->mm to a new value, this activates 123 * the context for the new mm so we see the new mappings. 124 */ 125static inline void activate_context(struct mm_struct *mm, unsigned int cpu) 126{ 127 get_mmu_context(mm, cpu); 128 set_asid(cpu_asid(cpu, mm)); 129} 130 131/* MMU_TTB is used for optimizing the fault handling. */ 132static inline void set_TTB(pgd_t *pgd) 133{ 134 ctrl_outl((unsigned long)pgd, MMU_TTB); 135} 136 137static inline pgd_t *get_TTB(void) 138{ 139 return (pgd_t *)ctrl_inl(MMU_TTB); 140} 141 142static inline void switch_mm(struct mm_struct *prev, 143 struct mm_struct *next, 144 struct task_struct *tsk) 145{ 146 unsigned int cpu = smp_processor_id(); 147 148 if (likely(prev != next)) { 149 cpu_set(cpu, next->cpu_vm_mask); 150 set_TTB(next->pgd); 151 activate_context(next, cpu); 152 } else 153 if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) 154 activate_context(next, cpu); 155} 156 157#define deactivate_mm(tsk,mm) do { } while (0) 158 159#define activate_mm(prev, next) \ 160 switch_mm((prev),(next),NULL) 161 162static inline void 163enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 164{ 165} 166#else /* !CONFIG_MMU */ 167#define get_mmu_context(mm) do { } while (0) 168#define init_new_context(tsk,mm) (0) 169#define destroy_context(mm) do { } while (0) 170#define set_asid(asid) do { } while (0) 171#define get_asid() (0) 172#define set_TTB(pgd) do { } while (0) 173#define get_TTB() (0) 174#define activate_context(mm,cpu) do { } while (0) 175#define switch_mm(prev,next,tsk) do { } while (0) 176#define deactivate_mm(tsk,mm) do { } while (0) 177#define activate_mm(prev,next) do { } while (0) 178#define enter_lazy_tlb(mm,tsk) do { } while (0) 179#endif /* CONFIG_MMU */ 180 181#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4) 182/* 183 * If this processor has an MMU, we need methods to turn it off/on .. 184 * paging_init() will also have to be updated for the processor in 185 * question. 186 */ 187static inline void enable_mmu(void) 188{ 189 unsigned int cpu = smp_processor_id(); 190 191 /* Enable MMU */ 192 ctrl_outl(MMU_CONTROL_INIT, MMUCR); 193 ctrl_barrier(); 194 195 if (asid_cache(cpu) == NO_CONTEXT) 196 asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION; 197 198 set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK); 199} 200 201static inline void disable_mmu(void) 202{ 203 unsigned long cr; 204 205 cr = ctrl_inl(MMUCR); 206 cr &= ~MMU_CONTROL_INIT; 207 ctrl_outl(cr, MMUCR); 208 209 ctrl_barrier(); 210} 211#else 212/* 213 * MMU control handlers for processors lacking memory 214 * management hardware. 215 */ 216#define enable_mmu() do { } while (0) 217#define disable_mmu() do { } while (0) 218#endif 219 220#endif /* __KERNEL__ */ 221#endif /* __ASM_SH_MMU_CONTEXT_H */ 222