1/*
2 * include/asm-ppc/mpc52xx.h
3 *
4 * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
5 * May need to be cleaned as the port goes on ...
6 *
7 *
8 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
9 *
10 * Originally written by Dale Farnsworth <dfarnsworth@mvista.com>
11 * for the 2.4 kernel.
12 *
13 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
14 * Copyright (C) 2003 MontaVista, Software, Inc.
15 *
16 * This file is licensed under the terms of the GNU General Public License
17 * version 2. This program is licensed "as is" without any warranty of any
18 * kind, whether express or implied.
19 */
20
21#ifndef __ASM_MPC52xx_H__
22#define __ASM_MPC52xx_H__
23
24#ifndef __ASSEMBLY__
25#include <asm/ppcboot.h>
26#include <asm/types.h>
27
28struct pt_regs;
29#endif /* __ASSEMBLY__ */
30
31
32/* ======================================================================== */
33/* PPC Sys devices definition                                               */
34/* ======================================================================== */
35
36enum ppc_sys_devices {
37	MPC52xx_MSCAN1,
38	MPC52xx_MSCAN2,
39	MPC52xx_SPI,
40	MPC52xx_USB,
41	MPC52xx_BDLC,
42	MPC52xx_PSC1,
43	MPC52xx_PSC2,
44	MPC52xx_PSC3,
45	MPC52xx_PSC4,
46	MPC52xx_PSC5,
47	MPC52xx_PSC6,
48	MPC52xx_FEC,
49	MPC52xx_ATA,
50	MPC52xx_I2C1,
51	MPC52xx_I2C2,
52	NUM_PPC_SYS_DEVS,
53};
54
55
56/* ======================================================================== */
57/* Main registers/struct addresses                                          */
58/* ======================================================================== */
59
60/* MBAR position */
61#define MPC52xx_MBAR		0xf0000000	/* Phys address */
62#define MPC52xx_MBAR_VIRT	0xf0000000	/* Virt address */
63#define MPC52xx_MBAR_SIZE	0x00010000
64
65#define MPC52xx_PA(x)		((phys_addr_t)(MPC52xx_MBAR + (x)))
66#define MPC52xx_VA(x)		((void __iomem *)(MPC52xx_MBAR_VIRT + (x)))
67
68/* Registers zone offset/size  */
69#define MPC52xx_MMAP_CTL_OFFSET		0x0000
70#define MPC52xx_MMAP_CTL_SIZE		0x068
71#define MPC52xx_SDRAM_OFFSET		0x0100
72#define MPC52xx_SDRAM_SIZE		0x010
73#define MPC52xx_CDM_OFFSET		0x0200
74#define MPC52xx_CDM_SIZE		0x038
75#define MPC52xx_INTR_OFFSET		0x0500
76#define MPC52xx_INTR_SIZE		0x04c
77#define MPC52xx_GPTx_OFFSET(x)		(0x0600 + ((x)<<4))
78#define MPC52xx_GPT_SIZE		0x010
79#define MPC52xx_RTC_OFFSET		0x0800
80#define MPC52xx_RTC_SIZE		0x024
81#define MPC52xx_GPIO_OFFSET		0x0b00
82#define MPC52xx_GPIO_SIZE		0x040
83#define MPC52xx_GPIO_WKUP_OFFSET	0x0c00
84#define MPC52xx_GPIO_WKUP_SIZE		0x028
85#define MPC52xx_PCI_OFFSET		0x0d00
86#define MPC52xx_PCI_SIZE		0x100
87#define MPC52xx_SDMA_OFFSET		0x1200
88#define MPC52xx_SDMA_SIZE		0x100
89#define MPC52xx_XLB_OFFSET		0x1f00
90#define MPC52xx_XLB_SIZE		0x100
91#define MPC52xx_PSCx_OFFSET(x)		(((x)!=6)?(0x1e00+((x)<<9)):0x2c00)
92#define MPC52xx_PSC_SIZE		0x0a0
93
94/* SRAM used for SDMA */
95#define MPC52xx_SRAM_OFFSET		0x8000
96#define MPC52xx_SRAM_SIZE		0x4000
97
98
99/* ======================================================================== */
100/* IRQ mapping                                                              */
101/* ======================================================================== */
102/* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change
103 * this
104 */
105
106#define MPC52xx_CRIT_IRQ_NUM	4
107#define MPC52xx_MAIN_IRQ_NUM	17
108#define MPC52xx_SDMA_IRQ_NUM	17
109#define MPC52xx_PERP_IRQ_NUM	23
110
111#define MPC52xx_CRIT_IRQ_BASE	1
112#define MPC52xx_MAIN_IRQ_BASE	(MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM)
113#define MPC52xx_SDMA_IRQ_BASE	(MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM)
114#define MPC52xx_PERP_IRQ_BASE	(MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)
115
116#define MPC52xx_IRQ0			(MPC52xx_CRIT_IRQ_BASE + 0)
117#define MPC52xx_SLICE_TIMER_0_IRQ	(MPC52xx_CRIT_IRQ_BASE + 1)
118#define MPC52xx_HI_INT_IRQ		(MPC52xx_CRIT_IRQ_BASE + 2)
119#define MPC52xx_CCS_IRQ			(MPC52xx_CRIT_IRQ_BASE + 3)
120
121#define MPC52xx_IRQ1			(MPC52xx_MAIN_IRQ_BASE + 1)
122#define MPC52xx_IRQ2			(MPC52xx_MAIN_IRQ_BASE + 2)
123#define MPC52xx_IRQ3			(MPC52xx_MAIN_IRQ_BASE + 3)
124
125#define MPC52xx_SDMA_IRQ		(MPC52xx_PERP_IRQ_BASE + 0)
126#define MPC52xx_PSC1_IRQ		(MPC52xx_PERP_IRQ_BASE + 1)
127#define MPC52xx_PSC2_IRQ		(MPC52xx_PERP_IRQ_BASE + 2)
128#define MPC52xx_PSC3_IRQ		(MPC52xx_PERP_IRQ_BASE + 3)
129#define MPC52xx_PSC6_IRQ		(MPC52xx_PERP_IRQ_BASE + 4)
130#define MPC52xx_IRDA_IRQ		(MPC52xx_PERP_IRQ_BASE + 4)
131#define MPC52xx_FEC_IRQ			(MPC52xx_PERP_IRQ_BASE + 5)
132#define MPC52xx_USB_IRQ			(MPC52xx_PERP_IRQ_BASE + 6)
133#define MPC52xx_ATA_IRQ			(MPC52xx_PERP_IRQ_BASE + 7)
134#define MPC52xx_PCI_CNTRL_IRQ		(MPC52xx_PERP_IRQ_BASE + 8)
135#define MPC52xx_PCI_SCIRX_IRQ		(MPC52xx_PERP_IRQ_BASE + 9)
136#define MPC52xx_PCI_SCITX_IRQ		(MPC52xx_PERP_IRQ_BASE + 10)
137#define MPC52xx_PSC4_IRQ		(MPC52xx_PERP_IRQ_BASE + 11)
138#define MPC52xx_PSC5_IRQ		(MPC52xx_PERP_IRQ_BASE + 12)
139#define MPC52xx_SPI_MODF_IRQ		(MPC52xx_PERP_IRQ_BASE + 13)
140#define MPC52xx_SPI_SPIF_IRQ		(MPC52xx_PERP_IRQ_BASE + 14)
141#define MPC52xx_I2C1_IRQ		(MPC52xx_PERP_IRQ_BASE + 15)
142#define MPC52xx_I2C2_IRQ		(MPC52xx_PERP_IRQ_BASE + 16)
143#define MPC52xx_MSCAN1_IRQ		(MPC52xx_PERP_IRQ_BASE + 17)
144#define MPC52xx_MSCAN2_IRQ		(MPC52xx_PERP_IRQ_BASE + 18)
145#define MPC52xx_IR_RX_IRQ		(MPC52xx_PERP_IRQ_BASE + 19)
146#define MPC52xx_IR_TX_IRQ		(MPC52xx_PERP_IRQ_BASE + 20)
147#define MPC52xx_XLB_ARB_IRQ		(MPC52xx_PERP_IRQ_BASE + 21)
148#define MPC52xx_BDLC_IRQ		(MPC52xx_PERP_IRQ_BASE + 22)
149
150
151
152/* ======================================================================== */
153/* Structures mapping of some unit register set                             */
154/* ======================================================================== */
155
156#ifndef __ASSEMBLY__
157
158/* Memory Mapping Control */
159struct mpc52xx_mmap_ctl {
160	u32	mbar;		/* MMAP_CTRL + 0x00 */
161
162	u32	cs0_start;	/* MMAP_CTRL + 0x04 */
163	u32	cs0_stop;	/* MMAP_CTRL + 0x08 */
164	u32	cs1_start;	/* MMAP_CTRL + 0x0c */
165	u32	cs1_stop;	/* MMAP_CTRL + 0x10 */
166	u32	cs2_start;	/* MMAP_CTRL + 0x14 */
167	u32	cs2_stop;	/* MMAP_CTRL + 0x18 */
168	u32	cs3_start;	/* MMAP_CTRL + 0x1c */
169	u32	cs3_stop;	/* MMAP_CTRL + 0x20 */
170	u32	cs4_start;	/* MMAP_CTRL + 0x24 */
171	u32	cs4_stop;	/* MMAP_CTRL + 0x28 */
172	u32	cs5_start;	/* MMAP_CTRL + 0x2c */
173	u32	cs5_stop;	/* MMAP_CTRL + 0x30 */
174
175	u32	sdram0;		/* MMAP_CTRL + 0x34 */
176	u32	sdram1;		/* MMAP_CTRL + 0X38 */
177
178	u32	reserved[4];	/* MMAP_CTRL + 0x3c .. 0x48 */
179
180	u32	boot_start;	/* MMAP_CTRL + 0x4c */
181	u32	boot_stop;	/* MMAP_CTRL + 0x50 */
182
183	u32	ipbi_ws_ctrl;	/* MMAP_CTRL + 0x54 */
184
185	u32	cs6_start;	/* MMAP_CTRL + 0x58 */
186	u32	cs6_stop;	/* MMAP_CTRL + 0x5c */
187	u32	cs7_start;	/* MMAP_CTRL + 0x60 */
188	u32	cs7_stop;	/* MMAP_CTRL + 0x64 */
189};
190
191/* SDRAM control */
192struct mpc52xx_sdram {
193	u32	mode;		/* SDRAM + 0x00 */
194	u32	ctrl;		/* SDRAM + 0x04 */
195	u32	config1;	/* SDRAM + 0x08 */
196	u32	config2;	/* SDRAM + 0x0c */
197};
198
199/* Interrupt controller */
200struct mpc52xx_intr {
201	u32	per_mask;	/* INTR + 0x00 */
202	u32	per_pri1;	/* INTR + 0x04 */
203	u32	per_pri2;	/* INTR + 0x08 */
204	u32	per_pri3;	/* INTR + 0x0c */
205	u32	ctrl;		/* INTR + 0x10 */
206	u32	main_mask;	/* INTR + 0x14 */
207	u32	main_pri1;	/* INTR + 0x18 */
208	u32	main_pri2;	/* INTR + 0x1c */
209	u32	reserved1;	/* INTR + 0x20 */
210	u32	enc_status;	/* INTR + 0x24 */
211	u32	crit_status;	/* INTR + 0x28 */
212	u32	main_status;	/* INTR + 0x2c */
213	u32	per_status;	/* INTR + 0x30 */
214	u32	reserved2;	/* INTR + 0x34 */
215	u32	per_error;	/* INTR + 0x38 */
216};
217
218/* SDMA */
219struct mpc52xx_sdma {
220	u32	taskBar;	/* SDMA + 0x00 */
221	u32	currentPointer;	/* SDMA + 0x04 */
222	u32	endPointer;	/* SDMA + 0x08 */
223	u32	variablePointer;/* SDMA + 0x0c */
224
225	u8	IntVect1;	/* SDMA + 0x10 */
226	u8	IntVect2;	/* SDMA + 0x11 */
227	u16	PtdCntrl;	/* SDMA + 0x12 */
228
229	u32	IntPend;	/* SDMA + 0x14 */
230	u32	IntMask;	/* SDMA + 0x18 */
231
232	u16	tcr[16];	/* SDMA + 0x1c .. 0x3a */
233
234	u8	ipr[32];	/* SDMA + 0x3c .. 0x5b */
235
236	u32	cReqSelect;	/* SDMA + 0x5c */
237	u32	task_size0;	/* SDMA + 0x60 */
238	u32	task_size1;	/* SDMA + 0x64 */
239	u32	MDEDebug;	/* SDMA + 0x68 */
240	u32	ADSDebug;	/* SDMA + 0x6c */
241	u32	Value1;		/* SDMA + 0x70 */
242	u32	Value2;		/* SDMA + 0x74 */
243	u32	Control;	/* SDMA + 0x78 */
244	u32	Status;		/* SDMA + 0x7c */
245	u32	PTDDebug;	/* SDMA + 0x80 */
246};
247
248/* GPT */
249struct mpc52xx_gpt {
250	u32	mode;		/* GPTx + 0x00 */
251	u32	count;		/* GPTx + 0x04 */
252	u32	pwm;		/* GPTx + 0x08 */
253	u32	status;		/* GPTx + 0X0c */
254};
255
256/* RTC */
257struct mpc52xx_rtc {
258	u32	time_set;	/* RTC + 0x00 */
259	u32	date_set;	/* RTC + 0x04 */
260	u32	stopwatch;	/* RTC + 0x08 */
261	u32	int_enable;	/* RTC + 0x0c */
262	u32	time;		/* RTC + 0x10 */
263	u32	date;		/* RTC + 0x14 */
264	u32	stopwatch_intr;	/* RTC + 0x18 */
265	u32	bus_error;	/* RTC + 0x1c */
266	u32	dividers;	/* RTC + 0x20 */
267};
268
269/* GPIO */
270struct mpc52xx_gpio {
271	u32	port_config;	/* GPIO + 0x00 */
272	u32	simple_gpioe;	/* GPIO + 0x04 */
273	u32	simple_ode;	/* GPIO + 0x08 */
274	u32	simple_ddr;	/* GPIO + 0x0c */
275	u32	simple_dvo;	/* GPIO + 0x10 */
276	u32	simple_ival;	/* GPIO + 0x14 */
277	u8	outo_gpioe;	/* GPIO + 0x18 */
278	u8	reserved1[3];	/* GPIO + 0x19 */
279	u8	outo_dvo;	/* GPIO + 0x1c */
280	u8	reserved2[3];	/* GPIO + 0x1d */
281	u8	sint_gpioe;	/* GPIO + 0x20 */
282	u8	reserved3[3];	/* GPIO + 0x21 */
283	u8	sint_ode;	/* GPIO + 0x24 */
284	u8	reserved4[3];	/* GPIO + 0x25 */
285	u8	sint_ddr;	/* GPIO + 0x28 */
286	u8	reserved5[3];	/* GPIO + 0x29 */
287	u8	sint_dvo;	/* GPIO + 0x2c */
288	u8	reserved6[3];	/* GPIO + 0x2d */
289	u8	sint_inten;	/* GPIO + 0x30 */
290	u8	reserved7[3];	/* GPIO + 0x31 */
291	u16	sint_itype;	/* GPIO + 0x34 */
292	u16	reserved8;	/* GPIO + 0x36 */
293	u8	gpio_control;	/* GPIO + 0x38 */
294	u8	reserved9[3];	/* GPIO + 0x39 */
295	u8	sint_istat;	/* GPIO + 0x3c */
296	u8	sint_ival;	/* GPIO + 0x3d */
297	u8	bus_errs;	/* GPIO + 0x3e */
298	u8	reserved10;	/* GPIO + 0x3f */
299};
300
301#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD	4
302#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD	5
303#define MPC52xx_GPIO_PCI_DIS			(1<<15)
304
305/* GPIO with WakeUp*/
306struct mpc52xx_gpio_wkup {
307	u8	wkup_gpioe;	/* GPIO_WKUP + 0x00 */
308	u8	reserved1[3];	/* GPIO_WKUP + 0x03 */
309	u8	wkup_ode;	/* GPIO_WKUP + 0x04 */
310	u8	reserved2[3];	/* GPIO_WKUP + 0x05 */
311	u8	wkup_ddr;	/* GPIO_WKUP + 0x08 */
312	u8	reserved3[3];	/* GPIO_WKUP + 0x09 */
313	u8	wkup_dvo;	/* GPIO_WKUP + 0x0C */
314	u8	reserved4[3];	/* GPIO_WKUP + 0x0D */
315	u8	wkup_inten;	/* GPIO_WKUP + 0x10 */
316	u8	reserved5[3];	/* GPIO_WKUP + 0x11 */
317	u8	wkup_iinten;	/* GPIO_WKUP + 0x14 */
318	u8	reserved6[3];	/* GPIO_WKUP + 0x15 */
319	u16	wkup_itype;	/* GPIO_WKUP + 0x18 */
320	u8	reserved7[2];	/* GPIO_WKUP + 0x1A */
321	u8	wkup_maste;	/* GPIO_WKUP + 0x1C */
322	u8	reserved8[3];	/* GPIO_WKUP + 0x1D */
323	u8	wkup_ival;	/* GPIO_WKUP + 0x20 */
324	u8	reserved9[3];	/* GPIO_WKUP + 0x21 */
325	u8	wkup_istat;	/* GPIO_WKUP + 0x24 */
326	u8	reserved10[3];	/* GPIO_WKUP + 0x25 */
327};
328
329/* XLB Bus control */
330struct mpc52xx_xlb {
331	u8	reserved[0x40];
332	u32	config;			/* XLB + 0x40 */
333	u32	version;		/* XLB + 0x44 */
334	u32	status;			/* XLB + 0x48 */
335	u32	int_enable;		/* XLB + 0x4c */
336	u32	addr_capture;		/* XLB + 0x50 */
337	u32	bus_sig_capture;	/* XLB + 0x54 */
338	u32	addr_timeout;		/* XLB + 0x58 */
339	u32	data_timeout;		/* XLB + 0x5c */
340	u32	bus_act_timeout;	/* XLB + 0x60 */
341	u32	master_pri_enable;	/* XLB + 0x64 */
342	u32	master_priority;	/* XLB + 0x68 */
343	u32	base_address;		/* XLB + 0x6c */
344	u32	snoop_window;		/* XLB + 0x70 */
345};
346
347#define MPC52xx_XLB_CFG_PLDIS		(1 << 31)
348#define MPC52xx_XLB_CFG_SNOOP		(1 << 15)
349
350/* Clock Distribution control */
351struct mpc52xx_cdm {
352	u32	jtag_id;		/* CDM + 0x00  reg0 read only */
353	u32	rstcfg;			/* CDM + 0x04  reg1 read only */
354	u32	breadcrumb;		/* CDM + 0x08  reg2 */
355
356	u8	mem_clk_sel;		/* CDM + 0x0c  reg3 byte0 */
357	u8	xlb_clk_sel;		/* CDM + 0x0d  reg3 byte1 read only */
358	u8	ipb_clk_sel;		/* CDM + 0x0e  reg3 byte2 */
359	u8	pci_clk_sel;		/* CDM + 0x0f  reg3 byte3 */
360
361	u8	ext_48mhz_en;		/* CDM + 0x10  reg4 byte0 */
362	u8	fd_enable;		/* CDM + 0x11  reg4 byte1 */
363	u16	fd_counters;		/* CDM + 0x12  reg4 byte2,3 */
364
365	u32	clk_enables;		/* CDM + 0x14  reg5 */
366
367	u8	osc_disable;		/* CDM + 0x18  reg6 byte0 */
368	u8	reserved0[3];		/* CDM + 0x19  reg6 byte1,2,3 */
369
370	u8	ccs_sleep_enable;	/* CDM + 0x1c  reg7 byte0 */
371	u8	osc_sleep_enable;	/* CDM + 0x1d  reg7 byte1 */
372	u8	reserved1;		/* CDM + 0x1e  reg7 byte2 */
373	u8	ccs_qreq_test;		/* CDM + 0x1f  reg7 byte3 */
374
375	u8	soft_reset;		/* CDM + 0x20  u8 byte0 */
376	u8	no_ckstp;		/* CDM + 0x21  u8 byte0 */
377	u8	reserved2[2];		/* CDM + 0x22  u8 byte1,2,3 */
378
379	u8	pll_lock;		/* CDM + 0x24  reg9 byte0 */
380	u8	pll_looselock;		/* CDM + 0x25  reg9 byte1 */
381	u8	pll_sm_lockwin;		/* CDM + 0x26  reg9 byte2 */
382	u8	reserved3;		/* CDM + 0x27  reg9 byte3 */
383
384	u16	reserved4;		/* CDM + 0x28  reg10 byte0,1 */
385	u16	mclken_div_psc1;	/* CDM + 0x2a  reg10 byte2,3 */
386
387	u16	reserved5;		/* CDM + 0x2c  reg11 byte0,1 */
388	u16	mclken_div_psc2;	/* CDM + 0x2e  reg11 byte2,3 */
389
390	u16	reserved6;		/* CDM + 0x30  reg12 byte0,1 */
391	u16	mclken_div_psc3;	/* CDM + 0x32  reg12 byte2,3 */
392
393	u16	reserved7;		/* CDM + 0x34  reg13 byte0,1 */
394	u16	mclken_div_psc6;	/* CDM + 0x36  reg13 byte2,3 */
395};
396
397#endif /* __ASSEMBLY__ */
398
399
400/* ========================================================================= */
401/* Prototypes for MPC52xx syslib                                             */
402/* ========================================================================= */
403
404#ifndef __ASSEMBLY__
405
406extern void mpc52xx_init_irq(void);
407extern int mpc52xx_get_irq(void);
408
409extern unsigned long mpc52xx_find_end_of_memory(void);
410extern void mpc52xx_set_bat(void);
411extern void mpc52xx_map_io(void);
412extern void mpc52xx_restart(char *cmd);
413extern void mpc52xx_halt(void);
414extern void mpc52xx_power_off(void);
415extern void mpc52xx_progress(char *s, unsigned short hex);
416extern void mpc52xx_calibrate_decr(void);
417
418extern void mpc52xx_find_bridges(void);
419
420extern void mpc52xx_setup_cpu(void);
421
422
423
424	/* Matching of PSC function */
425struct mpc52xx_psc_func {
426	int id;
427	char *func;
428};
429
430extern int mpc52xx_match_psc_function(int psc_idx, const char *func);
431extern struct  mpc52xx_psc_func mpc52xx_psc_functions[];
432	/* This array is to be defined in platform file */
433
434#endif /* __ASSEMBLY__ */
435
436
437/* ========================================================================= */
438/* Platform configuration                                                    */
439/* ========================================================================= */
440
441/* The U-Boot platform information struct */
442extern bd_t __res;
443
444/* Platform options */
445#if defined(CONFIG_LITE5200)
446#include <platforms/lite5200.h>
447#endif
448
449
450#endif /* __ASM_MPC52xx_H__ */
451