1/* 2 * Communication Processor Module v2. 3 * 4 * This file contains structures and information for the communication 5 * processor channels found in the dual port RAM or parameter RAM. 6 * All CPM control and status is available through the CPM2 internal 7 * memory map. See immap_cpm2.h for details. 8 */ 9#ifdef __KERNEL__ 10#ifndef __CPM2__ 11#define __CPM2__ 12 13#include <asm/immap_cpm2.h> 14 15/* CPM Command register. 16*/ 17#define CPM_CR_RST ((uint)0x80000000) 18#define CPM_CR_PAGE ((uint)0x7c000000) 19#define CPM_CR_SBLOCK ((uint)0x03e00000) 20#define CPM_CR_FLG ((uint)0x00010000) 21#define CPM_CR_MCN ((uint)0x00003fc0) 22#define CPM_CR_OPCODE ((uint)0x0000000f) 23 24/* Device sub-block and page codes. 25*/ 26#define CPM_CR_SCC1_SBLOCK (0x04) 27#define CPM_CR_SCC2_SBLOCK (0x05) 28#define CPM_CR_SCC3_SBLOCK (0x06) 29#define CPM_CR_SCC4_SBLOCK (0x07) 30#define CPM_CR_SMC1_SBLOCK (0x08) 31#define CPM_CR_SMC2_SBLOCK (0x09) 32#define CPM_CR_SPI_SBLOCK (0x0a) 33#define CPM_CR_I2C_SBLOCK (0x0b) 34#define CPM_CR_TIMER_SBLOCK (0x0f) 35#define CPM_CR_RAND_SBLOCK (0x0e) 36#define CPM_CR_FCC1_SBLOCK (0x10) 37#define CPM_CR_FCC2_SBLOCK (0x11) 38#define CPM_CR_FCC3_SBLOCK (0x12) 39#define CPM_CR_IDMA1_SBLOCK (0x14) 40#define CPM_CR_IDMA2_SBLOCK (0x15) 41#define CPM_CR_IDMA3_SBLOCK (0x16) 42#define CPM_CR_IDMA4_SBLOCK (0x17) 43#define CPM_CR_MCC1_SBLOCK (0x1c) 44 45#define CPM_CR_FCC_SBLOCK(x) (x + 0x10) 46 47#define CPM_CR_SCC1_PAGE (0x00) 48#define CPM_CR_SCC2_PAGE (0x01) 49#define CPM_CR_SCC3_PAGE (0x02) 50#define CPM_CR_SCC4_PAGE (0x03) 51#define CPM_CR_SMC1_PAGE (0x07) 52#define CPM_CR_SMC2_PAGE (0x08) 53#define CPM_CR_SPI_PAGE (0x09) 54#define CPM_CR_I2C_PAGE (0x0a) 55#define CPM_CR_TIMER_PAGE (0x0a) 56#define CPM_CR_RAND_PAGE (0x0a) 57#define CPM_CR_FCC1_PAGE (0x04) 58#define CPM_CR_FCC2_PAGE (0x05) 59#define CPM_CR_FCC3_PAGE (0x06) 60#define CPM_CR_IDMA1_PAGE (0x07) 61#define CPM_CR_IDMA2_PAGE (0x08) 62#define CPM_CR_IDMA3_PAGE (0x09) 63#define CPM_CR_IDMA4_PAGE (0x0a) 64#define CPM_CR_MCC1_PAGE (0x07) 65#define CPM_CR_MCC2_PAGE (0x08) 66 67#define CPM_CR_FCC_PAGE(x) (x + 0x04) 68 69/* Some opcodes (there are more...later) 70*/ 71#define CPM_CR_INIT_TRX ((ushort)0x0000) 72#define CPM_CR_INIT_RX ((ushort)0x0001) 73#define CPM_CR_INIT_TX ((ushort)0x0002) 74#define CPM_CR_HUNT_MODE ((ushort)0x0003) 75#define CPM_CR_STOP_TX ((ushort)0x0004) 76#define CPM_CR_GRA_STOP_TX ((ushort)0x0005) 77#define CPM_CR_RESTART_TX ((ushort)0x0006) 78#define CPM_CR_SET_GADDR ((ushort)0x0008) 79#define CPM_CR_START_IDMA ((ushort)0x0009) 80#define CPM_CR_STOP_IDMA ((ushort)0x000b) 81 82#define mk_cr_cmd(PG, SBC, MCN, OP) \ 83 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) 84 85/* Dual Port RAM addresses. The first 16K is available for almost 86 * any CPM use, so we put the BDs there. The first 128 bytes are 87 * used for SMC1 and SMC2 parameter RAM, so we start allocating 88 * BDs above that. All of this must change when we start 89 * downloading RAM microcode. 90 */ 91#define CPM_DATAONLY_BASE ((uint)128) 92#define CPM_DP_NOSPACE ((uint)0x7fffffff) 93#if defined(CONFIG_8272) || defined(CONFIG_MPC8555) 94#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) 95#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) 96#else 97#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) 98#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) 99#endif 100 101/* The number of pages of host memory we allocate for CPM. This is 102 * done early in kernel initialization to get physically contiguous 103 * pages. 104 */ 105#define NUM_CPM_HOST_PAGES 2 106 107/* Export the base address of the communication processor registers 108 * and dual port ram. 109 */ 110extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */ 111 112extern unsigned long cpm_dpalloc(uint size, uint align); 113extern int cpm_dpfree(unsigned long offset); 114extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); 115extern void cpm_dpdump(void); 116extern void *cpm_dpram_addr(unsigned long offset); 117extern void cpm_setbrg(uint brg, uint rate); 118extern void cpm2_fastbrg(uint brg, uint rate, int div16); 119extern void cpm2_reset(void); 120 121 122/* Buffer descriptors used by many of the CPM protocols. 123*/ 124typedef struct cpm_buf_desc { 125 ushort cbd_sc; /* Status and Control */ 126 ushort cbd_datlen; /* Data length in buffer */ 127 uint cbd_bufaddr; /* Buffer address in host memory */ 128} cbd_t; 129 130#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 131#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 132#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 133#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 134#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ 135#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ 136#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 137#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 138#define BD_SC_BR ((ushort)0x0020) /* Break received */ 139#define BD_SC_FR ((ushort)0x0010) /* Framing error */ 140#define BD_SC_PR ((ushort)0x0008) /* Parity error */ 141#define BD_SC_OV ((ushort)0x0002) /* Overrun */ 142#define BD_SC_CD ((ushort)0x0001) /* ?? */ 143 144/* Function code bits, usually generic to devices. 145*/ 146#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ 147#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ 148#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ 149#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ 150#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ 151 152/* Parameter RAM offsets from the base. 153*/ 154#define PROFF_SCC1 ((uint)0x8000) 155#define PROFF_SCC2 ((uint)0x8100) 156#define PROFF_SCC3 ((uint)0x8200) 157#define PROFF_SCC4 ((uint)0x8300) 158#define PROFF_FCC1 ((uint)0x8400) 159#define PROFF_FCC2 ((uint)0x8500) 160#define PROFF_FCC3 ((uint)0x8600) 161#define PROFF_MCC1 ((uint)0x8700) 162#define PROFF_SMC1_BASE ((uint)0x87fc) 163#define PROFF_IDMA1_BASE ((uint)0x87fe) 164#define PROFF_MCC2 ((uint)0x8800) 165#define PROFF_SMC2_BASE ((uint)0x88fc) 166#define PROFF_IDMA2_BASE ((uint)0x88fe) 167#define PROFF_SPI_BASE ((uint)0x89fc) 168#define PROFF_IDMA3_BASE ((uint)0x89fe) 169#define PROFF_TIMERS ((uint)0x8ae0) 170#define PROFF_REVNUM ((uint)0x8af0) 171#define PROFF_RAND ((uint)0x8af8) 172#define PROFF_I2C_BASE ((uint)0x8afc) 173#define PROFF_IDMA4_BASE ((uint)0x8afe) 174 175#define PROFF_SCC_SIZE ((uint)0x100) 176#define PROFF_FCC_SIZE ((uint)0x100) 177#define PROFF_SMC_SIZE ((uint)64) 178 179/* The SMCs are relocated to any of the first eight DPRAM pages. 180 * We will fix these at the first locations of DPRAM, until we 181 * get some microcode patches :-). 182 * The parameter ram space for the SMCs is fifty-some bytes, and 183 * they are required to start on a 64 byte boundary. 184 */ 185#define PROFF_SMC1 (0) 186#define PROFF_SMC2 (64) 187 188 189/* Define enough so I can at least use the serial port as a UART. 190 */ 191typedef struct smc_uart { 192 ushort smc_rbase; /* Rx Buffer descriptor base address */ 193 ushort smc_tbase; /* Tx Buffer descriptor base address */ 194 u_char smc_rfcr; /* Rx function code */ 195 u_char smc_tfcr; /* Tx function code */ 196 ushort smc_mrblr; /* Max receive buffer length */ 197 uint smc_rstate; /* Internal */ 198 uint smc_idp; /* Internal */ 199 ushort smc_rbptr; /* Internal */ 200 ushort smc_ibc; /* Internal */ 201 uint smc_rxtmp; /* Internal */ 202 uint smc_tstate; /* Internal */ 203 uint smc_tdp; /* Internal */ 204 ushort smc_tbptr; /* Internal */ 205 ushort smc_tbc; /* Internal */ 206 uint smc_txtmp; /* Internal */ 207 ushort smc_maxidl; /* Maximum idle characters */ 208 ushort smc_tmpidl; /* Temporary idle counter */ 209 ushort smc_brklen; /* Last received break length */ 210 ushort smc_brkec; /* rcv'd break condition counter */ 211 ushort smc_brkcr; /* xmt break count register */ 212 ushort smc_rmask; /* Temporary bit mask */ 213 uint smc_stmp; /* SDMA Temp */ 214} smc_uart_t; 215 216/* SMC uart mode register (Internal memory map). 217*/ 218#define SMCMR_REN ((ushort)0x0001) 219#define SMCMR_TEN ((ushort)0x0002) 220#define SMCMR_DM ((ushort)0x000c) 221#define SMCMR_SM_GCI ((ushort)0x0000) 222#define SMCMR_SM_UART ((ushort)0x0020) 223#define SMCMR_SM_TRANS ((ushort)0x0030) 224#define SMCMR_SM_MASK ((ushort)0x0030) 225#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ 226#define SMCMR_REVD SMCMR_PM_EVEN 227#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ 228#define SMCMR_BS SMCMR_PEN 229#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ 230#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ 231#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) 232 233/* SMC Event and Mask register. 234*/ 235#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ 236#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ 237#define SMCM_TXE ((unsigned char)0x10) 238#define SMCM_BSY ((unsigned char)0x04) 239#define SMCM_TX ((unsigned char)0x02) 240#define SMCM_RX ((unsigned char)0x01) 241 242/* Baud rate generators. 243*/ 244#define CPM_BRG_RST ((uint)0x00020000) 245#define CPM_BRG_EN ((uint)0x00010000) 246#define CPM_BRG_EXTC_INT ((uint)0x00000000) 247#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) 248#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) 249#define CPM_BRG_ATB ((uint)0x00002000) 250#define CPM_BRG_CD_MASK ((uint)0x00001ffe) 251#define CPM_BRG_DIV16 ((uint)0x00000001) 252 253/* SCCs. 254*/ 255#define SCC_GSMRH_IRP ((uint)0x00040000) 256#define SCC_GSMRH_GDE ((uint)0x00010000) 257#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) 258#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) 259#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) 260#define SCC_GSMRH_REVD ((uint)0x00002000) 261#define SCC_GSMRH_TRX ((uint)0x00001000) 262#define SCC_GSMRH_TTX ((uint)0x00000800) 263#define SCC_GSMRH_CDP ((uint)0x00000400) 264#define SCC_GSMRH_CTSP ((uint)0x00000200) 265#define SCC_GSMRH_CDS ((uint)0x00000100) 266#define SCC_GSMRH_CTSS ((uint)0x00000080) 267#define SCC_GSMRH_TFL ((uint)0x00000040) 268#define SCC_GSMRH_RFW ((uint)0x00000020) 269#define SCC_GSMRH_TXSY ((uint)0x00000010) 270#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) 271#define SCC_GSMRH_SYNL8 ((uint)0x00000008) 272#define SCC_GSMRH_SYNL4 ((uint)0x00000004) 273#define SCC_GSMRH_RTSM ((uint)0x00000002) 274#define SCC_GSMRH_RSYN ((uint)0x00000001) 275 276#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ 277#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) 278#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) 279#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) 280#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) 281#define SCC_GSMRL_TCI ((uint)0x10000000) 282#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) 283#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) 284#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) 285#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) 286#define SCC_GSMRL_RINV ((uint)0x02000000) 287#define SCC_GSMRL_TINV ((uint)0x01000000) 288#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) 289#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) 290#define SCC_GSMRL_TPL_48 ((uint)0x00800000) 291#define SCC_GSMRL_TPL_32 ((uint)0x00600000) 292#define SCC_GSMRL_TPL_16 ((uint)0x00400000) 293#define SCC_GSMRL_TPL_8 ((uint)0x00200000) 294#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) 295#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) 296#define SCC_GSMRL_TPP_01 ((uint)0x00100000) 297#define SCC_GSMRL_TPP_10 ((uint)0x00080000) 298#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) 299#define SCC_GSMRL_TEND ((uint)0x00040000) 300#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) 301#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) 302#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) 303#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) 304#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) 305#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) 306#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) 307#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) 308#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) 309#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) 310#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) 311#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) 312#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) 313#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) 314#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) 315#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) 316#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) 317#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) 318#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ 319#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) 320#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) 321#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) 322#define SCC_GSMRL_ENR ((uint)0x00000020) 323#define SCC_GSMRL_ENT ((uint)0x00000010) 324#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) 325#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) 326#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) 327#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) 328#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) 329#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) 330#define SCC_GSMRL_MODE_UART ((uint)0x00000004) 331#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) 332#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) 333#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) 334 335#define SCC_TODR_TOD ((ushort)0x8000) 336 337/* SCC Event and Mask register. 338*/ 339#define SCCM_TXE ((unsigned char)0x10) 340#define SCCM_BSY ((unsigned char)0x04) 341#define SCCM_TX ((unsigned char)0x02) 342#define SCCM_RX ((unsigned char)0x01) 343 344typedef struct scc_param { 345 ushort scc_rbase; /* Rx Buffer descriptor base address */ 346 ushort scc_tbase; /* Tx Buffer descriptor base address */ 347 u_char scc_rfcr; /* Rx function code */ 348 u_char scc_tfcr; /* Tx function code */ 349 ushort scc_mrblr; /* Max receive buffer length */ 350 uint scc_rstate; /* Internal */ 351 uint scc_idp; /* Internal */ 352 ushort scc_rbptr; /* Internal */ 353 ushort scc_ibc; /* Internal */ 354 uint scc_rxtmp; /* Internal */ 355 uint scc_tstate; /* Internal */ 356 uint scc_tdp; /* Internal */ 357 ushort scc_tbptr; /* Internal */ 358 ushort scc_tbc; /* Internal */ 359 uint scc_txtmp; /* Internal */ 360 uint scc_rcrc; /* Internal */ 361 uint scc_tcrc; /* Internal */ 362} sccp_t; 363 364/* CPM Ethernet through SCC1. 365 */ 366typedef struct scc_enet { 367 sccp_t sen_genscc; 368 uint sen_cpres; /* Preset CRC */ 369 uint sen_cmask; /* Constant mask for CRC */ 370 uint sen_crcec; /* CRC Error counter */ 371 uint sen_alec; /* alignment error counter */ 372 uint sen_disfc; /* discard frame counter */ 373 ushort sen_pads; /* Tx short frame pad character */ 374 ushort sen_retlim; /* Retry limit threshold */ 375 ushort sen_retcnt; /* Retry limit counter */ 376 ushort sen_maxflr; /* maximum frame length register */ 377 ushort sen_minflr; /* minimum frame length register */ 378 ushort sen_maxd1; /* maximum DMA1 length */ 379 ushort sen_maxd2; /* maximum DMA2 length */ 380 ushort sen_maxd; /* Rx max DMA */ 381 ushort sen_dmacnt; /* Rx DMA counter */ 382 ushort sen_maxb; /* Max BD byte count */ 383 ushort sen_gaddr1; /* Group address filter */ 384 ushort sen_gaddr2; 385 ushort sen_gaddr3; 386 ushort sen_gaddr4; 387 uint sen_tbuf0data0; /* Save area 0 - current frame */ 388 uint sen_tbuf0data1; /* Save area 1 - current frame */ 389 uint sen_tbuf0rba; /* Internal */ 390 uint sen_tbuf0crc; /* Internal */ 391 ushort sen_tbuf0bcnt; /* Internal */ 392 ushort sen_paddrh; /* physical address (MSB) */ 393 ushort sen_paddrm; 394 ushort sen_paddrl; /* physical address (LSB) */ 395 ushort sen_pper; /* persistence */ 396 ushort sen_rfbdptr; /* Rx first BD pointer */ 397 ushort sen_tfbdptr; /* Tx first BD pointer */ 398 ushort sen_tlbdptr; /* Tx last BD pointer */ 399 uint sen_tbuf1data0; /* Save area 0 - current frame */ 400 uint sen_tbuf1data1; /* Save area 1 - current frame */ 401 uint sen_tbuf1rba; /* Internal */ 402 uint sen_tbuf1crc; /* Internal */ 403 ushort sen_tbuf1bcnt; /* Internal */ 404 ushort sen_txlen; /* Tx Frame length counter */ 405 ushort sen_iaddr1; /* Individual address filter */ 406 ushort sen_iaddr2; 407 ushort sen_iaddr3; 408 ushort sen_iaddr4; 409 ushort sen_boffcnt; /* Backoff counter */ 410 411 /* NOTE: Some versions of the manual have the following items 412 * incorrectly documented. Below is the proper order. 413 */ 414 ushort sen_taddrh; /* temp address (MSB) */ 415 ushort sen_taddrm; 416 ushort sen_taddrl; /* temp address (LSB) */ 417} scc_enet_t; 418 419 420/* SCC Event register as used by Ethernet. 421*/ 422#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 423#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 424#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ 425#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ 426#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 427#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 428 429/* SCC Mode Register (PSMR) as used by Ethernet. 430*/ 431#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ 432#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ 433#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ 434#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ 435#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ 436#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ 437#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ 438#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ 439#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ 440#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ 441#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ 442#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ 443#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ 444 445/* Buffer descriptor control/status used by Ethernet receive. 446 * Common to SCC and FCC. 447 */ 448#define BD_ENET_RX_EMPTY ((ushort)0x8000) 449#define BD_ENET_RX_WRAP ((ushort)0x2000) 450#define BD_ENET_RX_INTR ((ushort)0x1000) 451#define BD_ENET_RX_LAST ((ushort)0x0800) 452#define BD_ENET_RX_FIRST ((ushort)0x0400) 453#define BD_ENET_RX_MISS ((ushort)0x0100) 454#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ 455#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ 456#define BD_ENET_RX_LG ((ushort)0x0020) 457#define BD_ENET_RX_NO ((ushort)0x0010) 458#define BD_ENET_RX_SH ((ushort)0x0008) 459#define BD_ENET_RX_CR ((ushort)0x0004) 460#define BD_ENET_RX_OV ((ushort)0x0002) 461#define BD_ENET_RX_CL ((ushort)0x0001) 462#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ 463 464/* Buffer descriptor control/status used by Ethernet transmit. 465 * Common to SCC and FCC. 466 */ 467#define BD_ENET_TX_READY ((ushort)0x8000) 468#define BD_ENET_TX_PAD ((ushort)0x4000) 469#define BD_ENET_TX_WRAP ((ushort)0x2000) 470#define BD_ENET_TX_INTR ((ushort)0x1000) 471#define BD_ENET_TX_LAST ((ushort)0x0800) 472#define BD_ENET_TX_TC ((ushort)0x0400) 473#define BD_ENET_TX_DEF ((ushort)0x0200) 474#define BD_ENET_TX_HB ((ushort)0x0100) 475#define BD_ENET_TX_LC ((ushort)0x0080) 476#define BD_ENET_TX_RL ((ushort)0x0040) 477#define BD_ENET_TX_RCMASK ((ushort)0x003c) 478#define BD_ENET_TX_UN ((ushort)0x0002) 479#define BD_ENET_TX_CSL ((ushort)0x0001) 480#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 481 482/* SCC as UART 483*/ 484typedef struct scc_uart { 485 sccp_t scc_genscc; 486 uint scc_res1; /* Reserved */ 487 uint scc_res2; /* Reserved */ 488 ushort scc_maxidl; /* Maximum idle chars */ 489 ushort scc_idlc; /* temp idle counter */ 490 ushort scc_brkcr; /* Break count register */ 491 ushort scc_parec; /* receive parity error counter */ 492 ushort scc_frmec; /* receive framing error counter */ 493 ushort scc_nosec; /* receive noise counter */ 494 ushort scc_brkec; /* receive break condition counter */ 495 ushort scc_brkln; /* last received break length */ 496 ushort scc_uaddr1; /* UART address character 1 */ 497 ushort scc_uaddr2; /* UART address character 2 */ 498 ushort scc_rtemp; /* Temp storage */ 499 ushort scc_toseq; /* Transmit out of sequence char */ 500 ushort scc_char1; /* control character 1 */ 501 ushort scc_char2; /* control character 2 */ 502 ushort scc_char3; /* control character 3 */ 503 ushort scc_char4; /* control character 4 */ 504 ushort scc_char5; /* control character 5 */ 505 ushort scc_char6; /* control character 6 */ 506 ushort scc_char7; /* control character 7 */ 507 ushort scc_char8; /* control character 8 */ 508 ushort scc_rccm; /* receive control character mask */ 509 ushort scc_rccr; /* receive control character register */ 510 ushort scc_rlbc; /* receive last break character */ 511} scc_uart_t; 512 513/* SCC Event and Mask registers when it is used as a UART. 514*/ 515#define UART_SCCM_GLR ((ushort)0x1000) 516#define UART_SCCM_GLT ((ushort)0x0800) 517#define UART_SCCM_AB ((ushort)0x0200) 518#define UART_SCCM_IDL ((ushort)0x0100) 519#define UART_SCCM_GRA ((ushort)0x0080) 520#define UART_SCCM_BRKE ((ushort)0x0040) 521#define UART_SCCM_BRKS ((ushort)0x0020) 522#define UART_SCCM_CCR ((ushort)0x0008) 523#define UART_SCCM_BSY ((ushort)0x0004) 524#define UART_SCCM_TX ((ushort)0x0002) 525#define UART_SCCM_RX ((ushort)0x0001) 526 527/* The SCC PSMR when used as a UART. 528*/ 529#define SCU_PSMR_FLC ((ushort)0x8000) 530#define SCU_PSMR_SL ((ushort)0x4000) 531#define SCU_PSMR_CL ((ushort)0x3000) 532#define SCU_PSMR_UM ((ushort)0x0c00) 533#define SCU_PSMR_FRZ ((ushort)0x0200) 534#define SCU_PSMR_RZS ((ushort)0x0100) 535#define SCU_PSMR_SYN ((ushort)0x0080) 536#define SCU_PSMR_DRT ((ushort)0x0040) 537#define SCU_PSMR_PEN ((ushort)0x0010) 538#define SCU_PSMR_RPM ((ushort)0x000c) 539#define SCU_PSMR_REVP ((ushort)0x0008) 540#define SCU_PSMR_TPM ((ushort)0x0003) 541#define SCU_PSMR_TEVP ((ushort)0x0002) 542 543/* CPM Transparent mode SCC. 544 */ 545typedef struct scc_trans { 546 sccp_t st_genscc; 547 uint st_cpres; /* Preset CRC */ 548 uint st_cmask; /* Constant mask for CRC */ 549} scc_trans_t; 550 551#define BD_SCC_TX_LAST ((ushort)0x0800) 552 553/* How about some FCCs..... 554*/ 555#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) 556#define FCC_GFMR_DIAG_LE ((uint)0x40000000) 557#define FCC_GFMR_DIAG_AE ((uint)0x80000000) 558#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) 559#define FCC_GFMR_TCI ((uint)0x20000000) 560#define FCC_GFMR_TRX ((uint)0x10000000) 561#define FCC_GFMR_TTX ((uint)0x08000000) 562#define FCC_GFMR_TTX ((uint)0x08000000) 563#define FCC_GFMR_CDP ((uint)0x04000000) 564#define FCC_GFMR_CTSP ((uint)0x02000000) 565#define FCC_GFMR_CDS ((uint)0x01000000) 566#define FCC_GFMR_CTSS ((uint)0x00800000) 567#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) 568#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) 569#define FCC_GFMR_SYNL_8 ((uint)0x00008000) 570#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) 571#define FCC_GFMR_RTSM ((uint)0x00002000) 572#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) 573#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) 574#define FCC_GFMR_REVD ((uint)0x00000400) 575#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) 576#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) 577#define FCC_GFMR_TCRC_16 ((uint)0x00000000) 578#define FCC_GFMR_TCRC_32 ((uint)0x00000080) 579#define FCC_GFMR_ENR ((uint)0x00000020) 580#define FCC_GFMR_ENT ((uint)0x00000010) 581#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) 582#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) 583#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) 584 585/* Generic FCC parameter ram. 586*/ 587typedef struct fcc_param { 588 ushort fcc_riptr; /* Rx Internal temp pointer */ 589 ushort fcc_tiptr; /* Tx Internal temp pointer */ 590 ushort fcc_res1; 591 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ 592 uint fcc_rstate; /* Upper byte is Func code, must be set */ 593 uint fcc_rbase; /* Receive BD base */ 594 ushort fcc_rbdstat; /* RxBD status */ 595 ushort fcc_rbdlen; /* RxBD down counter */ 596 uint fcc_rdptr; /* RxBD internal data pointer */ 597 uint fcc_tstate; /* Upper byte is Func code, must be set */ 598 uint fcc_tbase; /* Transmit BD base */ 599 ushort fcc_tbdstat; /* TxBD status */ 600 ushort fcc_tbdlen; /* TxBD down counter */ 601 uint fcc_tdptr; /* TxBD internal data pointer */ 602 uint fcc_rbptr; /* Rx BD Internal buf pointer */ 603 uint fcc_tbptr; /* Tx BD Internal buf pointer */ 604 uint fcc_rcrc; /* Rx temp CRC */ 605 uint fcc_res2; 606 uint fcc_tcrc; /* Tx temp CRC */ 607} fccp_t; 608 609 610/* Ethernet controller through FCC. 611*/ 612typedef struct fcc_enet { 613 fccp_t fen_genfcc; 614 uint fen_statbuf; /* Internal status buffer */ 615 uint fen_camptr; /* CAM address */ 616 uint fen_cmask; /* Constant mask for CRC */ 617 uint fen_cpres; /* Preset CRC */ 618 uint fen_crcec; /* CRC Error counter */ 619 uint fen_alec; /* alignment error counter */ 620 uint fen_disfc; /* discard frame counter */ 621 ushort fen_retlim; /* Retry limit */ 622 ushort fen_retcnt; /* Retry counter */ 623 ushort fen_pper; /* Persistence */ 624 ushort fen_boffcnt; /* backoff counter */ 625 uint fen_gaddrh; /* Group address filter, high 32-bits */ 626 uint fen_gaddrl; /* Group address filter, low 32-bits */ 627 ushort fen_tfcstat; /* out of sequence TxBD */ 628 ushort fen_tfclen; 629 uint fen_tfcptr; 630 ushort fen_mflr; /* Maximum frame length (1518) */ 631 ushort fen_paddrh; /* MAC address */ 632 ushort fen_paddrm; 633 ushort fen_paddrl; 634 ushort fen_ibdcount; /* Internal BD counter */ 635 ushort fen_ibdstart; /* Internal BD start pointer */ 636 ushort fen_ibdend; /* Internal BD end pointer */ 637 ushort fen_txlen; /* Internal Tx frame length counter */ 638 uint fen_ibdbase[8]; /* Internal use */ 639 uint fen_iaddrh; /* Individual address filter */ 640 uint fen_iaddrl; 641 ushort fen_minflr; /* Minimum frame length (64) */ 642 ushort fen_taddrh; /* Filter transfer MAC address */ 643 ushort fen_taddrm; 644 ushort fen_taddrl; 645 ushort fen_padptr; /* Pointer to pad byte buffer */ 646 ushort fen_cftype; /* control frame type */ 647 ushort fen_cfrange; /* control frame range */ 648 ushort fen_maxb; /* maximum BD count */ 649 ushort fen_maxd1; /* Max DMA1 length (1520) */ 650 ushort fen_maxd2; /* Max DMA2 length (1520) */ 651 ushort fen_maxd; /* internal max DMA count */ 652 ushort fen_dmacnt; /* internal DMA counter */ 653 uint fen_octc; /* Total octect counter */ 654 uint fen_colc; /* Total collision counter */ 655 uint fen_broc; /* Total broadcast packet counter */ 656 uint fen_mulc; /* Total multicast packet count */ 657 uint fen_uspc; /* Total packets < 64 bytes */ 658 uint fen_frgc; /* Total packets < 64 bytes with errors */ 659 uint fen_ospc; /* Total packets > 1518 */ 660 uint fen_jbrc; /* Total packets > 1518 with errors */ 661 uint fen_p64c; /* Total packets == 64 bytes */ 662 uint fen_p65c; /* Total packets 64 < bytes <= 127 */ 663 uint fen_p128c; /* Total packets 127 < bytes <= 255 */ 664 uint fen_p256c; /* Total packets 256 < bytes <= 511 */ 665 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ 666 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ 667 uint fen_cambuf; /* Internal CAM buffer poiner */ 668 ushort fen_rfthr; /* Received frames threshold */ 669 ushort fen_rfcnt; /* Received frames count */ 670} fcc_enet_t; 671 672/* FCC Event/Mask register as used by Ethernet. 673*/ 674#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 675#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ 676#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ 677#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 678#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ 679#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ 680#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 681#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 682 683/* FCC Mode Register (FPSMR) as used by Ethernet. 684*/ 685#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ 686#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ 687#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ 688#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ 689#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ 690#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ 691#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ 692#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ 693#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ 694#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ 695#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ 696#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ 697#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ 698 699/* IIC parameter RAM. 700*/ 701typedef struct iic { 702 ushort iic_rbase; /* Rx Buffer descriptor base address */ 703 ushort iic_tbase; /* Tx Buffer descriptor base address */ 704 u_char iic_rfcr; /* Rx function code */ 705 u_char iic_tfcr; /* Tx function code */ 706 ushort iic_mrblr; /* Max receive buffer length */ 707 uint iic_rstate; /* Internal */ 708 uint iic_rdp; /* Internal */ 709 ushort iic_rbptr; /* Internal */ 710 ushort iic_rbc; /* Internal */ 711 uint iic_rxtmp; /* Internal */ 712 uint iic_tstate; /* Internal */ 713 uint iic_tdp; /* Internal */ 714 ushort iic_tbptr; /* Internal */ 715 ushort iic_tbc; /* Internal */ 716 uint iic_txtmp; /* Internal */ 717} iic_t; 718 719/* SPI parameter RAM. 720*/ 721typedef struct spi { 722 ushort spi_rbase; /* Rx Buffer descriptor base address */ 723 ushort spi_tbase; /* Tx Buffer descriptor base address */ 724 u_char spi_rfcr; /* Rx function code */ 725 u_char spi_tfcr; /* Tx function code */ 726 ushort spi_mrblr; /* Max receive buffer length */ 727 uint spi_rstate; /* Internal */ 728 uint spi_rdp; /* Internal */ 729 ushort spi_rbptr; /* Internal */ 730 ushort spi_rbc; /* Internal */ 731 uint spi_rxtmp; /* Internal */ 732 uint spi_tstate; /* Internal */ 733 uint spi_tdp; /* Internal */ 734 ushort spi_tbptr; /* Internal */ 735 ushort spi_tbc; /* Internal */ 736 uint spi_txtmp; /* Internal */ 737 uint spi_res; /* Tx temp. */ 738 uint spi_res1[4]; /* SDMA temp. */ 739} spi_t; 740 741/* SPI Mode register. 742*/ 743#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ 744#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ 745#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ 746#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ 747#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ 748#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ 749#define SPMODE_EN ((ushort)0x0100) /* Enable */ 750#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ 751#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ 752 753#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) 754#define SPMODE_PM(x) ((x) &0xF) 755 756#define SPI_EB ((u_char)0x10) /* big endian byte order */ 757 758#define BD_IIC_START ((ushort)0x0400) 759 760/* IDMA parameter RAM 761*/ 762typedef struct idma { 763 ushort ibase; /* IDMA buffer descriptor table base address */ 764 ushort dcm; /* DMA channel mode */ 765 ushort ibdptr; /* IDMA current buffer descriptor pointer */ 766 ushort dpr_buf; /* IDMA transfer buffer base address */ 767 ushort buf_inv; /* internal buffer inventory */ 768 ushort ss_max; /* steady-state maximum transfer size */ 769 ushort dpr_in_ptr; /* write pointer inside the internal buffer */ 770 ushort sts; /* source transfer size */ 771 ushort dpr_out_ptr; /* read pointer inside the internal buffer */ 772 ushort seob; /* source end of burst */ 773 ushort deob; /* destination end of burst */ 774 ushort dts; /* destination transfer size */ 775 ushort ret_add; /* return address when working in ERM=1 mode */ 776 ushort res0; /* reserved */ 777 uint bd_cnt; /* internal byte count */ 778 uint s_ptr; /* source internal data pointer */ 779 uint d_ptr; /* destination internal data pointer */ 780 uint istate; /* internal state */ 781 u_char res1[20]; /* pad to 64-byte length */ 782} idma_t; 783 784/* DMA channel mode bit fields 785*/ 786#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */ 787#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */ 788#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */ 789#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */ 790#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */ 791#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */ 792#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */ 793#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */ 794#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */ 795#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */ 796#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */ 797#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */ 798#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */ 799#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */ 800#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */ 801#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */ 802#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */ 803#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */ 804 805/* IDMA Buffer Descriptors 806*/ 807typedef struct idma_bd { 808 uint flags; 809 uint len; /* data length */ 810 uint src; /* source data buffer pointer */ 811 uint dst; /* destination data buffer pointer */ 812} idma_bd_t; 813 814/* IDMA buffer descriptor flag bit fields 815*/ 816#define IDMA_BD_V ((uint)0x80000000) /* valid */ 817#define IDMA_BD_W ((uint)0x20000000) /* wrap */ 818#define IDMA_BD_I ((uint)0x10000000) /* interrupt */ 819#define IDMA_BD_L ((uint)0x08000000) /* last */ 820#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */ 821#define IDMA_BD_SDN ((uint)0x00400000) /* source done */ 822#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */ 823#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */ 824#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */ 825#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */ 826#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */ 827#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */ 828#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */ 829#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */ 830#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */ 831 832/* per-channel IDMA registers 833*/ 834typedef struct im_idma { 835 u_char idsr; /* IDMAn event status register */ 836 u_char res0[3]; 837 u_char idmr; /* IDMAn event mask register */ 838 u_char res1[3]; 839} im_idma_t; 840 841/* IDMA event register bit fields 842*/ 843#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */ 844#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */ 845#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */ 846#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */ 847 848/* RISC Controller Configuration Register (RCCR) bit fields 849*/ 850#define RCCR_TIME ((uint)0x80000000) /* timer enable */ 851#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */ 852#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */ 853#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */ 854#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */ 855#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */ 856#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */ 857#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */ 858#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */ 859#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */ 860#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */ 861#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */ 862#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */ 863#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */ 864#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */ 865#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */ 866#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */ 867#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */ 868#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */ 869#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */ 870#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */ 871#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */ 872#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */ 873#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */ 874#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */ 875#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */ 876#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */ 877#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */ 878#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */ 879#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */ 880#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */ 881#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */ 882#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */ 883#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */ 884#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */ 885#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */ 886#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */ 887#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */ 888 889/*----------------------------------------------------------------------- 890 * CMXFCR - CMX FCC Clock Route Register 891 */ 892#define CMXFCR_FC1 0x40000000 /* FCC1 connection */ 893#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ 894#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ 895#define CMXFCR_FC2 0x00400000 /* FCC2 connection */ 896#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ 897#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ 898#define CMXFCR_FC3 0x00004000 /* FCC3 connection */ 899#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ 900#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ 901 902#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ 903#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ 904#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ 905#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ 906#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ 907#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ 908#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ 909#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ 910 911#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ 912#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ 913#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ 914#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ 915#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ 916#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ 917#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ 918#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ 919 920#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ 921#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ 922#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ 923#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ 924#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ 925#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ 926#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ 927#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ 928 929#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ 930#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ 931#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ 932#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ 933#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ 934#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ 935#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ 936#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ 937 938#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ 939#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ 940#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ 941#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ 942#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ 943#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ 944#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ 945#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ 946 947#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ 948#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ 949#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ 950#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ 951#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ 952#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ 953#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ 954#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ 955 956/*----------------------------------------------------------------------- 957 * CMXSCR - CMX SCC Clock Route Register 958 */ 959#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ 960#define CMXSCR_SC1 0x40000000 /* SCC1 connection */ 961#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ 962#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ 963#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ 964#define CMXSCR_SC2 0x00400000 /* SCC2 connection */ 965#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ 966#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ 967#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ 968#define CMXSCR_SC3 0x00004000 /* SCC3 connection */ 969#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ 970#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ 971#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ 972#define CMXSCR_SC4 0x00000040 /* SCC4 connection */ 973#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ 974#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ 975 976#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ 977#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ 978#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ 979#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ 980#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ 981#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ 982#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ 983#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ 984 985#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ 986#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ 987#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ 988#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ 989#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ 990#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ 991#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ 992#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ 993 994#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ 995#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ 996#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ 997#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ 998#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ 999#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ 1000#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ 1001#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ 1002 1003#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ 1004#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ 1005#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ 1006#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ 1007#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ 1008#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ 1009#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ 1010#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ 1011 1012#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ 1013#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ 1014#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ 1015#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ 1016#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ 1017#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ 1018#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ 1019#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ 1020 1021#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ 1022#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ 1023#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ 1024#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ 1025#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ 1026#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ 1027#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ 1028#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ 1029 1030#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ 1031#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ 1032#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ 1033#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ 1034#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ 1035#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ 1036#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ 1037#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ 1038 1039#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ 1040#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ 1041#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ 1042#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ 1043#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ 1044#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ 1045#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ 1046#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ 1047 1048/*----------------------------------------------------------------------- 1049 * SIUMCR - SIU Module Configuration Register 4-31 1050 */ 1051#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */ 1052#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */ 1053#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */ 1054#define SIUMCR_CDIS 0x10000000 /* Core Disable */ 1055#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/ 1056#define SIUMCR_DPPC01 0x04000000 /* - " - */ 1057#define SIUMCR_DPPC10 0x08000000 /* - " - */ 1058#define SIUMCR_DPPC11 0x0c000000 /* - " - */ 1059#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ 1060#define SIUMCR_L2CPC01 0x01000000 /* - " - */ 1061#define SIUMCR_L2CPC10 0x02000000 /* - " - */ 1062#define SIUMCR_L2CPC11 0x03000000 /* - " - */ 1063#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */ 1064#define SIUMCR_LBPC01 0x00400000 /* - " - */ 1065#define SIUMCR_LBPC10 0x00800000 /* - " - */ 1066#define SIUMCR_LBPC11 0x00c00000 /* - " - */ 1067#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/ 1068#define SIUMCR_APPC01 0x00100000 /* - " - */ 1069#define SIUMCR_APPC10 0x00200000 /* - " - */ 1070#define SIUMCR_APPC11 0x00300000 /* - " - */ 1071#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */ 1072#define SIUMCR_CS10PC01 0x00040000 /* - " - */ 1073#define SIUMCR_CS10PC10 0x00080000 /* - " - */ 1074#define SIUMCR_CS10PC11 0x000c0000 /* - " - */ 1075#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */ 1076#define SIUMCR_BCTLC01 0x00010000 /* - " - */ 1077#define SIUMCR_BCTLC10 0x00020000 /* - " - */ 1078#define SIUMCR_BCTLC11 0x00030000 /* - " - */ 1079#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */ 1080#define SIUMCR_MMR01 0x00004000 /* - " - */ 1081#define SIUMCR_MMR10 0x00008000 /* - " - */ 1082#define SIUMCR_MMR11 0x0000c000 /* - " - */ 1083#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/ 1084 1085/*----------------------------------------------------------------------- 1086 * SCCR - System Clock Control Register 9-8 1087*/ 1088#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */ 1089#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */ 1090#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */ 1091#define SCCR_PCIDF_SHIFT 3 1092 1093#ifndef CPM_IMMR_OFFSET 1094#define CPM_IMMR_OFFSET 0x101a8 1095#endif 1096 1097#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ 1098 1099/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK 1100 * in order to use clock-computing stuff below for the FCC x 1101 */ 1102 1103/* Automatically generates register configurations */ 1104#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */ 1105 1106#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */ 1107#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */ 1108#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */ 1109#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */ 1110#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */ 1111#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */ 1112 1113#define PC_F1RXCLK PC_CLK(F1_RXCLK) 1114#define PC_F1TXCLK PC_CLK(F1_TXCLK) 1115#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK)) 1116#define CMX1_CLK_MASK ((uint)0xff000000) 1117 1118#define PC_F2RXCLK PC_CLK(F2_RXCLK) 1119#define PC_F2TXCLK PC_CLK(F2_TXCLK) 1120#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK)) 1121#define CMX2_CLK_MASK ((uint)0x00ff0000) 1122 1123#define PC_F3RXCLK PC_CLK(F3_RXCLK) 1124#define PC_F3TXCLK PC_CLK(F3_TXCLK) 1125#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK)) 1126#define CMX3_CLK_MASK ((uint)0x0000ff00) 1127 1128#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK) 1129#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE) 1130 1131#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK) 1132 1133/* I/O Pin assignment for FCC1. I don't yet know the best way to do this, 1134 * but there is little variation among the choices. 1135 */ 1136#define PA1_COL 0x00000001U 1137#define PA1_CRS 0x00000002U 1138#define PA1_TXER 0x00000004U 1139#define PA1_TXEN 0x00000008U 1140#define PA1_RXDV 0x00000010U 1141#define PA1_RXER 0x00000020U 1142#define PA1_TXDAT 0x00003c00U 1143#define PA1_RXDAT 0x0003c000U 1144#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT) 1145#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \ 1146 PA1_RXDV | PA1_RXER) 1147#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV) 1148#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER) 1149 1150 1151/* I/O Pin assignment for FCC2. I don't yet know the best way to do this, 1152 * but there is little variation among the choices. 1153 */ 1154#define PB2_TXER 0x00000001U 1155#define PB2_RXDV 0x00000002U 1156#define PB2_TXEN 0x00000004U 1157#define PB2_RXER 0x00000008U 1158#define PB2_COL 0x00000010U 1159#define PB2_CRS 0x00000020U 1160#define PB2_TXDAT 0x000003c0U 1161#define PB2_RXDAT 0x00003c00U 1162#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \ 1163 PB2_RXER | PB2_RXDV | PB2_TXER) 1164#define PB2_PSORB1 (PB2_TXEN) 1165#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV) 1166#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER) 1167 1168 1169/* I/O Pin assignment for FCC3. I don't yet know the best way to do this, 1170 * but there is little variation among the choices. 1171 */ 1172#define PB3_RXDV 0x00004000U 1173#define PB3_RXER 0x00008000U 1174#define PB3_TXER 0x00010000U 1175#define PB3_TXEN 0x00020000U 1176#define PB3_COL 0x00040000U 1177#define PB3_CRS 0x00080000U 1178#define PB3_TXDAT 0x0f000000U 1179#define PC3_TXDAT 0x00000010U 1180#define PB3_RXDAT 0x00f00000U 1181#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \ 1182 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN) 1183#define PB3_PSORB1 0 1184#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV) 1185#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER) 1186#define PC3_DIRC1 (PC3_TXDAT) 1187 1188/* Handy macro to specify mem for FCCs*/ 1189#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128)) 1190#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0) 1191#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1) 1192#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2) 1193 1194/* Clocks and GRG's */ 1195 1196enum cpm_clk_dir { 1197 CPM_CLK_RX, 1198 CPM_CLK_TX, 1199 CPM_CLK_RTX 1200}; 1201 1202enum cpm_clk_target { 1203 CPM_CLK_SCC1, 1204 CPM_CLK_SCC2, 1205 CPM_CLK_SCC3, 1206 CPM_CLK_SCC4, 1207 CPM_CLK_FCC1, 1208 CPM_CLK_FCC2, 1209 CPM_CLK_FCC3 1210}; 1211 1212enum cpm_clk { 1213 CPM_CLK_NONE = 0, 1214 CPM_BRG1, /* Baud Rate Generator 1 */ 1215 CPM_BRG2, /* Baud Rate Generator 2 */ 1216 CPM_BRG3, /* Baud Rate Generator 3 */ 1217 CPM_BRG4, /* Baud Rate Generator 4 */ 1218 CPM_BRG5, /* Baud Rate Generator 5 */ 1219 CPM_BRG6, /* Baud Rate Generator 6 */ 1220 CPM_BRG7, /* Baud Rate Generator 7 */ 1221 CPM_BRG8, /* Baud Rate Generator 8 */ 1222 CPM_CLK1, /* Clock 1 */ 1223 CPM_CLK2, /* Clock 2 */ 1224 CPM_CLK3, /* Clock 3 */ 1225 CPM_CLK4, /* Clock 4 */ 1226 CPM_CLK5, /* Clock 5 */ 1227 CPM_CLK6, /* Clock 6 */ 1228 CPM_CLK7, /* Clock 7 */ 1229 CPM_CLK8, /* Clock 8 */ 1230 CPM_CLK9, /* Clock 9 */ 1231 CPM_CLK10, /* Clock 10 */ 1232 CPM_CLK11, /* Clock 11 */ 1233 CPM_CLK12, /* Clock 12 */ 1234 CPM_CLK13, /* Clock 13 */ 1235 CPM_CLK14, /* Clock 14 */ 1236 CPM_CLK15, /* Clock 15 */ 1237 CPM_CLK16, /* Clock 16 */ 1238 CPM_CLK17, /* Clock 17 */ 1239 CPM_CLK18, /* Clock 18 */ 1240 CPM_CLK19, /* Clock 19 */ 1241 CPM_CLK20, /* Clock 20 */ 1242 CPM_CLK_DUMMY 1243}; 1244 1245extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode); 1246 1247#endif /* __CPM2__ */ 1248#endif /* __KERNEL__ */ 1249