1/* 2 * MPC8xx Communication Processor Module. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * This file contains structures and information for the communication 6 * processor channels. Some CPM control and status is available 7 * throught the MPC8xx internal memory map. See immap.h for details. 8 * This file only contains what I need for the moment, not the total 9 * CPM capabilities. I (or someone else) will add definitions as they 10 * are needed. -- Dan 11 * 12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 13 * bytes of the DP RAM and relocates the I2C parameter area to the 14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors 15 * or other use. 16 */ 17#ifndef __CPM_8XX__ 18#define __CPM_8XX__ 19 20#include <asm/8xx_immap.h> 21#include <asm/ptrace.h> 22 23/* CPM Command register. 24*/ 25#define CPM_CR_RST ((ushort)0x8000) 26#define CPM_CR_OPCODE ((ushort)0x0f00) 27#define CPM_CR_CHAN ((ushort)0x00f0) 28#define CPM_CR_FLG ((ushort)0x0001) 29 30/* Some commands (there are more...later) 31*/ 32#define CPM_CR_INIT_TRX ((ushort)0x0000) 33#define CPM_CR_INIT_RX ((ushort)0x0001) 34#define CPM_CR_INIT_TX ((ushort)0x0002) 35#define CPM_CR_HUNT_MODE ((ushort)0x0003) 36#define CPM_CR_STOP_TX ((ushort)0x0004) 37#define CPM_CR_GRA_STOP_TX ((ushort)0x0005) 38#define CPM_CR_RESTART_TX ((ushort)0x0006) 39#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007) 40#define CPM_CR_SET_GADDR ((ushort)0x0008) 41#define CPM_CR_SET_TIMER CPM_CR_SET_GADDR 42 43/* Channel numbers. 44*/ 45#define CPM_CR_CH_SCC1 ((ushort)0x0000) 46#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ 47#define CPM_CR_CH_SCC2 ((ushort)0x0004) 48#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */ 49#define CPM_CR_CH_TIMER CPM_CR_CH_SPI 50#define CPM_CR_CH_SCC3 ((ushort)0x0008) 51#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ 52#define CPM_CR_CH_SCC4 ((ushort)0x000c) 53#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ 54 55#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) 56 57/* The dual ported RAM is multi-functional. Some areas can be (and are 58 * being) used for microcode. There is an area that can only be used 59 * as data ram for buffer descriptors, which is all we use right now. 60 * Currently the first 512 and last 256 bytes are used for microcode. 61 */ 62#define CPM_DATAONLY_BASE ((uint)0x0800) 63#define CPM_DATAONLY_SIZE ((uint)0x0700) 64#define CPM_DP_NOSPACE ((uint)0x7fffffff) 65 66/* Export the base address of the communication processor registers 67 * and dual port ram. 68 */ 69extern cpm8xx_t *cpmp; /* Pointer to comm processor */ 70extern unsigned long cpm_dpalloc(uint size, uint align); 71extern int cpm_dpfree(unsigned long offset); 72extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); 73extern void cpm_dpdump(void); 74extern void *cpm_dpram_addr(unsigned long offset); 75extern uint cpm_dpram_phys(u8* addr); 76extern void cpm_setbrg(uint brg, uint rate); 77 78extern uint m8xx_cpm_hostalloc(uint size); 79extern int m8xx_cpm_hostfree(uint start); 80extern void m8xx_cpm_hostdump(void); 81 82extern void cpm_load_patch(volatile immap_t *immr); 83 84/* Buffer descriptors used by many of the CPM protocols. 85*/ 86typedef struct cpm_buf_desc { 87 ushort cbd_sc; /* Status and Control */ 88 ushort cbd_datlen; /* Data length in buffer */ 89 uint cbd_bufaddr; /* Buffer address in host memory */ 90} cbd_t; 91 92#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 93#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 94#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 95#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 96#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ 97#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ 98#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ 99#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 100#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 101#define BD_SC_BR ((ushort)0x0020) /* Break received */ 102#define BD_SC_FR ((ushort)0x0010) /* Framing error */ 103#define BD_SC_PR ((ushort)0x0008) /* Parity error */ 104#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */ 105#define BD_SC_OV ((ushort)0x0002) /* Overrun */ 106#define BD_SC_UN ((ushort)0x0002) /* Underrun */ 107#define BD_SC_CD ((ushort)0x0001) /* ?? */ 108#define BD_SC_CL ((ushort)0x0001) /* Collision */ 109 110/* Parameter RAM offsets. 111*/ 112#define PROFF_SCC1 ((uint)0x0000) 113#define PROFF_IIC ((uint)0x0080) 114#define PROFF_SCC2 ((uint)0x0100) 115#define PROFF_SPI ((uint)0x0180) 116#define PROFF_SCC3 ((uint)0x0200) 117#define PROFF_SMC1 ((uint)0x0280) 118#define PROFF_SCC4 ((uint)0x0300) 119#define PROFF_SMC2 ((uint)0x0380) 120 121/* Define enough so I can at least use the serial port as a UART. 122 * The MBX uses SMC1 as the host serial port. 123 */ 124typedef struct smc_uart { 125 ushort smc_rbase; /* Rx Buffer descriptor base address */ 126 ushort smc_tbase; /* Tx Buffer descriptor base address */ 127 u_char smc_rfcr; /* Rx function code */ 128 u_char smc_tfcr; /* Tx function code */ 129 ushort smc_mrblr; /* Max receive buffer length */ 130 uint smc_rstate; /* Internal */ 131 uint smc_idp; /* Internal */ 132 ushort smc_rbptr; /* Internal */ 133 ushort smc_ibc; /* Internal */ 134 uint smc_rxtmp; /* Internal */ 135 uint smc_tstate; /* Internal */ 136 uint smc_tdp; /* Internal */ 137 ushort smc_tbptr; /* Internal */ 138 ushort smc_tbc; /* Internal */ 139 uint smc_txtmp; /* Internal */ 140 ushort smc_maxidl; /* Maximum idle characters */ 141 ushort smc_tmpidl; /* Temporary idle counter */ 142 ushort smc_brklen; /* Last received break length */ 143 ushort smc_brkec; /* rcv'd break condition counter */ 144 ushort smc_brkcr; /* xmt break count register */ 145 ushort smc_rmask; /* Temporary bit mask */ 146 char res1[8]; /* Reserved */ 147 ushort smc_rpbase; /* Relocation pointer */ 148} smc_uart_t; 149 150/* Function code bits. 151*/ 152#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ 153 154/* SMC uart mode register. 155*/ 156#define SMCMR_REN ((ushort)0x0001) 157#define SMCMR_TEN ((ushort)0x0002) 158#define SMCMR_DM ((ushort)0x000c) 159#define SMCMR_SM_GCI ((ushort)0x0000) 160#define SMCMR_SM_UART ((ushort)0x0020) 161#define SMCMR_SM_TRANS ((ushort)0x0030) 162#define SMCMR_SM_MASK ((ushort)0x0030) 163#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ 164#define SMCMR_REVD SMCMR_PM_EVEN 165#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ 166#define SMCMR_BS SMCMR_PEN 167#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ 168#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ 169#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) 170 171/* SMC2 as Centronics parallel printer. It is half duplex, in that 172 * it can only receive or transmit. The parameter ram values for 173 * each direction are either unique or properly overlap, so we can 174 * include them in one structure. 175 */ 176typedef struct smc_centronics { 177 ushort scent_rbase; 178 ushort scent_tbase; 179 u_char scent_cfcr; 180 u_char scent_smask; 181 ushort scent_mrblr; 182 uint scent_rstate; 183 uint scent_r_ptr; 184 ushort scent_rbptr; 185 ushort scent_r_cnt; 186 uint scent_rtemp; 187 uint scent_tstate; 188 uint scent_t_ptr; 189 ushort scent_tbptr; 190 ushort scent_t_cnt; 191 uint scent_ttemp; 192 ushort scent_max_sl; 193 ushort scent_sl_cnt; 194 ushort scent_character1; 195 ushort scent_character2; 196 ushort scent_character3; 197 ushort scent_character4; 198 ushort scent_character5; 199 ushort scent_character6; 200 ushort scent_character7; 201 ushort scent_character8; 202 ushort scent_rccm; 203 ushort scent_rccr; 204} smc_cent_t; 205 206/* Centronics Status Mask Register. 207*/ 208#define SMC_CENT_F ((u_char)0x08) 209#define SMC_CENT_PE ((u_char)0x04) 210#define SMC_CENT_S ((u_char)0x02) 211 212/* SMC Event and Mask register. 213*/ 214#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ 215#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ 216#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ 217#define SMCM_BSY ((unsigned char)0x04) 218#define SMCM_TX ((unsigned char)0x02) 219#define SMCM_RX ((unsigned char)0x01) 220 221/* Baud rate generators. 222*/ 223#define CPM_BRG_RST ((uint)0x00020000) 224#define CPM_BRG_EN ((uint)0x00010000) 225#define CPM_BRG_EXTC_INT ((uint)0x00000000) 226#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) 227#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) 228#define CPM_BRG_ATB ((uint)0x00002000) 229#define CPM_BRG_CD_MASK ((uint)0x00001ffe) 230#define CPM_BRG_DIV16 ((uint)0x00000001) 231 232/* SI Clock Route Register 233*/ 234#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) 235#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) 236#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) 237#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) 238#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) 239#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) 240#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) 241#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) 242 243/* SCCs. 244*/ 245#define SCC_GSMRH_IRP ((uint)0x00040000) 246#define SCC_GSMRH_GDE ((uint)0x00010000) 247#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) 248#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) 249#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) 250#define SCC_GSMRH_REVD ((uint)0x00002000) 251#define SCC_GSMRH_TRX ((uint)0x00001000) 252#define SCC_GSMRH_TTX ((uint)0x00000800) 253#define SCC_GSMRH_CDP ((uint)0x00000400) 254#define SCC_GSMRH_CTSP ((uint)0x00000200) 255#define SCC_GSMRH_CDS ((uint)0x00000100) 256#define SCC_GSMRH_CTSS ((uint)0x00000080) 257#define SCC_GSMRH_TFL ((uint)0x00000040) 258#define SCC_GSMRH_RFW ((uint)0x00000020) 259#define SCC_GSMRH_TXSY ((uint)0x00000010) 260#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) 261#define SCC_GSMRH_SYNL8 ((uint)0x00000008) 262#define SCC_GSMRH_SYNL4 ((uint)0x00000004) 263#define SCC_GSMRH_RTSM ((uint)0x00000002) 264#define SCC_GSMRH_RSYN ((uint)0x00000001) 265 266#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ 267#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) 268#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) 269#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) 270#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) 271#define SCC_GSMRL_TCI ((uint)0x10000000) 272#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) 273#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) 274#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) 275#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) 276#define SCC_GSMRL_RINV ((uint)0x02000000) 277#define SCC_GSMRL_TINV ((uint)0x01000000) 278#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) 279#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) 280#define SCC_GSMRL_TPL_48 ((uint)0x00800000) 281#define SCC_GSMRL_TPL_32 ((uint)0x00600000) 282#define SCC_GSMRL_TPL_16 ((uint)0x00400000) 283#define SCC_GSMRL_TPL_8 ((uint)0x00200000) 284#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) 285#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) 286#define SCC_GSMRL_TPP_01 ((uint)0x00100000) 287#define SCC_GSMRL_TPP_10 ((uint)0x00080000) 288#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) 289#define SCC_GSMRL_TEND ((uint)0x00040000) 290#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) 291#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) 292#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) 293#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) 294#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) 295#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) 296#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) 297#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) 298#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) 299#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) 300#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) 301#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) 302#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) 303#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) 304#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) 305#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) 306#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) 307#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) 308#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ 309#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) 310#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) 311#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) 312#define SCC_GSMRL_ENR ((uint)0x00000020) 313#define SCC_GSMRL_ENT ((uint)0x00000010) 314#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) 315#define SCC_GSMRL_MODE_QMC ((uint)0x0000000a) 316#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) 317#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) 318#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) 319#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) 320#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) 321#define SCC_GSMRL_MODE_UART ((uint)0x00000004) 322#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) 323#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) 324#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) 325 326#define SCC_TODR_TOD ((ushort)0x8000) 327 328/* SCC Event and Mask register. 329*/ 330#define SCCM_TXE ((unsigned char)0x10) 331#define SCCM_BSY ((unsigned char)0x04) 332#define SCCM_TX ((unsigned char)0x02) 333#define SCCM_RX ((unsigned char)0x01) 334 335typedef struct scc_param { 336 ushort scc_rbase; /* Rx Buffer descriptor base address */ 337 ushort scc_tbase; /* Tx Buffer descriptor base address */ 338 u_char scc_rfcr; /* Rx function code */ 339 u_char scc_tfcr; /* Tx function code */ 340 ushort scc_mrblr; /* Max receive buffer length */ 341 uint scc_rstate; /* Internal */ 342 uint scc_idp; /* Internal */ 343 ushort scc_rbptr; /* Internal */ 344 ushort scc_ibc; /* Internal */ 345 uint scc_rxtmp; /* Internal */ 346 uint scc_tstate; /* Internal */ 347 uint scc_tdp; /* Internal */ 348 ushort scc_tbptr; /* Internal */ 349 ushort scc_tbc; /* Internal */ 350 uint scc_txtmp; /* Internal */ 351 uint scc_rcrc; /* Internal */ 352 uint scc_tcrc; /* Internal */ 353} sccp_t; 354 355/* Function code bits. 356*/ 357#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ 358 359/* CPM Ethernet through SCCx. 360 */ 361typedef struct scc_enet { 362 sccp_t sen_genscc; 363 uint sen_cpres; /* Preset CRC */ 364 uint sen_cmask; /* Constant mask for CRC */ 365 uint sen_crcec; /* CRC Error counter */ 366 uint sen_alec; /* alignment error counter */ 367 uint sen_disfc; /* discard frame counter */ 368 ushort sen_pads; /* Tx short frame pad character */ 369 ushort sen_retlim; /* Retry limit threshold */ 370 ushort sen_retcnt; /* Retry limit counter */ 371 ushort sen_maxflr; /* maximum frame length register */ 372 ushort sen_minflr; /* minimum frame length register */ 373 ushort sen_maxd1; /* maximum DMA1 length */ 374 ushort sen_maxd2; /* maximum DMA2 length */ 375 ushort sen_maxd; /* Rx max DMA */ 376 ushort sen_dmacnt; /* Rx DMA counter */ 377 ushort sen_maxb; /* Max BD byte count */ 378 ushort sen_gaddr1; /* Group address filter */ 379 ushort sen_gaddr2; 380 ushort sen_gaddr3; 381 ushort sen_gaddr4; 382 uint sen_tbuf0data0; /* Save area 0 - current frame */ 383 uint sen_tbuf0data1; /* Save area 1 - current frame */ 384 uint sen_tbuf0rba; /* Internal */ 385 uint sen_tbuf0crc; /* Internal */ 386 ushort sen_tbuf0bcnt; /* Internal */ 387 ushort sen_paddrh; /* physical address (MSB) */ 388 ushort sen_paddrm; 389 ushort sen_paddrl; /* physical address (LSB) */ 390 ushort sen_pper; /* persistence */ 391 ushort sen_rfbdptr; /* Rx first BD pointer */ 392 ushort sen_tfbdptr; /* Tx first BD pointer */ 393 ushort sen_tlbdptr; /* Tx last BD pointer */ 394 uint sen_tbuf1data0; /* Save area 0 - current frame */ 395 uint sen_tbuf1data1; /* Save area 1 - current frame */ 396 uint sen_tbuf1rba; /* Internal */ 397 uint sen_tbuf1crc; /* Internal */ 398 ushort sen_tbuf1bcnt; /* Internal */ 399 ushort sen_txlen; /* Tx Frame length counter */ 400 ushort sen_iaddr1; /* Individual address filter */ 401 ushort sen_iaddr2; 402 ushort sen_iaddr3; 403 ushort sen_iaddr4; 404 ushort sen_boffcnt; /* Backoff counter */ 405 406 /* NOTE: Some versions of the manual have the following items 407 * incorrectly documented. Below is the proper order. 408 */ 409 ushort sen_taddrh; /* temp address (MSB) */ 410 ushort sen_taddrm; 411 ushort sen_taddrl; /* temp address (LSB) */ 412} scc_enet_t; 413 414/* SCC Event register as used by Ethernet. 415*/ 416#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 417#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 418#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ 419#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ 420#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 421#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 422 423/* SCC Mode Register (PMSR) as used by Ethernet. 424*/ 425#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ 426#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ 427#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ 428#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ 429#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ 430#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ 431#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ 432#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ 433#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ 434#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ 435#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ 436#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ 437#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ 438 439/* Buffer descriptor control/status used by Ethernet receive. 440*/ 441#define BD_ENET_RX_EMPTY ((ushort)0x8000) 442#define BD_ENET_RX_WRAP ((ushort)0x2000) 443#define BD_ENET_RX_INTR ((ushort)0x1000) 444#define BD_ENET_RX_LAST ((ushort)0x0800) 445#define BD_ENET_RX_FIRST ((ushort)0x0400) 446#define BD_ENET_RX_MISS ((ushort)0x0100) 447#define BD_ENET_RX_LG ((ushort)0x0020) 448#define BD_ENET_RX_NO ((ushort)0x0010) 449#define BD_ENET_RX_SH ((ushort)0x0008) 450#define BD_ENET_RX_CR ((ushort)0x0004) 451#define BD_ENET_RX_OV ((ushort)0x0002) 452#define BD_ENET_RX_CL ((ushort)0x0001) 453#define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */ 454#define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */ 455#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 456 457/* Buffer descriptor control/status used by Ethernet transmit. 458*/ 459#define BD_ENET_TX_READY ((ushort)0x8000) 460#define BD_ENET_TX_PAD ((ushort)0x4000) 461#define BD_ENET_TX_WRAP ((ushort)0x2000) 462#define BD_ENET_TX_INTR ((ushort)0x1000) 463#define BD_ENET_TX_LAST ((ushort)0x0800) 464#define BD_ENET_TX_TC ((ushort)0x0400) 465#define BD_ENET_TX_DEF ((ushort)0x0200) 466#define BD_ENET_TX_HB ((ushort)0x0100) 467#define BD_ENET_TX_LC ((ushort)0x0080) 468#define BD_ENET_TX_RL ((ushort)0x0040) 469#define BD_ENET_TX_RCMASK ((ushort)0x003c) 470#define BD_ENET_TX_UN ((ushort)0x0002) 471#define BD_ENET_TX_CSL ((ushort)0x0001) 472#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 473 474/* SCC as UART 475*/ 476typedef struct scc_uart { 477 sccp_t scc_genscc; 478 char res1[8]; /* Reserved */ 479 ushort scc_maxidl; /* Maximum idle chars */ 480 ushort scc_idlc; /* temp idle counter */ 481 ushort scc_brkcr; /* Break count register */ 482 ushort scc_parec; /* receive parity error counter */ 483 ushort scc_frmec; /* receive framing error counter */ 484 ushort scc_nosec; /* receive noise counter */ 485 ushort scc_brkec; /* receive break condition counter */ 486 ushort scc_brkln; /* last received break length */ 487 ushort scc_uaddr1; /* UART address character 1 */ 488 ushort scc_uaddr2; /* UART address character 2 */ 489 ushort scc_rtemp; /* Temp storage */ 490 ushort scc_toseq; /* Transmit out of sequence char */ 491 ushort scc_char1; /* control character 1 */ 492 ushort scc_char2; /* control character 2 */ 493 ushort scc_char3; /* control character 3 */ 494 ushort scc_char4; /* control character 4 */ 495 ushort scc_char5; /* control character 5 */ 496 ushort scc_char6; /* control character 6 */ 497 ushort scc_char7; /* control character 7 */ 498 ushort scc_char8; /* control character 8 */ 499 ushort scc_rccm; /* receive control character mask */ 500 ushort scc_rccr; /* receive control character register */ 501 ushort scc_rlbc; /* receive last break character */ 502} scc_uart_t; 503 504/* SCC Event and Mask registers when it is used as a UART. 505*/ 506#define UART_SCCM_GLR ((ushort)0x1000) 507#define UART_SCCM_GLT ((ushort)0x0800) 508#define UART_SCCM_AB ((ushort)0x0200) 509#define UART_SCCM_IDL ((ushort)0x0100) 510#define UART_SCCM_GRA ((ushort)0x0080) 511#define UART_SCCM_BRKE ((ushort)0x0040) 512#define UART_SCCM_BRKS ((ushort)0x0020) 513#define UART_SCCM_CCR ((ushort)0x0008) 514#define UART_SCCM_BSY ((ushort)0x0004) 515#define UART_SCCM_TX ((ushort)0x0002) 516#define UART_SCCM_RX ((ushort)0x0001) 517 518/* The SCC PMSR when used as a UART. 519*/ 520#define SCU_PSMR_FLC ((ushort)0x8000) 521#define SCU_PSMR_SL ((ushort)0x4000) 522#define SCU_PSMR_CL ((ushort)0x3000) 523#define SCU_PSMR_UM ((ushort)0x0c00) 524#define SCU_PSMR_FRZ ((ushort)0x0200) 525#define SCU_PSMR_RZS ((ushort)0x0100) 526#define SCU_PSMR_SYN ((ushort)0x0080) 527#define SCU_PSMR_DRT ((ushort)0x0040) 528#define SCU_PSMR_PEN ((ushort)0x0010) 529#define SCU_PSMR_RPM ((ushort)0x000c) 530#define SCU_PSMR_REVP ((ushort)0x0008) 531#define SCU_PSMR_TPM ((ushort)0x0003) 532#define SCU_PSMR_TEVP ((ushort)0x0002) 533 534/* CPM Transparent mode SCC. 535 */ 536typedef struct scc_trans { 537 sccp_t st_genscc; 538 uint st_cpres; /* Preset CRC */ 539 uint st_cmask; /* Constant mask for CRC */ 540} scc_trans_t; 541 542#define BD_SCC_TX_LAST ((ushort)0x0800) 543 544/* IIC parameter RAM. 545*/ 546typedef struct iic { 547 ushort iic_rbase; /* Rx Buffer descriptor base address */ 548 ushort iic_tbase; /* Tx Buffer descriptor base address */ 549 u_char iic_rfcr; /* Rx function code */ 550 u_char iic_tfcr; /* Tx function code */ 551 ushort iic_mrblr; /* Max receive buffer length */ 552 uint iic_rstate; /* Internal */ 553 uint iic_rdp; /* Internal */ 554 ushort iic_rbptr; /* Internal */ 555 ushort iic_rbc; /* Internal */ 556 uint iic_rxtmp; /* Internal */ 557 uint iic_tstate; /* Internal */ 558 uint iic_tdp; /* Internal */ 559 ushort iic_tbptr; /* Internal */ 560 ushort iic_tbc; /* Internal */ 561 uint iic_txtmp; /* Internal */ 562 char res1[4]; /* Reserved */ 563 ushort iic_rpbase; /* Relocation pointer */ 564 char res2[2]; /* Reserved */ 565} iic_t; 566 567#define BD_IIC_START ((ushort)0x0400) 568 569/* SPI parameter RAM. 570*/ 571typedef struct spi { 572 ushort spi_rbase; /* Rx Buffer descriptor base address */ 573 ushort spi_tbase; /* Tx Buffer descriptor base address */ 574 u_char spi_rfcr; /* Rx function code */ 575 u_char spi_tfcr; /* Tx function code */ 576 ushort spi_mrblr; /* Max receive buffer length */ 577 uint spi_rstate; /* Internal */ 578 uint spi_rdp; /* Internal */ 579 ushort spi_rbptr; /* Internal */ 580 ushort spi_rbc; /* Internal */ 581 uint spi_rxtmp; /* Internal */ 582 uint spi_tstate; /* Internal */ 583 uint spi_tdp; /* Internal */ 584 ushort spi_tbptr; /* Internal */ 585 ushort spi_tbc; /* Internal */ 586 uint spi_txtmp; /* Internal */ 587 uint spi_res; 588 ushort spi_rpbase; /* Relocation pointer */ 589 ushort spi_res2; 590} spi_t; 591 592/* SPI Mode register. 593*/ 594#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ 595#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ 596#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ 597#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ 598#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ 599#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ 600#define SPMODE_EN ((ushort)0x0100) /* Enable */ 601#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ 602#define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */ 603#define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */ 604#define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */ 605#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ 606 607/* SPIE fields */ 608#define SPIE_MME 0x20 609#define SPIE_TXE 0x10 610#define SPIE_BSY 0x04 611#define SPIE_TXB 0x02 612#define SPIE_RXB 0x01 613 614/* 615 * RISC Controller Configuration Register definitons 616 */ 617#define RCCR_TIME 0x8000 /* RISC Timer Enable */ 618#define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */ 619#define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */ 620 621/* RISC Timer Parameter RAM offset */ 622#define PROFF_RTMR ((uint)0x01B0) 623 624typedef struct risc_timer_pram { 625 unsigned short tm_base; /* RISC Timer Table Base Address */ 626 unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */ 627 unsigned short r_tmr; /* RISC Timer Mode Register */ 628 unsigned short r_tmv; /* RISC Timer Valid Register */ 629 unsigned long tm_cmd; /* RISC Timer Command Register */ 630 unsigned long tm_cnt; /* RISC Timer Internal Count */ 631} rt_pram_t; 632 633/* Bits in RISC Timer Command Register */ 634#define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */ 635#define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */ 636#define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */ 637#define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */ 638#define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */ 639 640/* CPM interrupts. There are nearly 32 interrupts generated by CPM 641 * channels or devices. All of these are presented to the PPC core 642 * as a single interrupt. The CPM interrupt handler dispatches its 643 * own handlers, in a similar fashion to the PPC core handler. We 644 * use the table as defined in the manuals (i.e. no special high 645 * priority and SCC1 == SCCa, etc...). 646 */ 647#define CPMVEC_NR 32 648#define CPMVEC_PIO_PC15 ((ushort)0x1f) 649#define CPMVEC_SCC1 ((ushort)0x1e) 650#define CPMVEC_SCC2 ((ushort)0x1d) 651#define CPMVEC_SCC3 ((ushort)0x1c) 652#define CPMVEC_SCC4 ((ushort)0x1b) 653#define CPMVEC_PIO_PC14 ((ushort)0x1a) 654#define CPMVEC_TIMER1 ((ushort)0x19) 655#define CPMVEC_PIO_PC13 ((ushort)0x18) 656#define CPMVEC_PIO_PC12 ((ushort)0x17) 657#define CPMVEC_SDMA_CB_ERR ((ushort)0x16) 658#define CPMVEC_IDMA1 ((ushort)0x15) 659#define CPMVEC_IDMA2 ((ushort)0x14) 660#define CPMVEC_TIMER2 ((ushort)0x12) 661#define CPMVEC_RISCTIMER ((ushort)0x11) 662#define CPMVEC_I2C ((ushort)0x10) 663#define CPMVEC_PIO_PC11 ((ushort)0x0f) 664#define CPMVEC_PIO_PC10 ((ushort)0x0e) 665#define CPMVEC_TIMER3 ((ushort)0x0c) 666#define CPMVEC_PIO_PC9 ((ushort)0x0b) 667#define CPMVEC_PIO_PC8 ((ushort)0x0a) 668#define CPMVEC_PIO_PC7 ((ushort)0x09) 669#define CPMVEC_TIMER4 ((ushort)0x07) 670#define CPMVEC_PIO_PC6 ((ushort)0x06) 671#define CPMVEC_SPI ((ushort)0x05) 672#define CPMVEC_SMC1 ((ushort)0x04) 673#define CPMVEC_SMC2 ((ushort)0x03) 674#define CPMVEC_PIO_PC5 ((ushort)0x02) 675#define CPMVEC_PIO_PC4 ((ushort)0x01) 676#define CPMVEC_ERROR ((ushort)0x00) 677 678/* CPM interrupt configuration vector. 679*/ 680#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ 681#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ 682#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ 683#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ 684#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ 685#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ 686#define CICR_IEN ((uint)0x00000080) /* Int. enable */ 687#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ 688 689extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); 690extern void cpm_free_handler(int vec); 691 692#endif /* __CPM_8XX__ */ 693