1/*
2 * common routine and memory layout for Tundra TSI108(Grendel) host bridge
3 * memory controller.
4 *
5 * Author: Jacob Pan (jacob.pan@freescale.com)
6 *	   Alex Bounine (alexandreb@tundra.com)
7 *
8 * Copyright 2004-2006 Freescale Semiconductor, Inc.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#ifndef __PPC_KERNEL_TSI108_H
17#define __PPC_KERNEL_TSI108_H
18
19#include <asm/pci-bridge.h>
20
21/* Size of entire register space */
22#define TSI108_REG_SIZE		(0x10000)
23
24/* Sizes of register spaces for individual blocks */
25#define TSI108_HLP_SIZE		0x1000
26#define TSI108_PCI_SIZE		0x1000
27#define TSI108_CLK_SIZE		0x1000
28#define TSI108_PB_SIZE		0x1000
29#define TSI108_SD_SIZE		0x1000
30#define TSI108_DMA_SIZE		0x1000
31#define TSI108_ETH_SIZE		0x1000
32#define TSI108_I2C_SIZE		0x400
33#define TSI108_MPIC_SIZE	0x400
34#define TSI108_UART0_SIZE	0x200
35#define TSI108_GPIO_SIZE	0x200
36#define TSI108_UART1_SIZE	0x200
37
38/* Offsets within Tsi108(A) CSR space for individual blocks */
39#define TSI108_HLP_OFFSET	0x0000
40#define TSI108_PCI_OFFSET	0x1000
41#define TSI108_CLK_OFFSET	0x2000
42#define TSI108_PB_OFFSET	0x3000
43#define TSI108_SD_OFFSET	0x4000
44#define TSI108_DMA_OFFSET	0x5000
45#define TSI108_ETH_OFFSET	0x6000
46#define TSI108_I2C_OFFSET	0x7000
47#define TSI108_MPIC_OFFSET	0x7400
48#define TSI108_UART0_OFFSET	0x7800
49#define TSI108_GPIO_OFFSET	0x7A00
50#define TSI108_UART1_OFFSET	0x7C00
51
52/* Tsi108 registers used by common code components */
53#define TSI108_PCI_CSR		(0x004)
54#define TSI108_PCI_IRP_CFG_CTL	(0x180)
55#define TSI108_PCI_IRP_STAT	(0x184)
56#define TSI108_PCI_IRP_ENABLE	(0x188)
57#define TSI108_PCI_IRP_INTAD	(0x18C)
58
59#define TSI108_PCI_IRP_STAT_P_INT	(0x00400000)
60#define TSI108_PCI_IRP_ENABLE_P_INT	(0x00400000)
61
62#define TSI108_CG_PWRUP_STATUS	(0x234)
63
64#define TSI108_PB_ISR		(0x00C)
65#define TSI108_PB_ERRCS		(0x404)
66#define TSI108_PB_AERR		(0x408)
67
68#define TSI108_PB_ERRCS_ES		(1 << 1)
69#define TSI108_PB_ISR_PBS_RD_ERR	(1 << 8)
70
71#define TSI108_PCI_CFG_SIZE		(0x01000000)
72
73/*
74 * PHY Configuration Options
75 *
76 * Specify "bcm54xx" in the compatible property of your device tree phy
77 * nodes if your board uses the Broadcom PHYs
78 */
79#define TSI108_PHY_MV88E	0	/* Marvel 88Exxxx PHY */
80#define TSI108_PHY_BCM54XX	1	/* Broardcom BCM54xx PHY */
81
82/* Global variables */
83
84extern u32 tsi108_pci_cfg_base;
85/* Exported functions */
86
87extern int tsi108_bridge_init(struct pci_controller *hose, uint phys_csr_base);
88extern unsigned long tsi108_get_mem_size(void);
89extern unsigned long tsi108_get_cpu_clk(void);
90extern unsigned long tsi108_get_sdc_clk(void);
91extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn,
92				      int offset, int len, u32 val);
93extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn,
94				     int offset, int len, u32 * val);
95extern void tsi108_clear_pci_error(u32 pci_cfg_base);
96
97extern phys_addr_t get_csrbase(void);
98
99typedef struct {
100	u32 regs;		/* hw registers base address */
101	u32 phyregs;		/* phy registers base address */
102	u16 phy;		/* phy address */
103	u16 irq_num;		/* irq number */
104	u8 mac_addr[6];		/* phy mac address */
105	u16 phy_type;	/* type of phy on board */
106} hw_info;
107
108extern u32 get_vir_csrbase(void);
109extern u32 tsi108_csr_vir_base;
110
111static inline u32 tsi108_read_reg(u32 reg_offset)
112{
113	return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
114}
115
116static inline void tsi108_write_reg(u32 reg_offset, u32 val)
117{
118	out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
119}
120
121#endif				/* __PPC_KERNEL_TSI108_H */
122