1#ifndef _ASM_POWERPC_MPIC_H
2#define _ASM_POWERPC_MPIC_H
3#ifdef __KERNEL__
4
5#include <linux/irq.h>
6#include <linux/sysdev.h>
7#include <asm/dcr.h>
8
9/*
10 * Global registers
11 */
12
13#define MPIC_GREG_BASE			0x01000
14
15#define MPIC_GREG_FEATURE_0		0x00000
16#define		MPIC_GREG_FEATURE_LAST_SRC_MASK		0x07ff0000
17#define		MPIC_GREG_FEATURE_LAST_SRC_SHIFT	16
18#define		MPIC_GREG_FEATURE_LAST_CPU_MASK		0x00001f00
19#define		MPIC_GREG_FEATURE_LAST_CPU_SHIFT	8
20#define		MPIC_GREG_FEATURE_VERSION_MASK		0xff
21#define MPIC_GREG_FEATURE_1		0x00010
22#define MPIC_GREG_GLOBAL_CONF_0		0x00020
23#define		MPIC_GREG_GCONF_RESET			0x80000000
24#define		MPIC_GREG_GCONF_8259_PTHROU_DIS		0x20000000
25#define		MPIC_GREG_GCONF_BASE_MASK		0x000fffff
26#define MPIC_GREG_GLOBAL_CONF_1		0x00030
27#define		MPIC_GREG_GLOBAL_CONF_1_SIE		0x08000000
28#define		MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK	0x70000000
29#define		MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r)	\
30			(((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
31#define MPIC_GREG_VENDOR_0		0x00040
32#define MPIC_GREG_VENDOR_1		0x00050
33#define MPIC_GREG_VENDOR_2		0x00060
34#define MPIC_GREG_VENDOR_3		0x00070
35#define MPIC_GREG_VENDOR_ID		0x00080
36#define 	MPIC_GREG_VENDOR_ID_STEPPING_MASK	0x00ff0000
37#define 	MPIC_GREG_VENDOR_ID_STEPPING_SHIFT	16
38#define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK	0x0000ff00
39#define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT	8
40#define 	MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK	0x000000ff
41#define MPIC_GREG_PROCESSOR_INIT	0x00090
42#define MPIC_GREG_IPI_VECTOR_PRI_0	0x000a0
43#define MPIC_GREG_IPI_VECTOR_PRI_1	0x000b0
44#define MPIC_GREG_IPI_VECTOR_PRI_2	0x000c0
45#define MPIC_GREG_IPI_VECTOR_PRI_3	0x000d0
46#define MPIC_GREG_IPI_STRIDE		0x10
47#define MPIC_GREG_SPURIOUS		0x000e0
48#define MPIC_GREG_TIMER_FREQ		0x000f0
49
50/*
51 *
52 * Timer registers
53 */
54#define MPIC_TIMER_BASE			0x01100
55#define MPIC_TIMER_STRIDE		0x40
56
57#define MPIC_TIMER_CURRENT_CNT		0x00000
58#define MPIC_TIMER_BASE_CNT		0x00010
59#define MPIC_TIMER_VECTOR_PRI		0x00020
60#define MPIC_TIMER_DESTINATION		0x00030
61
62/*
63 * Per-Processor registers
64 */
65
66#define MPIC_CPU_THISBASE		0x00000
67#define MPIC_CPU_BASE			0x20000
68#define MPIC_CPU_STRIDE			0x01000
69
70#define MPIC_CPU_IPI_DISPATCH_0		0x00040
71#define MPIC_CPU_IPI_DISPATCH_1		0x00050
72#define MPIC_CPU_IPI_DISPATCH_2		0x00060
73#define MPIC_CPU_IPI_DISPATCH_3		0x00070
74#define MPIC_CPU_IPI_DISPATCH_STRIDE	0x00010
75#define MPIC_CPU_CURRENT_TASK_PRI	0x00080
76#define 	MPIC_CPU_TASKPRI_MASK			0x0000000f
77#define MPIC_CPU_WHOAMI			0x00090
78#define 	MPIC_CPU_WHOAMI_MASK			0x0000001f
79#define MPIC_CPU_INTACK			0x000a0
80#define MPIC_CPU_EOI			0x000b0
81
82/*
83 * Per-source registers
84 */
85
86#define MPIC_IRQ_BASE			0x10000
87#define MPIC_IRQ_STRIDE			0x00020
88#define MPIC_IRQ_VECTOR_PRI		0x00000
89#define 	MPIC_VECPRI_MASK			0x80000000
90#define 	MPIC_VECPRI_ACTIVITY			0x40000000	/* Read Only */
91#define 	MPIC_VECPRI_PRIORITY_MASK		0x000f0000
92#define 	MPIC_VECPRI_PRIORITY_SHIFT		16
93#define 	MPIC_VECPRI_VECTOR_MASK			0x000007ff
94#define 	MPIC_VECPRI_POLARITY_POSITIVE		0x00800000
95#define 	MPIC_VECPRI_POLARITY_NEGATIVE		0x00000000
96#define 	MPIC_VECPRI_POLARITY_MASK		0x00800000
97#define 	MPIC_VECPRI_SENSE_LEVEL			0x00400000
98#define 	MPIC_VECPRI_SENSE_EDGE			0x00000000
99#define 	MPIC_VECPRI_SENSE_MASK			0x00400000
100#define MPIC_IRQ_DESTINATION		0x00010
101
102#define MPIC_MAX_IRQ_SOURCES	2048
103#define MPIC_MAX_CPUS		32
104#define MPIC_MAX_ISU		32
105
106/*
107 * Tsi108 implementation of MPIC has many differences from the original one
108 */
109
110/*
111 * Global registers
112 */
113
114#define TSI108_GREG_BASE		0x00000
115#define TSI108_GREG_FEATURE_0		0x00000
116#define TSI108_GREG_GLOBAL_CONF_0	0x00004
117#define TSI108_GREG_VENDOR_ID		0x0000c
118#define TSI108_GREG_IPI_VECTOR_PRI_0	0x00204		/* Doorbell 0 */
119#define TSI108_GREG_IPI_STRIDE		0x0c
120#define TSI108_GREG_SPURIOUS		0x00010
121#define TSI108_GREG_TIMER_FREQ		0x00014
122
123/*
124 * Timer registers
125 */
126#define TSI108_TIMER_BASE		0x0030
127#define TSI108_TIMER_STRIDE		0x10
128#define TSI108_TIMER_CURRENT_CNT	0x00000
129#define TSI108_TIMER_BASE_CNT		0x00004
130#define TSI108_TIMER_VECTOR_PRI		0x00008
131#define TSI108_TIMER_DESTINATION	0x0000c
132
133/*
134 * Per-Processor registers
135 */
136#define TSI108_CPU_BASE			0x00300
137#define TSI108_CPU_STRIDE		0x00040
138#define TSI108_CPU_IPI_DISPATCH_0	0x00200
139#define TSI108_CPU_IPI_DISPATCH_STRIDE	0x00000
140#define TSI108_CPU_CURRENT_TASK_PRI	0x00000
141#define TSI108_CPU_WHOAMI		0xffffffff
142#define TSI108_CPU_INTACK		0x00004
143#define TSI108_CPU_EOI			0x00008
144
145/*
146 * Per-source registers
147 */
148#define TSI108_IRQ_BASE			0x00100
149#define TSI108_IRQ_STRIDE		0x00008
150#define TSI108_IRQ_VECTOR_PRI		0x00000
151#define TSI108_VECPRI_VECTOR_MASK	0x000000ff
152#define TSI108_VECPRI_POLARITY_POSITIVE	0x01000000
153#define TSI108_VECPRI_POLARITY_NEGATIVE	0x00000000
154#define TSI108_VECPRI_SENSE_LEVEL	0x02000000
155#define TSI108_VECPRI_SENSE_EDGE	0x00000000
156#define TSI108_VECPRI_POLARITY_MASK	0x01000000
157#define TSI108_VECPRI_SENSE_MASK	0x02000000
158#define TSI108_IRQ_DESTINATION		0x00004
159
160/* weird mpic register indices and mask bits in the HW info array */
161enum {
162	MPIC_IDX_GREG_BASE = 0,
163	MPIC_IDX_GREG_FEATURE_0,
164	MPIC_IDX_GREG_GLOBAL_CONF_0,
165	MPIC_IDX_GREG_VENDOR_ID,
166	MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
167	MPIC_IDX_GREG_IPI_STRIDE,
168	MPIC_IDX_GREG_SPURIOUS,
169	MPIC_IDX_GREG_TIMER_FREQ,
170
171	MPIC_IDX_TIMER_BASE,
172	MPIC_IDX_TIMER_STRIDE,
173	MPIC_IDX_TIMER_CURRENT_CNT,
174	MPIC_IDX_TIMER_BASE_CNT,
175	MPIC_IDX_TIMER_VECTOR_PRI,
176	MPIC_IDX_TIMER_DESTINATION,
177
178	MPIC_IDX_CPU_BASE,
179	MPIC_IDX_CPU_STRIDE,
180	MPIC_IDX_CPU_IPI_DISPATCH_0,
181	MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
182	MPIC_IDX_CPU_CURRENT_TASK_PRI,
183	MPIC_IDX_CPU_WHOAMI,
184	MPIC_IDX_CPU_INTACK,
185	MPIC_IDX_CPU_EOI,
186
187	MPIC_IDX_IRQ_BASE,
188	MPIC_IDX_IRQ_STRIDE,
189	MPIC_IDX_IRQ_VECTOR_PRI,
190
191	MPIC_IDX_VECPRI_VECTOR_MASK,
192	MPIC_IDX_VECPRI_POLARITY_POSITIVE,
193	MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
194	MPIC_IDX_VECPRI_SENSE_LEVEL,
195	MPIC_IDX_VECPRI_SENSE_EDGE,
196	MPIC_IDX_VECPRI_POLARITY_MASK,
197	MPIC_IDX_VECPRI_SENSE_MASK,
198	MPIC_IDX_IRQ_DESTINATION,
199	MPIC_IDX_END
200};
201
202
203#ifdef CONFIG_MPIC_U3_HT_IRQS
204/* Fixup table entry */
205struct mpic_irq_fixup
206{
207	u8 __iomem	*base;
208	u8 __iomem	*applebase;
209	u32		data;
210	unsigned int	index;
211};
212#endif /* CONFIG_MPIC_U3_HT_IRQS */
213
214
215enum mpic_reg_type {
216	mpic_access_mmio_le,
217	mpic_access_mmio_be,
218#ifdef CONFIG_PPC_DCR
219	mpic_access_dcr
220#endif
221};
222
223struct mpic_reg_bank {
224	u32 __iomem	*base;
225#ifdef CONFIG_PPC_DCR
226	dcr_host_t	dhost;
227	unsigned int	dbase;
228	unsigned int	doff;
229#endif /* CONFIG_PPC_DCR */
230};
231
232struct mpic_irq_save {
233	u32		vecprio,
234			dest;
235#ifdef CONFIG_MPIC_U3_HT_IRQS
236	u32		fixup_data;
237#endif
238};
239
240/* The instance data of a given MPIC */
241struct mpic
242{
243	/* The device node of the interrupt controller */
244	struct device_node	*of_node;
245
246	/* The remapper for this MPIC */
247	struct irq_host		*irqhost;
248
249	/* The "linux" controller struct */
250	struct irq_chip		hc_irq;
251#ifdef CONFIG_MPIC_U3_HT_IRQS
252	struct irq_chip		hc_ht_irq;
253#endif
254#ifdef CONFIG_SMP
255	struct irq_chip		hc_ipi;
256#endif
257	const char		*name;
258	/* Flags */
259	unsigned int		flags;
260	/* How many irq sources in a given ISU */
261	unsigned int		isu_size;
262	unsigned int		isu_shift;
263	unsigned int		isu_mask;
264	unsigned int		irq_count;
265	/* Number of sources */
266	unsigned int		num_sources;
267	/* Number of CPUs */
268	unsigned int		num_cpus;
269	/* default senses array */
270	unsigned char		*senses;
271	unsigned int		senses_count;
272
273	/* vector numbers used for internal sources (ipi/timers) */
274	unsigned int		ipi_vecs[4];
275	unsigned int		timer_vecs[4];
276
277	/* Spurious vector to program into unused sources */
278	unsigned int		spurious_vec;
279
280#ifdef CONFIG_MPIC_U3_HT_IRQS
281	/* The fixup table */
282	struct mpic_irq_fixup	*fixups;
283	spinlock_t		fixup_lock;
284#endif
285
286	/* Register access method */
287	enum mpic_reg_type	reg_type;
288
289	/* The various ioremap'ed bases */
290	struct mpic_reg_bank	gregs;
291	struct mpic_reg_bank	tmregs;
292	struct mpic_reg_bank	cpuregs[MPIC_MAX_CPUS];
293	struct mpic_reg_bank	isus[MPIC_MAX_ISU];
294
295#ifdef CONFIG_PPC_DCR
296	unsigned int		dcr_base;
297#endif
298
299#ifdef CONFIG_MPIC_WEIRD
300	/* Pointer to HW info array */
301	u32			*hw_set;
302#endif
303
304#ifdef CONFIG_PCI_MSI
305	spinlock_t		bitmap_lock;
306	unsigned long		*hwirq_bitmap;
307#endif
308
309	/* link */
310	struct mpic		*next;
311
312	struct sys_device	sysdev;
313
314#ifdef CONFIG_PM
315	struct mpic_irq_save	*save_data;
316#endif
317};
318
319/*
320 * MPIC flags (passed to mpic_alloc)
321 *
322 * The top 4 bits contain an MPIC bhw id that is used to index the
323 * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
324 * Note setting any ID (leaving those bits to 0) means standard MPIC
325 */
326
327/* This is the primary controller, only that one has IPIs and
328 * has afinity control. A non-primary MPIC always uses CPU0
329 * registers only
330 */
331#define MPIC_PRIMARY			0x00000001
332
333/* Set this for a big-endian MPIC */
334#define MPIC_BIG_ENDIAN			0x00000002
335/* Broken U3 MPIC */
336#define MPIC_U3_HT_IRQS			0x00000004
337/* Broken IPI registers (autodetected) */
338#define MPIC_BROKEN_IPI			0x00000008
339/* MPIC wants a reset */
340#define MPIC_WANTS_RESET		0x00000010
341/* Spurious vector requires EOI */
342#define MPIC_SPV_EOI			0x00000020
343/* No passthrough disable */
344#define MPIC_NO_PTHROU_DIS		0x00000040
345/* DCR based MPIC */
346#define MPIC_USES_DCR			0x00000080
347/* MPIC has 11-bit vector fields (or larger) */
348#define MPIC_LARGE_VECTORS		0x00000100
349
350/* MPIC HW modification ID */
351#define MPIC_REGSET_MASK		0xf0000000
352#define MPIC_REGSET(val)		(((val) & 0xf ) << 28)
353#define MPIC_GET_REGSET(flags)		(((flags) >> 28) & 0xf)
354
355#define	MPIC_REGSET_STANDARD		MPIC_REGSET(0)	/* Original MPIC */
356#define	MPIC_REGSET_TSI108		MPIC_REGSET(1)	/* Tsi108/109 PIC */
357
358/* Allocate the controller structure and setup the linux irq descs
359 * for the range if interrupts passed in. No HW initialization is
360 * actually performed.
361 *
362 * @phys_addr:	physial base address of the MPIC
363 * @flags:	flags, see constants above
364 * @isu_size:	number of interrupts in an ISU. Use 0 to use a
365 *              standard ISU-less setup (aka powermac)
366 * @irq_offset: first irq number to assign to this mpic
367 * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
368 *	        to match the number of sources
369 * @ipi_offset: first irq number to assign to this mpic IPI sources,
370 *		used only on primary mpic
371 * @senses:	array of sense values
372 * @senses_num: number of entries in the array
373 *
374 * Note about the sense array. If none is passed, all interrupts are
375 * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
376 * case they are edge positive (and the array is ignored anyway).
377 * The values in the array start at the first source of the MPIC,
378 * that is senses[0] correspond to linux irq "irq_offset".
379 */
380extern struct mpic *mpic_alloc(struct device_node *node,
381			       phys_addr_t phys_addr,
382			       unsigned int flags,
383			       unsigned int isu_size,
384			       unsigned int irq_count,
385			       const char *name);
386
387/* Assign ISUs, to call before mpic_init()
388 *
389 * @mpic:	controller structure as returned by mpic_alloc()
390 * @isu_num:	ISU number
391 * @phys_addr:	physical address of the ISU
392 */
393extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
394			    phys_addr_t phys_addr);
395
396/* Set default sense codes
397 *
398 * @mpic:	controller
399 * @senses:	array of sense codes
400 * @count:	size of above array
401 *
402 * Optionally provide an array (indexed on hardware interrupt numbers
403 * for this MPIC) of default sense codes for the chip. Those are linux
404 * sense codes IRQ_TYPE_*
405 *
406 * The driver gets ownership of the pointer, don't dispose of it or
407 * anything like that. __init only.
408 */
409extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
410
411
412/* Initialize the controller. After this has been called, none of the above
413 * should be called again for this mpic
414 */
415extern void mpic_init(struct mpic *mpic);
416
417/*
418 * All of the following functions must only be used after the
419 * ISUs have been assigned and the controller fully initialized
420 * with mpic_init()
421 */
422
423
424/* Change/Read the priority of an interrupt. Default is 8 for irqs and
425 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
426 * IPI number is then the offset'ed (linux irq number mapped to the IPI)
427 */
428extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
429extern unsigned int mpic_irq_get_priority(unsigned int irq);
430
431/* Setup a non-boot CPU */
432extern void mpic_setup_this_cpu(void);
433
434/* Clean up for kexec (or cpu offline or ...) */
435extern void mpic_teardown_this_cpu(int secondary);
436
437/* Get the current cpu priority for this cpu (0..15) */
438extern int mpic_cpu_get_priority(void);
439
440/* Set the current cpu priority for this cpu */
441extern void mpic_cpu_set_priority(int prio);
442
443/* Request IPIs on primary mpic */
444extern void mpic_request_ipis(void);
445
446/* Send an IPI (non offseted number 0..3) */
447extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
448
449/* Send a message (IPI) to a given target (cpu number or MSG_*) */
450void smp_mpic_message_pass(int target, int msg);
451
452/* Fetch interrupt from a given mpic */
453extern unsigned int mpic_get_one_irq(struct mpic *mpic);
454/* This one gets to the primary mpic */
455extern unsigned int mpic_get_irq(void);
456
457/* Set the EPIC clock ratio */
458void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
459
460/* Enable/Disable EPIC serial interrupt mode */
461void mpic_set_serial_int(struct mpic *mpic, int enable);
462
463#endif /* __KERNEL__ */
464#endif	/* _ASM_POWERPC_MPIC_H */
465