1/* 2 * Copyright (C) 2001 Mike Corrigan IBM Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18#ifndef _ASM_POWERPC_ISERIES_LPAR_MAP_H 19#define _ASM_POWERPC_ISERIES_LPAR_MAP_H 20 21#ifndef __ASSEMBLY__ 22 23#include <asm/types.h> 24 25/* 26 * The iSeries hypervisor will set up mapping for one or more 27 * ESID/VSID pairs (in SLB/segment registers) and will set up 28 * mappings of one or more ranges of pages to VAs. 29 * We will have the hypervisor set up the ESID->VSID mapping 30 * for the four kernel segments (C-F). With shared processors, 31 * the hypervisor will clear all segment registers and reload 32 * these four whenever the processor is switched from one 33 * partition to another. 34 */ 35 36/* The Vsid and Esid identified below will be used by the hypervisor 37 * to set up a memory mapping for part of the load area before giving 38 * control to the Linux kernel. The load area is 64 MB, but this must 39 * not attempt to map the whole load area. The Hashed Page Table may 40 * need to be located within the load area (if the total partition size 41 * is 64 MB), but cannot be mapped. Typically, this should specify 42 * to map half (32 MB) of the load area. 43 * 44 * The hypervisor will set up page table entries for the number of 45 * pages specified. 46 * 47 * In 32-bit mode, the hypervisor will load all four of the 48 * segment registers (identified by the low-order four bits of the 49 * Esid field. In 64-bit mode, the hypervisor will load one SLB 50 * entry to map the Esid to the Vsid. 51*/ 52 53#define HvEsidsToMap 2 54#define HvRangesToMap 1 55 56/* Hypervisor initially maps 32MB of the load area */ 57#define HvPagesToMap 8192 58 59struct LparMap { 60 u64 xNumberEsids; // Number of ESID/VSID pairs 61 u64 xNumberRanges; // Number of VA ranges to map 62 u64 xSegmentTableOffs; // Page number within load area of seg table 63 u64 xRsvd[5]; 64 struct { 65 u64 xKernelEsid; // Esid used to map kernel load 66 u64 xKernelVsid; // Vsid used to map kernel load 67 } xEsids[HvEsidsToMap]; 68 struct { 69 u64 xPages; // Number of pages to be mapped 70 u64 xOffset; // Offset from start of load area 71 u64 xVPN; // Virtual Page Number 72 } xRanges[HvRangesToMap]; 73}; 74 75extern const struct LparMap xLparMap; 76 77#endif /* __ASSEMBLY__ */ 78 79/* the fixed address where the LparMap exists */ 80#define LPARMAP_PHYS 0x7000 81 82#endif /* _ASM_POWERPC_ISERIES_LPAR_MAP_H */ 83