1#ifndef _ASM_POWERPC_IO_H 2#define _ASM_POWERPC_IO_H 3#ifdef __KERNEL__ 4 5/* 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12/* Check of existence of legacy devices */ 13extern int check_legacy_ioport(unsigned long base_port); 14#define I8042_DATA_REG 0x60 15#define FDC_BASE 0x3f0 16/* only relevant for PReP */ 17#define _PIDXR 0x279 18#define _PNPWRP 0xa79 19#define PNPBIOS_BASE 0xf000 20 21#include <linux/compiler.h> 22#include <asm/page.h> 23#include <asm/byteorder.h> 24#include <asm/synch.h> 25#include <asm/delay.h> 26#include <asm/mmu.h> 27 28#include <asm-generic/iomap.h> 29 30#ifdef CONFIG_PPC64 31#include <asm/paca.h> 32#endif 33 34#define SIO_CONFIG_RA 0x398 35#define SIO_CONFIG_RD 0x399 36 37#define SLOW_DOWN_IO 38 39/* 32 bits uses slightly different variables for the various IO 40 * bases. Most of this file only uses _IO_BASE though which we 41 * define properly based on the platform 42 */ 43#ifndef CONFIG_PCI 44#define _IO_BASE 0 45#define _ISA_MEM_BASE 0 46#define PCI_DRAM_OFFSET 0 47#elif defined(CONFIG_PPC32) 48#define _IO_BASE isa_io_base 49#define _ISA_MEM_BASE isa_mem_base 50#define PCI_DRAM_OFFSET pci_dram_offset 51#else 52#define _IO_BASE pci_io_base 53#define _ISA_MEM_BASE 0 54#define PCI_DRAM_OFFSET 0 55#endif 56 57extern unsigned long isa_io_base; 58extern unsigned long isa_mem_base; 59extern unsigned long pci_io_base; 60extern unsigned long pci_dram_offset; 61 62#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO) 63#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits 64#endif 65 66/* 67 * 68 * Low level MMIO accessors 69 * 70 * This provides the non-bus specific accessors to MMIO. Those are PowerPC 71 * specific and thus shouldn't be used in generic code. The accessors 72 * provided here are: 73 * 74 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64 75 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64 76 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns 77 * 78 * Those operate directly on a kernel virtual address. Note that the prototype 79 * for the out_* accessors has the arguments in opposite order from the usual 80 * linux PCI accessors. Unlike those, they take the address first and the value 81 * next. 82 * 83 * Note: I might drop the _ns suffix on the stream operations soon as it is 84 * simply normal for stream operations to not swap in the first place. 85 * 86 */ 87 88#ifdef CONFIG_PPC64 89#define IO_SET_SYNC_FLAG() do { get_paca()->io_sync = 1; } while(0) 90#else 91#define IO_SET_SYNC_FLAG() 92#endif 93 94#define DEF_MMIO_IN(name, type, insn) \ 95static inline type name(const volatile type __iomem *addr) \ 96{ \ 97 type ret; \ 98 __asm__ __volatile__("sync;" insn ";twi 0,%0,0;isync" \ 99 : "=r" (ret) : "r" (addr), "m" (*addr)); \ 100 return ret; \ 101} 102 103#define DEF_MMIO_OUT(name, type, insn) \ 104static inline void name(volatile type __iomem *addr, type val) \ 105{ \ 106 __asm__ __volatile__("sync;" insn \ 107 : "=m" (*addr) : "r" (val), "r" (addr)); \ 108 IO_SET_SYNC_FLAG(); \ 109} 110 111 112#define DEF_MMIO_IN_BE(name, size, insn) \ 113 DEF_MMIO_IN(name, u##size, __stringify(insn)"%U2%X2 %0,%2") 114#define DEF_MMIO_IN_LE(name, size, insn) \ 115 DEF_MMIO_IN(name, u##size, __stringify(insn)" %0,0,%1") 116 117#define DEF_MMIO_OUT_BE(name, size, insn) \ 118 DEF_MMIO_OUT(name, u##size, __stringify(insn)"%U0%X0 %1,%0") 119#define DEF_MMIO_OUT_LE(name, size, insn) \ 120 DEF_MMIO_OUT(name, u##size, __stringify(insn)" %1,0,%2") 121 122DEF_MMIO_IN_BE(in_8, 8, lbz); 123DEF_MMIO_IN_BE(in_be16, 16, lhz); 124DEF_MMIO_IN_BE(in_be32, 32, lwz); 125DEF_MMIO_IN_LE(in_le16, 16, lhbrx); 126DEF_MMIO_IN_LE(in_le32, 32, lwbrx); 127 128DEF_MMIO_OUT_BE(out_8, 8, stb); 129DEF_MMIO_OUT_BE(out_be16, 16, sth); 130DEF_MMIO_OUT_BE(out_be32, 32, stw); 131DEF_MMIO_OUT_LE(out_le16, 16, sthbrx); 132DEF_MMIO_OUT_LE(out_le32, 32, stwbrx); 133 134#ifdef __powerpc64__ 135DEF_MMIO_OUT_BE(out_be64, 64, std); 136DEF_MMIO_IN_BE(in_be64, 64, ld); 137 138/* There is no asm instructions for 64 bits reverse loads and stores */ 139static inline u64 in_le64(const volatile u64 __iomem *addr) 140{ 141 return le64_to_cpu(in_be64(addr)); 142} 143 144static inline void out_le64(volatile u64 __iomem *addr, u64 val) 145{ 146 out_be64(addr, cpu_to_le64(val)); 147} 148#endif /* __powerpc64__ */ 149 150/* 151 * Low level IO stream instructions are defined out of line for now 152 */ 153extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); 154extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); 155extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); 156extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); 157extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); 158extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); 159 160/* The _ns naming is historical and will be removed. For now, just #define 161 * the non _ns equivalent names 162 */ 163#define _insw _insw_ns 164#define _insl _insl_ns 165#define _outsw _outsw_ns 166#define _outsl _outsl_ns 167 168 169/* 170 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line 171 */ 172 173extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n); 174extern void _memcpy_fromio(void *dest, const volatile void __iomem *src, 175 unsigned long n); 176extern void _memcpy_toio(volatile void __iomem *dest, const void *src, 177 unsigned long n); 178 179/* 180 * 181 * PCI and standard ISA accessors 182 * 183 * Those are globally defined linux accessors for devices on PCI or ISA 184 * busses. They follow the Linux defined semantics. The current implementation 185 * for PowerPC is as close as possible to the x86 version of these, and thus 186 * provides fairly heavy weight barriers for the non-raw versions 187 * 188 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO 189 * allowing the platform to provide its own implementation of some or all 190 * of the accessors. 191 */ 192 193/* 194 * Include the EEH definitions when EEH is enabled only so they don't get 195 * in the way when building for 32 bits 196 */ 197#ifdef CONFIG_EEH 198#include <asm/eeh.h> 199#endif 200 201/* Shortcut to the MMIO argument pointer */ 202#define PCI_IO_ADDR volatile void __iomem * 203 204/* Indirect IO address tokens: 205 * 206 * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks 207 * on all IOs. (Note that this is all 64 bits only for now) 208 * 209 * To help platforms who may need to differenciate MMIO addresses in 210 * their hooks, a bitfield is reserved for use by the platform near the 211 * top of MMIO addresses (not PIO, those have to cope the hard way). 212 * 213 * This bit field is 12 bits and is at the top of the IO virtual 214 * addresses PCI_IO_INDIRECT_TOKEN_MASK. 215 * 216 * The kernel virtual space is thus: 217 * 218 * 0xD000000000000000 : vmalloc 219 * 0xD000080000000000 : PCI PHB IO space 220 * 0xD000080080000000 : ioremap 221 * 0xD0000fffffffffff : end of ioremap region 222 * 223 * Since the top 4 bits are reserved as the region ID, we use thus 224 * the next 12 bits and keep 4 bits available for the future if the 225 * virtual address space is ever to be extended. 226 * 227 * The direct IO mapping operations will then mask off those bits 228 * before doing the actual access, though that only happen when 229 * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that 230 * mechanism 231 */ 232 233#ifdef CONFIG_PPC_INDIRECT_IO 234#define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul 235#define PCI_IO_IND_TOKEN_SHIFT 48 236#define PCI_FIX_ADDR(addr) \ 237 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK)) 238#define PCI_GET_ADDR_TOKEN(addr) \ 239 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \ 240 PCI_IO_IND_TOKEN_SHIFT) 241#define PCI_SET_ADDR_TOKEN(addr, token) \ 242do { \ 243 unsigned long __a = (unsigned long)(addr); \ 244 __a &= ~PCI_IO_IND_TOKEN_MASK; \ 245 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \ 246 (addr) = (void __iomem *)__a; \ 247} while(0) 248#else 249#define PCI_FIX_ADDR(addr) (addr) 250#endif 251 252 253/* 254 * Non ordered and non-swapping "raw" accessors 255 */ 256 257static inline unsigned char __raw_readb(const volatile void __iomem *addr) 258{ 259 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr); 260} 261static inline unsigned short __raw_readw(const volatile void __iomem *addr) 262{ 263 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr); 264} 265static inline unsigned int __raw_readl(const volatile void __iomem *addr) 266{ 267 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr); 268} 269static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) 270{ 271 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v; 272} 273static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) 274{ 275 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v; 276} 277static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) 278{ 279 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v; 280} 281 282#ifdef __powerpc64__ 283static inline unsigned long __raw_readq(const volatile void __iomem *addr) 284{ 285 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr); 286} 287static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) 288{ 289 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v; 290} 291#endif /* __powerpc64__ */ 292 293/* 294 * 295 * PCI PIO and MMIO accessors. 296 * 297 * 298 * On 32 bits, PIO operations have a recovery mechanism in case they trigger 299 * machine checks (which they occasionally do when probing non existing 300 * IO ports on some platforms, like PowerMac and 8xx). 301 * I always found it to be of dubious reliability and I am tempted to get 302 * rid of it one of these days. So if you think it's important to keep it, 303 * please voice up asap. We never had it for 64 bits and I do not intend 304 * to port it over 305 */ 306 307#ifdef CONFIG_PPC32 308 309#define __do_in_asm(name, op) \ 310static inline unsigned int name(unsigned int port) \ 311{ \ 312 unsigned int x; \ 313 __asm__ __volatile__( \ 314 "sync\n" \ 315 "0:" op " %0,0,%1\n" \ 316 "1: twi 0,%0,0\n" \ 317 "2: isync\n" \ 318 "3: nop\n" \ 319 "4:\n" \ 320 ".section .fixup,\"ax\"\n" \ 321 "5: li %0,-1\n" \ 322 " b 4b\n" \ 323 ".previous\n" \ 324 ".section __ex_table,\"a\"\n" \ 325 " .align 2\n" \ 326 " .long 0b,5b\n" \ 327 " .long 1b,5b\n" \ 328 " .long 2b,5b\n" \ 329 " .long 3b,5b\n" \ 330 ".previous" \ 331 : "=&r" (x) \ 332 : "r" (port + _IO_BASE)); \ 333 return x; \ 334} 335 336#define __do_out_asm(name, op) \ 337static inline void name(unsigned int val, unsigned int port) \ 338{ \ 339 __asm__ __volatile__( \ 340 "sync\n" \ 341 "0:" op " %0,0,%1\n" \ 342 "1: sync\n" \ 343 "2:\n" \ 344 ".section __ex_table,\"a\"\n" \ 345 " .align 2\n" \ 346 " .long 0b,2b\n" \ 347 " .long 1b,2b\n" \ 348 ".previous" \ 349 : : "r" (val), "r" (port + _IO_BASE)); \ 350} 351 352__do_in_asm(_rec_inb, "lbzx") 353__do_in_asm(_rec_inw, "lhbrx") 354__do_in_asm(_rec_inl, "lwbrx") 355__do_out_asm(_rec_outb, "stbx") 356__do_out_asm(_rec_outw, "sthbrx") 357__do_out_asm(_rec_outl, "stwbrx") 358 359#endif /* CONFIG_PPC32 */ 360 361/* The "__do_*" operations below provide the actual "base" implementation 362 * for each of the defined acccessor. Some of them use the out_* functions 363 * directly, some of them still use EEH, though we might change that in the 364 * future. Those macros below provide the necessary argument swapping and 365 * handling of the IO base for PIO. 366 * 367 * They are themselves used by the macros that define the actual accessors 368 * and can be used by the hooks if any. 369 * 370 * Note that PIO operations are always defined in terms of their corresonding 371 * MMIO operations. That allows platforms like iSeries who want to modify the 372 * behaviour of both to only hook on the MMIO version and get both. It's also 373 * possible to hook directly at the toplevel PIO operation if they have to 374 * be handled differently 375 */ 376#define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val) 377#define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val) 378#define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val) 379#define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val) 380#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val) 381#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val) 382#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val) 383 384#ifdef CONFIG_EEH 385#define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr)) 386#define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr)) 387#define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr)) 388#define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr)) 389#define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr)) 390#define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr)) 391#define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr)) 392#else /* CONFIG_EEH */ 393#define __do_readb(addr) in_8(PCI_FIX_ADDR(addr)) 394#define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr)) 395#define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr)) 396#define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr)) 397#define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr)) 398#define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr)) 399#define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr)) 400#endif /* !defined(CONFIG_EEH) */ 401 402#ifdef CONFIG_PPC32 403#define __do_outb(val, port) _rec_outb(val, port) 404#define __do_outw(val, port) _rec_outw(val, port) 405#define __do_outl(val, port) _rec_outl(val, port) 406#define __do_inb(port) _rec_inb(port) 407#define __do_inw(port) _rec_inw(port) 408#define __do_inl(port) _rec_inl(port) 409#else /* CONFIG_PPC32 */ 410#define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port); 411#define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port); 412#define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port); 413#define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); 414#define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port); 415#define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port); 416#endif /* !CONFIG_PPC32 */ 417 418#ifdef CONFIG_EEH 419#define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n)) 420#define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n)) 421#define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n)) 422#else /* CONFIG_EEH */ 423#define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n)) 424#define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n)) 425#define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n)) 426#endif /* !CONFIG_EEH */ 427#define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n)) 428#define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n)) 429#define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n)) 430 431#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 432#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 433#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 434#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 435#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 436#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 437 438#define __do_memset_io(addr, c, n) \ 439 _memset_io(PCI_FIX_ADDR(addr), c, n) 440#define __do_memcpy_toio(dst, src, n) \ 441 _memcpy_toio(PCI_FIX_ADDR(dst), src, n) 442 443#ifdef CONFIG_EEH 444#define __do_memcpy_fromio(dst, src, n) \ 445 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n) 446#else /* CONFIG_EEH */ 447#define __do_memcpy_fromio(dst, src, n) \ 448 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n) 449#endif /* !CONFIG_EEH */ 450 451#ifdef CONFIG_PPC_INDIRECT_IO 452#define DEF_PCI_HOOK(x) x 453#else 454#define DEF_PCI_HOOK(x) NULL 455#endif 456 457/* Structure containing all the hooks */ 458extern struct ppc_pci_io { 459 460#define DEF_PCI_AC_RET(name, ret, at, al) ret (*name) at; 461#define DEF_PCI_AC_NORET(name, at, al) void (*name) at; 462 463#include <asm/io-defs.h> 464 465#undef DEF_PCI_AC_RET 466#undef DEF_PCI_AC_NORET 467 468} ppc_pci_io; 469 470/* The inline wrappers */ 471#define DEF_PCI_AC_RET(name, ret, at, al) \ 472static inline ret name at \ 473{ \ 474 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \ 475 return ppc_pci_io.name al; \ 476 return __do_##name al; \ 477} 478 479#define DEF_PCI_AC_NORET(name, at, al) \ 480static inline void name at \ 481{ \ 482 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \ 483 ppc_pci_io.name al; \ 484 else \ 485 __do_##name al; \ 486} 487 488#include <asm/io-defs.h> 489 490#undef DEF_PCI_AC_RET 491#undef DEF_PCI_AC_NORET 492 493/* Some drivers check for the presence of readq & writeq with 494 * a #ifdef, so we make them happy here. 495 */ 496#ifdef __powerpc64__ 497#define readq readq 498#define writeq writeq 499#endif 500 501#ifdef CONFIG_NOT_COHERENT_CACHE 502 503#define dma_cache_inv(_start,_size) \ 504 invalidate_dcache_range(_start, (_start + _size)) 505#define dma_cache_wback(_start,_size) \ 506 clean_dcache_range(_start, (_start + _size)) 507#define dma_cache_wback_inv(_start,_size) \ 508 flush_dcache_range(_start, (_start + _size)) 509 510#else /* CONFIG_NOT_COHERENT_CACHE */ 511 512#define dma_cache_inv(_start,_size) do { } while (0) 513#define dma_cache_wback(_start,_size) do { } while (0) 514#define dma_cache_wback_inv(_start,_size) do { } while (0) 515 516#endif /* !CONFIG_NOT_COHERENT_CACHE */ 517 518/* 519 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 520 * access 521 */ 522#define xlate_dev_mem_ptr(p) __va(p) 523 524/* 525 * Convert a virtual cached pointer to an uncached pointer 526 */ 527#define xlate_dev_kmem_ptr(p) p 528 529/* 530 * We don't do relaxed operations yet, at least not with this semantic 531 */ 532#define readb_relaxed(addr) readb(addr) 533#define readw_relaxed(addr) readw(addr) 534#define readl_relaxed(addr) readl(addr) 535#define readq_relaxed(addr) readq(addr) 536 537#ifdef CONFIG_PPC32 538#define mmiowb() 539#else 540/* 541 * Enforce synchronisation of stores vs. spin_unlock 542 * (this does it explicitely, though our implementation of spin_unlock 543 * does it implicitely too) 544 */ 545static inline void mmiowb(void) 546{ 547 unsigned long tmp; 548 549 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)" 550 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync)) 551 : "memory"); 552} 553#endif /* !CONFIG_PPC32 */ 554 555static inline void iosync(void) 556{ 557 __asm__ __volatile__ ("sync" : : : "memory"); 558} 559 560/* Enforce in-order execution of data I/O. 561 * No distinction between read/write on PPC; use eieio for all three. 562 * Those are fairly week though. They don't provide a barrier between 563 * MMIO and cacheable storage nor do they provide a barrier vs. locks, 564 * they only provide barriers between 2 __raw MMIO operations and 565 * possibly break write combining. 566 */ 567#define iobarrier_rw() eieio() 568#define iobarrier_r() eieio() 569#define iobarrier_w() eieio() 570 571 572/* 573 * output pause versions need a delay at least for the 574 * w83c105 ide controller in a p610. 575 */ 576#define inb_p(port) inb(port) 577#define outb_p(val, port) (udelay(1), outb((val), (port))) 578#define inw_p(port) inw(port) 579#define outw_p(val, port) (udelay(1), outw((val), (port))) 580#define inl_p(port) inl(port) 581#define outl_p(val, port) (udelay(1), outl((val), (port))) 582 583 584#define IO_SPACE_LIMIT ~(0UL) 585 586 587/** 588 * ioremap - map bus memory into CPU space 589 * @address: bus address of the memory 590 * @size: size of the resource to map 591 * 592 * ioremap performs a platform specific sequence of operations to 593 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 594 * writew/writel functions and the other mmio helpers. The returned 595 * address is not guaranteed to be usable directly as a virtual 596 * address. 597 * 598 * We provide a few variations of it: 599 * 600 * * ioremap is the standard one and provides non-cacheable guarded mappings 601 * and can be hooked by the platform via ppc_md 602 * 603 * * ioremap_flags allows to specify the page flags as an argument and can 604 * also be hooked by the platform via ppc_md 605 * 606 * * ioremap_nocache is identical to ioremap 607 * 608 * * iounmap undoes such a mapping and can be hooked 609 * 610 * * __ioremap_explicit (and the pending __iounmap_explicit) are low level 611 * functions to create hand-made mappings for use only by the PCI code 612 * and cannot currently be hooked. 613 * 614 * * __ioremap is the low level implementation used by ioremap and 615 * ioremap_flags and cannot be hooked (but can be used by a hook on one 616 * of the previous ones) 617 * 618 * * __iounmap, is the low level implementation used by iounmap and cannot 619 * be hooked (but can be used by a hook on iounmap) 620 * 621 */ 622extern void __iomem *ioremap(phys_addr_t address, unsigned long size); 623extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size, 624 unsigned long flags); 625#define ioremap_nocache(addr, size) ioremap((addr), (size)) 626extern void iounmap(volatile void __iomem *addr); 627 628extern void __iomem *__ioremap(phys_addr_t, unsigned long size, 629 unsigned long flags); 630extern void __iounmap(volatile void __iomem *addr); 631 632extern int __ioremap_explicit(phys_addr_t p_addr, unsigned long v_addr, 633 unsigned long size, unsigned long flags); 634extern int __iounmap_explicit(volatile void __iomem *start, 635 unsigned long size); 636 637extern void __iomem * reserve_phb_iospace(unsigned long size); 638 639/* Those are more 32 bits only functions */ 640extern unsigned long iopa(unsigned long addr); 641extern unsigned long mm_ptov(unsigned long addr) __attribute_const__; 642extern void io_block_mapping(unsigned long virt, phys_addr_t phys, 643 unsigned int size, int flags); 644 645 646/* 647 * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation 648 * which needs some additional definitions here. They basically allow PIO 649 * space overall to be 1GB. This will work as long as we never try to use 650 * iomap to map MMIO below 1GB which should be fine on ppc64 651 */ 652#define HAVE_ARCH_PIO_SIZE 1 653#define PIO_OFFSET 0x00000000UL 654#define PIO_MASK 0x3fffffffUL 655#define PIO_RESERVED 0x40000000UL 656 657#define mmio_read16be(addr) readw_be(addr) 658#define mmio_read32be(addr) readl_be(addr) 659#define mmio_write16be(val, addr) writew_be(val, addr) 660#define mmio_write32be(val, addr) writel_be(val, addr) 661#define mmio_insb(addr, dst, count) readsb(addr, dst, count) 662#define mmio_insw(addr, dst, count) readsw(addr, dst, count) 663#define mmio_insl(addr, dst, count) readsl(addr, dst, count) 664#define mmio_outsb(addr, src, count) writesb(addr, src, count) 665#define mmio_outsw(addr, src, count) writesw(addr, src, count) 666#define mmio_outsl(addr, src, count) writesl(addr, src, count) 667 668/** 669 * virt_to_phys - map virtual addresses to physical 670 * @address: address to remap 671 * 672 * The returned physical address is the physical (CPU) mapping for 673 * the memory address given. It is only valid to use this function on 674 * addresses directly mapped or allocated via kmalloc. 675 * 676 * This function does not give bus mappings for DMA transfers. In 677 * almost all conceivable cases a device driver should not be using 678 * this function 679 */ 680static inline unsigned long virt_to_phys(volatile void * address) 681{ 682 return __pa((unsigned long)address); 683} 684 685/** 686 * phys_to_virt - map physical address to virtual 687 * @address: address to remap 688 * 689 * The returned virtual address is a current CPU mapping for 690 * the memory address given. It is only valid to use this function on 691 * addresses that have a kernel mapping 692 * 693 * This function does not handle bus mappings for DMA transfers. In 694 * almost all conceivable cases a device driver should not be using 695 * this function 696 */ 697static inline void * phys_to_virt(unsigned long address) 698{ 699 return (void *)__va(address); 700} 701 702/* 703 * Change "struct page" to physical address. 704 */ 705#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) 706 707/* We do NOT want virtual merging, it would put too much pressure on 708 * our iommu allocator. Instead, we want drivers to be smart enough 709 * to coalesce sglists that happen to have been mapped in a contiguous 710 * way by the iommu 711 */ 712#define BIO_VMERGE_BOUNDARY 0 713 714/* 715 * 32 bits still uses virt_to_bus() for it's implementation of DMA 716 * mappings se we have to keep it defined here. We also have some old 717 * drivers (shame shame shame) that use bus_to_virt() and haven't been 718 * fixed yet so I need to define it here. 719 */ 720#ifdef CONFIG_PPC32 721 722static inline unsigned long virt_to_bus(volatile void * address) 723{ 724 if (address == NULL) 725 return 0; 726 return __pa(address) + PCI_DRAM_OFFSET; 727} 728 729static inline void * bus_to_virt(unsigned long address) 730{ 731 if (address == 0) 732 return NULL; 733 return __va(address - PCI_DRAM_OFFSET); 734} 735 736#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) 737 738#endif /* CONFIG_PPC32 */ 739 740/* access ports */ 741#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) 742#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) 743 744#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) 745#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) 746 747#endif /* __KERNEL__ */ 748 749#endif /* _ASM_POWERPC_IO_H */ 750