1#ifndef _PARISC_PGTABLE_H 2#define _PARISC_PGTABLE_H 3 4#include <asm-generic/4level-fixup.h> 5 6#include <asm/fixmap.h> 7 8#ifndef __ASSEMBLY__ 9/* 10 * we simulate an x86-style page table for the linux mm code 11 */ 12 13#include <linux/mm.h> /* for vm_area_struct */ 14#include <asm/processor.h> 15#include <asm/cache.h> 16#include <asm/bitops.h> 17 18#define kern_addr_valid(addr) (1) 19 20/* Certain architectures need to do special things when PTEs 21 * within a page table are directly modified. Thus, the following 22 * hook is made available. 23 */ 24#define set_pte(pteptr, pteval) \ 25 do{ \ 26 *(pteptr) = (pteval); \ 27 } while(0) 28#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 29 30#endif /* !__ASSEMBLY__ */ 31 32#define pte_ERROR(e) \ 33 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 34#define pmd_ERROR(e) \ 35 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e)) 36#define pgd_ERROR(e) \ 37 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e)) 38 39 /* Note: If you change ISTACK_SIZE, you need to change the corresponding 40 * values in vmlinux.lds and vmlinux64.lds (init_istack section). Also, 41 * the "order" and size need to agree. 42 */ 43 44#define ISTACK_SIZE 32768 /* Interrupt Stack Size */ 45#define ISTACK_ORDER 3 46 47/* This is the size of the initially mapped kernel memory */ 48#ifdef CONFIG_64BIT 49#define KERNEL_INITIAL_ORDER 24 /* 0 to 1<<24 = 16MB */ 50#else 51#define KERNEL_INITIAL_ORDER 23 /* 0 to 1<<23 = 8MB */ 52#endif 53#define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER) 54 55#if defined(CONFIG_64BIT) && defined(CONFIG_PARISC_PAGE_SIZE_4KB) 56#define PT_NLEVELS 3 57#define PGD_ORDER 1 /* Number of pages per pgd */ 58#define PMD_ORDER 1 /* Number of pages per pmd */ 59#define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */ 60#else 61#define PT_NLEVELS 2 62#define PGD_ORDER 1 /* Number of pages per pgd */ 63#define PGD_ALLOC_ORDER PGD_ORDER 64#endif 65 66/* Definitions for 3rd level (we use PLD here for Page Lower directory 67 * because PTE_SHIFT is used lower down to mean shift that has to be 68 * done to get usable bits out of the PTE) */ 69#define PLD_SHIFT PAGE_SHIFT 70#define PLD_SIZE PAGE_SIZE 71#define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY) 72#define PTRS_PER_PTE (1UL << BITS_PER_PTE) 73 74/* Definitions for 2nd level */ 75#define pgtable_cache_init() do { } while (0) 76 77#define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE) 78#define PMD_SIZE (1UL << PMD_SHIFT) 79#define PMD_MASK (~(PMD_SIZE-1)) 80#if PT_NLEVELS == 3 81#define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY) 82#else 83#define BITS_PER_PMD 0 84#endif 85#define PTRS_PER_PMD (1UL << BITS_PER_PMD) 86 87/* Definitions for 1st level */ 88#define PGDIR_SHIFT (PMD_SHIFT + BITS_PER_PMD) 89#define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) 90#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 91#define PGDIR_MASK (~(PGDIR_SIZE-1)) 92#define PTRS_PER_PGD (1UL << BITS_PER_PGD) 93#define USER_PTRS_PER_PGD PTRS_PER_PGD 94 95#define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD) 96#define MAX_ADDRESS (1UL << MAX_ADDRBITS) 97 98#define SPACEID_SHIFT (MAX_ADDRBITS - 32) 99 100/* This calculates the number of initial pages we need for the initial 101 * page tables */ 102#if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT) 103# define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT)) 104#else 105# define PT_INITIAL (1) /* all initial PTEs fit into one page */ 106#endif 107 108/* 109 * pgd entries used up by user/kernel: 110 */ 111 112#define FIRST_USER_ADDRESS 0 113 114#ifndef __ASSEMBLY__ 115extern void *vmalloc_start; 116#define PCXL_DMA_MAP_SIZE (8*1024*1024) 117#define VMALLOC_START ((unsigned long)vmalloc_start) 118/* this is a fixmap remnant, see fixmap.h */ 119#define VMALLOC_END (KERNEL_MAP_END) 120#endif 121 122/* NB: The tlb miss handlers make certain assumptions about the order */ 123/* of the following bits, so be careful (One example, bits 25-31 */ 124/* are moved together in one instruction). */ 125 126#define _PAGE_READ_BIT 31 /* (0x001) read access allowed */ 127#define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */ 128#define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */ 129#define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */ 130#define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */ 131#define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */ 132#define _PAGE_FILE_BIT _PAGE_DIRTY_BIT /* overload this bit */ 133#define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */ 134#define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */ 135#define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */ 136#define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */ 137#define _PAGE_FLUSH_BIT 21 /* (0x400) Software: translation valid */ 138 /* for cache flushing only */ 139#define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */ 140 141/* N.B. The bits are defined in terms of a 32 bit word above, so the */ 142/* following macro is ok for both 32 and 64 bit. */ 143 144#define xlate_pabit(x) (31 - x) 145 146/* this defines the shift to the usable bits in the PTE it is set so 147 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set 148 * to zero */ 149#define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT) 150 151/* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */ 152#define PFN_PTE_SHIFT 12 153 154 155/* this is how many bits may be used by the file functions */ 156#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_SHIFT) 157 158#define pte_to_pgoff(pte) (pte_val(pte) >> PTE_SHIFT) 159#define pgoff_to_pte(off) ((pte_t) { ((off) << PTE_SHIFT) | _PAGE_FILE }) 160 161#define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT)) 162#define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT)) 163#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 164#define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT)) 165#define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT)) 166#define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT)) 167#define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT)) 168#define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT)) 169#define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT)) 170#define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT)) 171#define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT)) 172#define _PAGE_FLUSH (1 << xlate_pabit(_PAGE_FLUSH_BIT)) 173#define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT)) 174#define _PAGE_FILE (1 << xlate_pabit(_PAGE_FILE_BIT)) 175 176#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED) 177#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 178#define _PAGE_KERNEL (_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED) 179 180/* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds 181 * are page-aligned, we don't care about the PAGE_OFFSET bits, except 182 * for a few meta-information bits, so we shift the address to be 183 * able to effectively address 40/42/44-bits of physical address space 184 * depending on 4k/16k/64k PAGE_SIZE */ 185#define _PxD_PRESENT_BIT 31 186#define _PxD_ATTACHED_BIT 30 187#define _PxD_VALID_BIT 29 188 189#define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT)) 190#define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT)) 191#define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT)) 192#define PxD_FLAG_MASK (0xf) 193#define PxD_FLAG_SHIFT (4) 194#define PxD_VALUE_SHIFT (8) /* (PAGE_SHIFT-PxD_FLAG_SHIFT) */ 195 196#ifndef __ASSEMBLY__ 197 198#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED) 199#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_ACCESSED) 200/* Others seem to make this executable, I don't know if that's correct 201 or not. The stack is mapped this way though so this is necessary 202 in the short term - dhd@linuxcare.com, 2000-08-08 */ 203#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_ACCESSED) 204#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE | _PAGE_ACCESSED) 205#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC |_PAGE_ACCESSED) 206#define PAGE_COPY PAGE_EXECREAD 207#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC |_PAGE_ACCESSED) 208#define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 209#define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) 210#define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE) 211#define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ) 212#define PAGE_FLUSH __pgprot(_PAGE_FLUSH) 213 214 215/* 216 * We could have an execute only page using "gateway - promote to priv 217 * level 3", but that is kind of silly. So, the way things are defined 218 * now, we must always have read permission for pages with execute 219 * permission. For the fun of it we'll go ahead and support write only 220 * pages. 221 */ 222 223 /*xwr*/ 224#define __P000 PAGE_NONE 225#define __P001 PAGE_READONLY 226#define __P010 __P000 /* copy on write */ 227#define __P011 __P001 /* copy on write */ 228#define __P100 PAGE_EXECREAD 229#define __P101 PAGE_EXECREAD 230#define __P110 __P100 /* copy on write */ 231#define __P111 __P101 /* copy on write */ 232 233#define __S000 PAGE_NONE 234#define __S001 PAGE_READONLY 235#define __S010 PAGE_WRITEONLY 236#define __S011 PAGE_SHARED 237#define __S100 PAGE_EXECREAD 238#define __S101 PAGE_EXECREAD 239#define __S110 PAGE_RWX 240#define __S111 PAGE_RWX 241 242 243extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */ 244 245/* initial page tables for 0-8MB for kernel */ 246 247extern pte_t pg0[]; 248 249/* zero page used for uninitialized stuff */ 250 251extern unsigned long *empty_zero_page; 252 253/* 254 * ZERO_PAGE is a global shared page that is always zero: used 255 * for zero-mapped memory areas etc.. 256 */ 257 258#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 259 260#define pte_none(x) ((pte_val(x) == 0) || (pte_val(x) & _PAGE_FLUSH)) 261#define pte_present(x) (pte_val(x) & _PAGE_PRESENT) 262#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) 263 264#define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK) 265#define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 266#define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK) 267#define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 268 269#if PT_NLEVELS == 3 270/* The first entry of the permanent pmd is not there if it contains 271 * the gateway marker */ 272#define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED) 273#else 274#define pmd_none(x) (!pmd_val(x)) 275#endif 276#define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID)) 277#define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT) 278static inline void pmd_clear(pmd_t *pmd) { 279#if PT_NLEVELS == 3 280 if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED) 281 /* This is the entry pointing to the permanent pmd 282 * attached to the pgd; cannot clear it */ 283 __pmd_val_set(*pmd, PxD_FLAG_ATTACHED); 284 else 285#endif 286 __pmd_val_set(*pmd, 0); 287} 288 289 290 291#if PT_NLEVELS == 3 292#define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_address(pgd))) 293#define pgd_page(pgd) virt_to_page((void *)pgd_page_vaddr(pgd)) 294 295/* For 64 bit we have three level tables */ 296 297#define pgd_none(x) (!pgd_val(x)) 298#define pgd_bad(x) (!(pgd_flag(x) & PxD_FLAG_VALID)) 299#define pgd_present(x) (pgd_flag(x) & PxD_FLAG_PRESENT) 300static inline void pgd_clear(pgd_t *pgd) { 301#if PT_NLEVELS == 3 302 if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED) 303 /* This is the permanent pmd attached to the pgd; cannot 304 * free it */ 305 return; 306#endif 307 __pgd_val_set(*pgd, 0); 308} 309#else 310/* 311 * The "pgd_xxx()" functions here are trivial for a folded two-level 312 * setup: the pgd is never bad, and a pmd always exists (as it's folded 313 * into the pgd entry) 314 */ 315extern inline int pgd_none(pgd_t pgd) { return 0; } 316extern inline int pgd_bad(pgd_t pgd) { return 0; } 317extern inline int pgd_present(pgd_t pgd) { return 1; } 318extern inline void pgd_clear(pgd_t * pgdp) { } 319#endif 320 321/* 322 * The following only work if pte_present() is true. 323 * Undefined behaviour if not.. 324 */ 325extern inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } 326extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 327extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 328extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } 329extern inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } 330extern inline int pte_user(pte_t pte) { return pte_val(pte) & _PAGE_USER; } 331 332extern inline pte_t pte_rdprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_READ; return pte; } 333extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } 334extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 335extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; } 336extern inline pte_t pte_mkread(pte_t pte) { pte_val(pte) |= _PAGE_READ; return pte; } 337extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } 338extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 339extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; } 340 341/* 342 * Conversion functions: convert a page and protection to a page entry, 343 * and a page entry and page directory to the page they refer to. 344 */ 345#define __mk_pte(addr,pgprot) \ 346({ \ 347 pte_t __pte; \ 348 \ 349 pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \ 350 \ 351 __pte; \ 352}) 353 354#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 355 356static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 357{ 358 pte_t pte; 359 pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot); 360 return pte; 361} 362 363extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 364{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } 365 366/* Permanent address of a page. On parisc we don't have highmem. */ 367 368#define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT) 369 370#define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 371 372#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_address(pmd))) 373 374#define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd))) 375#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 376 377#define pgd_index(address) ((address) >> PGDIR_SHIFT) 378 379/* to find an entry in a page-table-directory */ 380#define pgd_offset(mm, address) \ 381((mm)->pgd + ((address) >> PGDIR_SHIFT)) 382 383/* to find an entry in a kernel page-table-directory */ 384#define pgd_offset_k(address) pgd_offset(&init_mm, address) 385 386/* Find an entry in the second-level page table.. */ 387 388#if PT_NLEVELS == 3 389#define pmd_offset(dir,address) \ 390((pmd_t *) pgd_page_vaddr(*(dir)) + (((address)>>PMD_SHIFT) & (PTRS_PER_PMD-1))) 391#else 392#define pmd_offset(dir,addr) ((pmd_t *) dir) 393#endif 394 395/* Find an entry in the third-level page table.. */ 396#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) 397#define pte_offset_kernel(pmd, address) \ 398 ((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address)) 399#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) 400#define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address) 401#define pte_unmap(pte) do { } while (0) 402#define pte_unmap_nested(pte) do { } while (0) 403 404#define pte_unmap(pte) do { } while (0) 405#define pte_unmap_nested(pte) do { } while (0) 406 407extern void paging_init (void); 408 409/* Used for deferring calls to flush_dcache_page() */ 410 411#define PG_dcache_dirty PG_arch_1 412 413extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); 414 415/* Encode and de-code a swap entry */ 416 417#define __swp_type(x) ((x).val & 0x1f) 418#define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \ 419 (((x).val >> 8) & ~0x7) ) 420#define __swp_entry(type, offset) ((swp_entry_t) { (type) | \ 421 ((offset & 0x7) << 6) | \ 422 ((offset & ~0x7) << 8) }) 423#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 424#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 425 426static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) 427{ 428#ifdef CONFIG_SMP 429 if (!pte_young(*ptep)) 430 return 0; 431 return test_and_clear_bit(xlate_pabit(_PAGE_ACCESSED_BIT), &pte_val(*ptep)); 432#else 433 pte_t pte = *ptep; 434 if (!pte_young(pte)) 435 return 0; 436 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte)); 437 return 1; 438#endif 439} 440 441static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) 442{ 443#ifdef CONFIG_SMP 444 if (!pte_dirty(*ptep)) 445 return 0; 446 return test_and_clear_bit(xlate_pabit(_PAGE_DIRTY_BIT), &pte_val(*ptep)); 447#else 448 pte_t pte = *ptep; 449 if (!pte_dirty(pte)) 450 return 0; 451 set_pte_at(vma->vm_mm, addr, ptep, pte_mkclean(pte)); 452 return 1; 453#endif 454} 455 456extern spinlock_t pa_dbit_lock; 457 458struct mm_struct; 459static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 460{ 461 pte_t old_pte; 462 pte_t pte; 463 464 spin_lock(&pa_dbit_lock); 465 pte = old_pte = *ptep; 466 pte_val(pte) &= ~_PAGE_PRESENT; 467 pte_val(pte) |= _PAGE_FLUSH; 468 set_pte_at(mm,addr,ptep,pte); 469 spin_unlock(&pa_dbit_lock); 470 471 return old_pte; 472} 473 474static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 475{ 476#ifdef CONFIG_SMP 477 unsigned long new, old; 478 479 do { 480 old = pte_val(*ptep); 481 new = pte_val(pte_wrprotect(__pte (old))); 482 } while (cmpxchg((unsigned long *) ptep, old, new) != old); 483#else 484 pte_t old_pte = *ptep; 485 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte)); 486#endif 487} 488 489#define pte_same(A,B) (pte_val(A) == pte_val(B)) 490 491#endif /* !__ASSEMBLY__ */ 492 493 494/* TLB page size encoding - see table 3-1 in parisc20.pdf */ 495#define _PAGE_SIZE_ENCODING_4K 0 496#define _PAGE_SIZE_ENCODING_16K 1 497#define _PAGE_SIZE_ENCODING_64K 2 498#define _PAGE_SIZE_ENCODING_256K 3 499#define _PAGE_SIZE_ENCODING_1M 4 500#define _PAGE_SIZE_ENCODING_4M 5 501#define _PAGE_SIZE_ENCODING_16M 6 502#define _PAGE_SIZE_ENCODING_64M 7 503 504#if defined(CONFIG_PARISC_PAGE_SIZE_4KB) 505# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K 506#elif defined(CONFIG_PARISC_PAGE_SIZE_16KB) 507# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K 508#elif defined(CONFIG_PARISC_PAGE_SIZE_64KB) 509# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K 510#endif 511 512 513#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ 514 remap_pfn_range(vma, vaddr, pfn, size, prot) 515 516#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE) 517 518/* We provide our own get_unmapped_area to provide cache coherency */ 519 520#define HAVE_ARCH_UNMAPPED_AREA 521 522#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 523#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY 524#define __HAVE_ARCH_PTEP_GET_AND_CLEAR 525#define __HAVE_ARCH_PTEP_SET_WRPROTECT 526#define __HAVE_ARCH_PTE_SAME 527#include <asm-generic/pgtable.h> 528 529#endif /* _PARISC_PGTABLE_H */ 530