1#ifndef __PARISC_PATPDC_H
2#define __PARISC_PATPDC_H
3
4/*
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License.  See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright 2000 (c) Hewlett Packard (Paul Bame <bame()spam.parisc-linux.org>)
10 * Copyright 2000,2004 (c) Grant Grundler <grundler()nahspam.parisc-linux.org>
11 */
12
13
14#define PDC_PAT_CELL           	64L   /* Interface for gaining and
15                                         * manipulatin g cell state within PD */
16#define PDC_PAT_CELL_GET_NUMBER    0L   /* Return Cell number */
17#define PDC_PAT_CELL_GET_INFO      1L   /* Returns info about Cell */
18#define PDC_PAT_CELL_MODULE        2L   /* Returns info about Module */
19#define PDC_PAT_CELL_SET_ATTENTION 9L   /* Set Cell Attention indicator */
20#define PDC_PAT_CELL_NUMBER_TO_LOC 10L   /* Cell Number -> Location */
21#define PDC_PAT_CELL_WALK_FABRIC   11L   /* Walk the Fabric */
22#define PDC_PAT_CELL_GET_RDT_SIZE  12L   /* Return Route Distance Table Sizes */
23#define PDC_PAT_CELL_GET_RDT       13L   /* Return Route Distance Tables */
24#define PDC_PAT_CELL_GET_LOCAL_PDH_SZ 14L /* Read Local PDH Buffer Size */
25#define PDC_PAT_CELL_SET_LOCAL_PDH    15L  /* Write Local PDH Buffer */
26#define PDC_PAT_CELL_GET_REMOTE_PDH_SZ 16L /* Return Remote PDH Buffer Size */
27#define PDC_PAT_CELL_GET_REMOTE_PDH 17L /* Read Remote PDH Buffer */
28#define PDC_PAT_CELL_GET_DBG_INFO   128L  /* Return DBG Buffer Info */
29#define PDC_PAT_CELL_CHANGE_ALIAS   129L  /* Change Non-Equivalent Alias Chacking */
30
31
32/*
33** Arg to PDC_PAT_CELL_MODULE memaddr[4]
34**
35** Addresses on the Merced Bus != all Runway Bus addresses.
36** This is intended for programming SBA/LBA chips range registers.
37*/
38#define IO_VIEW      0UL
39#define PA_VIEW      1UL
40
41/* PDC_PAT_CELL_MODULE entity type values */
42#define	PAT_ENTITY_CA	0	/* central agent */
43#define	PAT_ENTITY_PROC	1	/* processor */
44#define	PAT_ENTITY_MEM	2	/* memory controller */
45#define	PAT_ENTITY_SBA	3	/* system bus adapter */
46#define	PAT_ENTITY_LBA	4	/* local bus adapter */
47#define	PAT_ENTITY_PBC	5	/* processor bus converter */
48#define	PAT_ENTITY_XBC	6	/* crossbar fabric connect */
49#define	PAT_ENTITY_RC	7	/* fabric interconnect */
50
51/* PDC_PAT_CELL_MODULE address range type values */
52#define PAT_PBNUM           0         /* PCI Bus Number */
53#define PAT_LMMIO           1         /* < 4G MMIO Space */
54#define PAT_GMMIO           2         /* > 4G MMIO Space */
55#define PAT_NPIOP           3         /* Non Postable I/O Port Space */
56#define PAT_PIOP            4         /* Postable I/O Port Space */
57#define PAT_AHPA            5         /* Addional HPA Space */
58#define PAT_UFO             6         /* HPA Space (UFO for Mariposa) */
59#define PAT_GNIP            7         /* GNI Reserved Space */
60
61
62
63/* PDC PAT CHASSIS LOG -- Platform logging & forward progress functions */
64
65#define PDC_PAT_CHASSIS_LOG		65L
66#define PDC_PAT_CHASSIS_WRITE_LOG    	0L /* Write Log Entry */
67#define PDC_PAT_CHASSIS_READ_LOG     	1L /* Read  Log Entry */
68
69
70/* PDC PAT CPU  -- CPU configuration within the protection domain */
71
72#define PDC_PAT_CPU                	67L
73#define PDC_PAT_CPU_INFO            	0L /* Return CPU config info */
74#define PDC_PAT_CPU_DELETE          	1L /* Delete CPU */
75#define PDC_PAT_CPU_ADD             	2L /* Add    CPU */
76#define PDC_PAT_CPU_GET_NUMBER      	3L /* Return CPU Number */
77#define PDC_PAT_CPU_GET_HPA         	4L /* Return CPU HPA */
78#define PDC_PAT_CPU_STOP            	5L /* Stop   CPU */
79#define PDC_PAT_CPU_RENDEZVOUS      	6L /* Rendezvous CPU */
80#define PDC_PAT_CPU_GET_CLOCK_INFO  	7L /* Return CPU Clock info */
81#define PDC_PAT_CPU_GET_RENDEZVOUS_STATE 8L /* Return Rendezvous State */
82#define PDC_PAT_CPU_PLUNGE_FABRIC 	128L /* Plunge Fabric */
83#define PDC_PAT_CPU_UPDATE_CACHE_CLEANSING 129L /* Manipulate Cache
84                                                 * Cleansing Mode */
85/*  PDC PAT EVENT -- Platform Events */
86
87#define PDC_PAT_EVENT              	68L
88#define PDC_PAT_EVENT_GET_CAPS     	0L /* Get Capabilities */
89#define PDC_PAT_EVENT_SET_MODE     	1L /* Set Notification Mode */
90#define PDC_PAT_EVENT_SCAN         	2L /* Scan Event */
91#define PDC_PAT_EVENT_HANDLE       	3L /* Handle Event */
92#define PDC_PAT_EVENT_GET_NB_CALL  	4L /* Get Non-Blocking call Args */
93
94/*  PDC PAT HPMC -- Cause processor to go into spin loop, and wait
95 *  			for wake up from Monarch Processor.
96 */
97
98#define PDC_PAT_HPMC               70L
99#define PDC_PAT_HPMC_RENDEZ_CPU     0L /* go into spin loop */
100#define PDC_PAT_HPMC_SET_PARAMS     1L /* Allows OS to specify intr which PDC
101                                        * will use to interrupt OS during
102                                        * machine check rendezvous */
103
104/* parameters for PDC_PAT_HPMC_SET_PARAMS: */
105#define HPMC_SET_PARAMS_INTR 	    1L /* Rendezvous Interrupt */
106#define HPMC_SET_PARAMS_WAKE 	    2L /* Wake up processor */
107
108
109/*  PDC PAT IO  -- On-line services for I/O modules */
110
111#define PDC_PAT_IO                  71L
112#define PDC_PAT_IO_GET_SLOT_STATUS   	5L /* Get Slot Status Info*/
113#define PDC_PAT_IO_GET_LOC_FROM_HARDWARE 6L /* Get Physical Location from */
114                                            /* Hardware Path */
115#define PDC_PAT_IO_GET_HARDWARE_FROM_LOC 7L /* Get Hardware Path from
116                                             * Physical Location */
117#define PDC_PAT_IO_GET_PCI_CONFIG_FROM_HW 11L /* Get PCI Configuration
118                                               * Address from Hardware Path */
119#define PDC_PAT_IO_GET_HW_FROM_PCI_CONFIG 12L /* Get Hardware Path
120                                               * from PCI Configuration Address */
121#define PDC_PAT_IO_READ_HOST_BRIDGE_INFO 13L  /* Read Host Bridge State Info */
122#define PDC_PAT_IO_CLEAR_HOST_BRIDGE_INFO 14L /* Clear Host Bridge State Info*/
123#define PDC_PAT_IO_GET_PCI_ROUTING_TABLE_SIZE 15L /* Get PCI INT Routing Table
124                                                   * Size */
125#define PDC_PAT_IO_GET_PCI_ROUTING_TABLE  16L /* Get PCI INT Routing Table */
126#define PDC_PAT_IO_GET_HINT_TABLE_SIZE 	17L /* Get Hint Table Size */
127#define PDC_PAT_IO_GET_HINT_TABLE   	18L /* Get Hint Table */
128#define PDC_PAT_IO_PCI_CONFIG_READ  	19L /* PCI Config Read */
129#define PDC_PAT_IO_PCI_CONFIG_WRITE 	20L /* PCI Config Write */
130#define PDC_PAT_IO_GET_NUM_IO_SLOTS 	21L /* Get Number of I/O Bay Slots in
131                                       		  * Cabinet */
132#define PDC_PAT_IO_GET_LOC_IO_SLOTS 	22L /* Get Physical Location of I/O */
133                                   		     /* Bay Slots in Cabinet */
134#define PDC_PAT_IO_BAY_STATUS_INFO  	28L /* Get I/O Bay Slot Status Info */
135#define PDC_PAT_IO_GET_PROC_VIEW        29L /* Get Processor view of IO address */
136#define PDC_PAT_IO_PROG_SBA_DIR_RANGE   30L /* Program directed range */
137
138
139/* PDC PAT MEM  -- Manage memory page deallocation */
140
141#define PDC_PAT_MEM            72L
142#define PDC_PAT_MEM_PD_INFO     	0L /* Return PDT info for PD       */
143#define PDC_PAT_MEM_PD_CLEAR    	1L /* Clear PDT for PD             */
144#define PDC_PAT_MEM_PD_READ     	2L /* Read PDT entries for PD      */
145#define PDC_PAT_MEM_PD_RESET    	3L /* Reset clear bit for PD       */
146#define PDC_PAT_MEM_CELL_INFO   	5L /* Return PDT info For Cell     */
147#define PDC_PAT_MEM_CELL_CLEAR  	6L /* Clear PDT For Cell           */
148#define PDC_PAT_MEM_CELL_READ   	7L /* Read PDT entries For Cell    */
149#define PDC_PAT_MEM_CELL_RESET  	8L /* Reset clear bit For Cell     */
150#define PDC_PAT_MEM_SETGM	  	9L /* Set Golden Memory value      */
151#define PDC_PAT_MEM_ADD_PAGE    	10L /* ADDs a page to the cell      */
152#define PDC_PAT_MEM_ADDRESS     	11L /* Get Physical Location From   */
153                                    		 /* Memory Address               */
154#define PDC_PAT_MEM_GET_TXT_SIZE   	12L /* Get Formatted Text Size   */
155#define PDC_PAT_MEM_GET_PD_TXT     	13L /* Get PD Formatted Text     */
156#define PDC_PAT_MEM_GET_CELL_TXT   	14L /* Get Cell Formatted Text   */
157#define PDC_PAT_MEM_RD_STATE_INFO  	15L /* Read Mem Module State Info*/
158#define PDC_PAT_MEM_CLR_STATE_INFO 	16L /*Clear Mem Module State Info*/
159#define PDC_PAT_MEM_CLEAN_RANGE    	128L /*Clean Mem in specific range*/
160#define PDC_PAT_MEM_GET_TBL_SIZE   	131L /* Get Memory Table Size     */
161#define PDC_PAT_MEM_GET_TBL        	132L /* Get Memory Table          */
162
163
164/* PDC PAT NVOLATILE  --  Access Non-Volatile Memory */
165
166#define PDC_PAT_NVOLATILE	73L
167#define PDC_PAT_NVOLATILE_READ		0L /* Read Non-Volatile Memory   */
168#define PDC_PAT_NVOLATILE_WRITE		1L /* Write Non-Volatile Memory  */
169#define PDC_PAT_NVOLATILE_GET_SIZE	2L /* Return size of NVM         */
170#define PDC_PAT_NVOLATILE_VERIFY	3L /* Verify contents of NVM     */
171#define PDC_PAT_NVOLATILE_INIT		4L /* Initialize NVM             */
172
173/* PDC PAT PD */
174#define PDC_PAT_PD		74L         /* Protection Domain Info   */
175#define PDC_PAT_PD_GET_ADDR_MAP		0L  /* Get Address Map          */
176
177/* PDC_PAT_PD_GET_ADDR_MAP entry types */
178#define PAT_MEMORY_DESCRIPTOR		1
179
180/* PDC_PAT_PD_GET_ADDR_MAP memory types */
181#define PAT_MEMTYPE_MEMORY		0
182#define PAT_MEMTYPE_FIRMWARE		4
183
184/* PDC_PAT_PD_GET_ADDR_MAP memory usage */
185#define PAT_MEMUSE_GENERAL		0
186#define PAT_MEMUSE_GI			128
187#define PAT_MEMUSE_GNI			129
188
189
190#ifndef __ASSEMBLY__
191#include <linux/types.h>
192
193#ifdef CONFIG_64BIT
194#define is_pdc_pat()	(PDC_TYPE_PAT == pdc_type)
195extern int pdc_pat_get_irt_size(unsigned long *num_entries, unsigned long cell_num);
196extern int pdc_pat_get_irt(void *r_addr, unsigned long cell_num);
197#else	/* ! CONFIG_64BIT */
198/* No PAT support for 32-bit kernels...sorry */
199#define is_pdc_pat()	(0)
200#define pdc_pat_get_irt_size(num_entries, cell_numn)	PDC_BAD_PROC
201#define pdc_pat_get_irt(r_addr, cell_num)		PDC_BAD_PROC
202#endif	/* ! CONFIG_64BIT */
203
204
205struct pdc_pat_cell_num {
206	unsigned long cell_num;
207	unsigned long cell_loc;
208};
209
210struct pdc_pat_cpu_num {
211	unsigned long cpu_num;
212	unsigned long cpu_loc;
213};
214
215struct pdc_pat_pd_addr_map_entry {
216	unsigned char entry_type;       /* 1 = Memory Descriptor Entry Type */
217	unsigned char reserve1[5];
218	unsigned char memory_type;
219	unsigned char memory_usage;
220	unsigned long paddr;
221	unsigned int  pages;            /* Length in 4K pages */
222	unsigned int  reserve2;
223	unsigned long cell_map;
224};
225
226/********************************************************************
227* PDC_PAT_CELL[Return Cell Module] memaddr[0] conf_base_addr
228* ----------------------------------------------------------
229* Bit  0 to 51 - conf_base_addr
230* Bit 52 to 62 - reserved
231* Bit       63 - endianess bit
232********************************************************************/
233#define PAT_GET_CBA(value) ((value) & 0xfffffffffffff000UL)
234
235/********************************************************************
236* PDC_PAT_CELL[Return Cell Module] memaddr[1] mod_info
237* ----------------------------------------------------
238* Bit  0 to  7 - entity type
239*    0 = central agent,            1 = processor,
240*    2 = memory controller,        3 = system bus adapter,
241*    4 = local bus adapter,        5 = processor bus converter,
242*    6 = crossbar fabric connect,  7 = fabric interconnect,
243*    8 to 254 reserved,            255 = unknown.
244* Bit  8 to 15 - DVI
245* Bit 16 to 23 - IOC functions
246* Bit 24 to 39 - reserved
247* Bit 40 to 63 - mod_pages
248*    number of 4K pages a module occupies starting at conf_base_addr
249********************************************************************/
250#define PAT_GET_ENTITY(value)	(((value) >> 56) & 0xffUL)
251#define PAT_GET_DVI(value)	(((value) >> 48) & 0xffUL)
252#define PAT_GET_IOC(value)	(((value) >> 40) & 0xffUL)
253#define PAT_GET_MOD_PAGES(value) ((value) & 0xffffffUL)
254
255
256/*
257** PDC_PAT_CELL_GET_INFO return block
258*/
259typedef struct pdc_pat_cell_info_rtn_block {
260	unsigned long cpu_info;
261	unsigned long cell_info;
262	unsigned long cell_location;
263	unsigned long reo_location;
264	unsigned long mem_size;
265	unsigned long dimm_status;
266	unsigned long pdc_rev;
267	unsigned long fabric_info0;
268	unsigned long fabric_info1;
269	unsigned long fabric_info2;
270	unsigned long fabric_info3;
271	unsigned long reserved[21];
272} pdc_pat_cell_info_rtn_block_t;
273
274
275struct pdc_pat_cell_mod_maddr_block {	/* PDC_PAT_CELL_MODULE */
276	unsigned long cba;		/* func 0 cfg space address */
277	unsigned long mod_info;		/* module information */
278	unsigned long mod_location;	/* physical location of the module */
279	struct hardware_path mod_path;	/* module path (device path - layers) */
280	unsigned long mod[508];		/* PAT cell module components */
281} __attribute__((aligned(8))) ;
282
283typedef struct pdc_pat_cell_mod_maddr_block pdc_pat_cell_mod_maddr_block_t;
284
285
286extern int pdc_pat_chassis_send_log(unsigned long status, unsigned long data);
287extern int pdc_pat_cell_get_number(struct pdc_pat_cell_num *cell_info);
288extern int pdc_pat_cell_module(unsigned long *actcnt, unsigned long ploc, unsigned long mod, unsigned long view_type, void *mem_addr);
289extern int pdc_pat_cell_num_to_loc(void *, unsigned long);
290
291extern int pdc_pat_cpu_get_number(struct pdc_pat_cpu_num *cpu_info, void *hpa);
292
293extern int pdc_pat_pd_get_addr_map(unsigned long *actual_len, void *mem_addr, unsigned long count, unsigned long offset);
294
295
296extern int pdc_pat_io_pci_cfg_read(unsigned long pci_addr, int pci_size, u32 *val);
297extern int pdc_pat_io_pci_cfg_write(unsigned long pci_addr, int pci_size, u32 val);
298
299
300/* Flag to indicate this is a PAT box...don't use this unless you
301** really have to...it might go away some day.
302*/
303extern int pdc_pat;     /* arch/parisc/kernel/inventory.c */
304
305#endif /* __ASSEMBLY__ */
306
307#endif /* ! __PARISC_PATPDC_H */
308