1/*
2 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
3 * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
4 * Copyright (C) 1999 SuSE GmbH
5 *
6 *    This program is free software; you can redistribute it and/or modify
7 *    it under the terms of the GNU General Public License as published by
8 *    the Free Software Foundation; either version 2, or (at your option)
9 *    any later version.
10 *
11 *    This program is distributed in the hope that it will be useful,
12 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 *    GNU General Public License for more details.
15 *
16 *    You should have received a copy of the GNU General Public License
17 *    along with this program; if not, write to the Free Software
18 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef _PARISC_ASSEMBLY_H
22#define _PARISC_ASSEMBLY_H
23
24#define CALLEE_FLOAT_FRAME_SIZE	80
25
26#ifdef CONFIG_64BIT
27#define LDREG	ldd
28#define STREG	std
29#define LDREGX  ldd,s
30#define LDREGM	ldd,mb
31#define STREGM	std,ma
32#define SHRREG	shrd
33#define SHLREG	shld
34#define ADDIB   addib,*
35#define CMPB    cmpb,*
36#define ANDCM   andcm,*
37#define RP_OFFSET	16
38#define FRAME_SIZE	128
39#define CALLEE_REG_FRAME_SIZE	144
40#define ASM_ULONG_INSN	.dword
41#else	/* CONFIG_64BIT */
42#define LDREG	ldw
43#define STREG	stw
44#define LDREGX  ldwx,s
45#define LDREGM	ldwm
46#define STREGM	stwm
47#define SHRREG	shr
48#define SHLREG	shlw
49#define ADDIB   addib,
50#define CMPB    cmpb,
51#define ANDCM   andcm
52#define RP_OFFSET	20
53#define FRAME_SIZE	64
54#define CALLEE_REG_FRAME_SIZE	128
55#define ASM_ULONG_INSN	.word
56#endif
57
58#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
59
60#ifdef CONFIG_PA20
61#define LDCW		ldcw,co
62#define BL		b,l
63# ifdef CONFIG_64BIT
64#  define LEVEL		2.0w
65# else
66#  define LEVEL		2.0
67# endif
68#else
69#define LDCW		ldcw
70#define BL		bl
71#define LEVEL		1.1
72#endif
73
74#ifdef __ASSEMBLY__
75
76#ifdef CONFIG_64BIT
77	.level 2.0w
78#endif
79
80#include <asm/asm-offsets.h>
81#include <asm/page.h>
82
83#include <asm/asmregs.h>
84
85	sp	=	30
86	gp	=	27
87	ipsw	=	22
88
89	/*
90	 * We provide two versions of each macro to convert from physical
91	 * to virtual and vice versa. The "_r1" versions take one argument
92	 * register, but trashes r1 to do the conversion. The other
93	 * version takes two arguments: a src and destination register.
94	 * However, the source and destination registers can not be
95	 * the same register.
96	 */
97
98	.macro  tophys  grvirt, grphys
99	ldil    L%(__PAGE_OFFSET), \grphys
100	sub     \grvirt, \grphys, \grphys
101	.endm
102
103	.macro  tovirt  grphys, grvirt
104	ldil    L%(__PAGE_OFFSET), \grvirt
105	add     \grphys, \grvirt, \grvirt
106	.endm
107
108	.macro  tophys_r1  gr
109	ldil    L%(__PAGE_OFFSET), %r1
110	sub     \gr, %r1, \gr
111	.endm
112
113	.macro  tovirt_r1  gr
114	ldil    L%(__PAGE_OFFSET), %r1
115	add     \gr, %r1, \gr
116	.endm
117
118	.macro delay value
119	ldil	L%\value, 1
120	ldo	R%\value(1), 1
121	addib,UV,n -1,1,.
122	addib,NUV,n -1,1,.+8
123	nop
124	.endm
125
126	.macro	debug value
127	.endm
128
129
130	/* Shift Left - note the r and t can NOT be the same! */
131	.macro shl r, sa, t
132	dep,z	\r, 31-\sa, 32-\sa, \t
133	.endm
134
135	/* The PA 2.0 shift left */
136	.macro shlw r, sa, t
137	depw,z	\r, 31-\sa, 32-\sa, \t
138	.endm
139
140	/* And the PA 2.0W shift left */
141	.macro shld r, sa, t
142	depd,z	\r, 63-\sa, 64-\sa, \t
143	.endm
144
145	/* Shift Right - note the r and t can NOT be the same! */
146	.macro shr r, sa, t
147	extru \r, 31-\sa, 32-\sa, \t
148	.endm
149
150	/* pa20w version of shift right */
151	.macro shrd r, sa, t
152	extrd,u \r, 63-\sa, 64-\sa, \t
153	.endm
154
155	/* load 32-bit 'value' into 'reg' compensating for the ldil
156	 * sign-extension when running in wide mode.
157	 * WARNING!! neither 'value' nor 'reg' can be expressions
158	 * containing '.'!!!! */
159	.macro	load32 value, reg
160	ldil	L%\value, \reg
161	ldo	R%\value(\reg), \reg
162	.endm
163
164	.macro loadgp
165#ifdef CONFIG_64BIT
166	ldil		L%__gp, %r27
167	ldo		R%__gp(%r27), %r27
168#else
169	ldil		L%$global$, %r27
170	ldo		R%$global$(%r27), %r27
171#endif
172	.endm
173
174#define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
175#define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
176#define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
177#define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
178
179	.macro	save_general	regs
180	STREG %r1, PT_GR1 (\regs)
181	STREG %r2, PT_GR2 (\regs)
182	STREG %r3, PT_GR3 (\regs)
183	STREG %r4, PT_GR4 (\regs)
184	STREG %r5, PT_GR5 (\regs)
185	STREG %r6, PT_GR6 (\regs)
186	STREG %r7, PT_GR7 (\regs)
187	STREG %r8, PT_GR8 (\regs)
188	STREG %r9, PT_GR9 (\regs)
189	STREG %r10, PT_GR10(\regs)
190	STREG %r11, PT_GR11(\regs)
191	STREG %r12, PT_GR12(\regs)
192	STREG %r13, PT_GR13(\regs)
193	STREG %r14, PT_GR14(\regs)
194	STREG %r15, PT_GR15(\regs)
195	STREG %r16, PT_GR16(\regs)
196	STREG %r17, PT_GR17(\regs)
197	STREG %r18, PT_GR18(\regs)
198	STREG %r19, PT_GR19(\regs)
199	STREG %r20, PT_GR20(\regs)
200	STREG %r21, PT_GR21(\regs)
201	STREG %r22, PT_GR22(\regs)
202	STREG %r23, PT_GR23(\regs)
203	STREG %r24, PT_GR24(\regs)
204	STREG %r25, PT_GR25(\regs)
205	/* r26 is saved in get_stack and used to preserve a value across virt_map */
206	STREG %r27, PT_GR27(\regs)
207	STREG %r28, PT_GR28(\regs)
208	/* r29 is saved in get_stack and used to point to saved registers */
209	/* r30 stack pointer saved in get_stack */
210	STREG %r31, PT_GR31(\regs)
211	.endm
212
213	.macro	rest_general	regs
214	/* r1 used as a temp in rest_stack and is restored there */
215	LDREG PT_GR2 (\regs), %r2
216	LDREG PT_GR3 (\regs), %r3
217	LDREG PT_GR4 (\regs), %r4
218	LDREG PT_GR5 (\regs), %r5
219	LDREG PT_GR6 (\regs), %r6
220	LDREG PT_GR7 (\regs), %r7
221	LDREG PT_GR8 (\regs), %r8
222	LDREG PT_GR9 (\regs), %r9
223	LDREG PT_GR10(\regs), %r10
224	LDREG PT_GR11(\regs), %r11
225	LDREG PT_GR12(\regs), %r12
226	LDREG PT_GR13(\regs), %r13
227	LDREG PT_GR14(\regs), %r14
228	LDREG PT_GR15(\regs), %r15
229	LDREG PT_GR16(\regs), %r16
230	LDREG PT_GR17(\regs), %r17
231	LDREG PT_GR18(\regs), %r18
232	LDREG PT_GR19(\regs), %r19
233	LDREG PT_GR20(\regs), %r20
234	LDREG PT_GR21(\regs), %r21
235	LDREG PT_GR22(\regs), %r22
236	LDREG PT_GR23(\regs), %r23
237	LDREG PT_GR24(\regs), %r24
238	LDREG PT_GR25(\regs), %r25
239	LDREG PT_GR26(\regs), %r26
240	LDREG PT_GR27(\regs), %r27
241	LDREG PT_GR28(\regs), %r28
242	/* r29 points to register save area, and is restored in rest_stack */
243	/* r30 stack pointer restored in rest_stack */
244	LDREG PT_GR31(\regs), %r31
245	.endm
246
247	.macro	save_fp 	regs
248	fstd,ma  %fr0, 8(\regs)
249	fstd,ma	 %fr1, 8(\regs)
250	fstd,ma	 %fr2, 8(\regs)
251	fstd,ma	 %fr3, 8(\regs)
252	fstd,ma	 %fr4, 8(\regs)
253	fstd,ma	 %fr5, 8(\regs)
254	fstd,ma	 %fr6, 8(\regs)
255	fstd,ma	 %fr7, 8(\regs)
256	fstd,ma	 %fr8, 8(\regs)
257	fstd,ma	 %fr9, 8(\regs)
258	fstd,ma	%fr10, 8(\regs)
259	fstd,ma	%fr11, 8(\regs)
260	fstd,ma	%fr12, 8(\regs)
261	fstd,ma	%fr13, 8(\regs)
262	fstd,ma	%fr14, 8(\regs)
263	fstd,ma	%fr15, 8(\regs)
264	fstd,ma	%fr16, 8(\regs)
265	fstd,ma	%fr17, 8(\regs)
266	fstd,ma	%fr18, 8(\regs)
267	fstd,ma	%fr19, 8(\regs)
268	fstd,ma	%fr20, 8(\regs)
269	fstd,ma	%fr21, 8(\regs)
270	fstd,ma	%fr22, 8(\regs)
271	fstd,ma	%fr23, 8(\regs)
272	fstd,ma	%fr24, 8(\regs)
273	fstd,ma	%fr25, 8(\regs)
274	fstd,ma	%fr26, 8(\regs)
275	fstd,ma	%fr27, 8(\regs)
276	fstd,ma	%fr28, 8(\regs)
277	fstd,ma	%fr29, 8(\regs)
278	fstd,ma	%fr30, 8(\regs)
279	fstd	%fr31, 0(\regs)
280	.endm
281
282	.macro	rest_fp 	regs
283	fldd	0(\regs),	 %fr31
284	fldd,mb	-8(\regs),       %fr30
285	fldd,mb	-8(\regs),       %fr29
286	fldd,mb	-8(\regs),       %fr28
287	fldd,mb	-8(\regs),       %fr27
288	fldd,mb	-8(\regs),       %fr26
289	fldd,mb	-8(\regs),       %fr25
290	fldd,mb	-8(\regs),       %fr24
291	fldd,mb	-8(\regs),       %fr23
292	fldd,mb	-8(\regs),       %fr22
293	fldd,mb	-8(\regs),       %fr21
294	fldd,mb	-8(\regs),       %fr20
295	fldd,mb	-8(\regs),       %fr19
296	fldd,mb	-8(\regs),       %fr18
297	fldd,mb	-8(\regs),       %fr17
298	fldd,mb	-8(\regs),       %fr16
299	fldd,mb	-8(\regs),       %fr15
300	fldd,mb	-8(\regs),       %fr14
301	fldd,mb	-8(\regs),       %fr13
302	fldd,mb	-8(\regs),       %fr12
303	fldd,mb	-8(\regs),       %fr11
304	fldd,mb	-8(\regs),       %fr10
305	fldd,mb	-8(\regs),       %fr9
306	fldd,mb	-8(\regs),       %fr8
307	fldd,mb	-8(\regs),       %fr7
308	fldd,mb	-8(\regs),       %fr6
309	fldd,mb	-8(\regs),       %fr5
310	fldd,mb	-8(\regs),       %fr4
311	fldd,mb	-8(\regs),       %fr3
312	fldd,mb	-8(\regs),       %fr2
313	fldd,mb	-8(\regs),       %fr1
314	fldd,mb	-8(\regs),       %fr0
315	.endm
316
317	.macro	callee_save_float
318	fstd,ma	 %fr12,	8(%r30)
319	fstd,ma	 %fr13,	8(%r30)
320	fstd,ma	 %fr14,	8(%r30)
321	fstd,ma	 %fr15,	8(%r30)
322	fstd,ma	 %fr16,	8(%r30)
323	fstd,ma	 %fr17,	8(%r30)
324	fstd,ma	 %fr18,	8(%r30)
325	fstd,ma	 %fr19,	8(%r30)
326	fstd,ma	 %fr20,	8(%r30)
327	fstd,ma	 %fr21,	8(%r30)
328	.endm
329
330	.macro	callee_rest_float
331	fldd,mb	-8(%r30),   %fr21
332	fldd,mb	-8(%r30),   %fr20
333	fldd,mb	-8(%r30),   %fr19
334	fldd,mb	-8(%r30),   %fr18
335	fldd,mb	-8(%r30),   %fr17
336	fldd,mb	-8(%r30),   %fr16
337	fldd,mb	-8(%r30),   %fr15
338	fldd,mb	-8(%r30),   %fr14
339	fldd,mb	-8(%r30),   %fr13
340	fldd,mb	-8(%r30),   %fr12
341	.endm
342
343#ifdef CONFIG_64BIT
344	.macro	callee_save
345	std,ma	  %r3,	 CALLEE_REG_FRAME_SIZE(%r30)
346	mfctl	  %cr27, %r3
347	std	  %r4,	-136(%r30)
348	std	  %r5,	-128(%r30)
349	std	  %r6,	-120(%r30)
350	std	  %r7,	-112(%r30)
351	std	  %r8,	-104(%r30)
352	std	  %r9,	 -96(%r30)
353	std	 %r10,	 -88(%r30)
354	std	 %r11,	 -80(%r30)
355	std	 %r12,	 -72(%r30)
356	std	 %r13,	 -64(%r30)
357	std	 %r14,	 -56(%r30)
358	std	 %r15,	 -48(%r30)
359	std	 %r16,	 -40(%r30)
360	std	 %r17,	 -32(%r30)
361	std	 %r18,	 -24(%r30)
362	std	  %r3,	 -16(%r30)
363	.endm
364
365	.macro	callee_rest
366	ldd	 -16(%r30),    %r3
367	ldd	 -24(%r30),   %r18
368	ldd	 -32(%r30),   %r17
369	ldd	 -40(%r30),   %r16
370	ldd	 -48(%r30),   %r15
371	ldd	 -56(%r30),   %r14
372	ldd	 -64(%r30),   %r13
373	ldd	 -72(%r30),   %r12
374	ldd	 -80(%r30),   %r11
375	ldd	 -88(%r30),   %r10
376	ldd	 -96(%r30),    %r9
377	ldd	-104(%r30),    %r8
378	ldd	-112(%r30),    %r7
379	ldd	-120(%r30),    %r6
380	ldd	-128(%r30),    %r5
381	ldd	-136(%r30),    %r4
382	mtctl	%r3, %cr27
383	ldd,mb	-CALLEE_REG_FRAME_SIZE(%r30),    %r3
384	.endm
385
386#else /* ! CONFIG_64BIT */
387
388	.macro	callee_save
389	stw,ma	 %r3,	CALLEE_REG_FRAME_SIZE(%r30)
390	mfctl	 %cr27, %r3
391	stw	 %r4,	-124(%r30)
392	stw	 %r5,	-120(%r30)
393	stw	 %r6,	-116(%r30)
394	stw	 %r7,	-112(%r30)
395	stw	 %r8,	-108(%r30)
396	stw	 %r9,	-104(%r30)
397	stw	 %r10,	-100(%r30)
398	stw	 %r11,	 -96(%r30)
399	stw	 %r12,	 -92(%r30)
400	stw	 %r13,	 -88(%r30)
401	stw	 %r14,	 -84(%r30)
402	stw	 %r15,	 -80(%r30)
403	stw	 %r16,	 -76(%r30)
404	stw	 %r17,	 -72(%r30)
405	stw	 %r18,	 -68(%r30)
406	stw	  %r3,	 -64(%r30)
407	.endm
408
409	.macro	callee_rest
410	ldw	 -64(%r30),    %r3
411	ldw	 -68(%r30),   %r18
412	ldw	 -72(%r30),   %r17
413	ldw	 -76(%r30),   %r16
414	ldw	 -80(%r30),   %r15
415	ldw	 -84(%r30),   %r14
416	ldw	 -88(%r30),   %r13
417	ldw	 -92(%r30),   %r12
418	ldw	 -96(%r30),   %r11
419	ldw	-100(%r30),   %r10
420	ldw	-104(%r30),   %r9
421	ldw	-108(%r30),   %r8
422	ldw	-112(%r30),   %r7
423	ldw	-116(%r30),   %r6
424	ldw	-120(%r30),   %r5
425	ldw	-124(%r30),   %r4
426	mtctl	%r3, %cr27
427	ldw,mb	-CALLEE_REG_FRAME_SIZE(%r30),   %r3
428	.endm
429#endif /* ! CONFIG_64BIT */
430
431	.macro	save_specials	regs
432
433	SAVE_SP  (%sr0, PT_SR0 (\regs))
434	SAVE_SP  (%sr1, PT_SR1 (\regs))
435	SAVE_SP  (%sr2, PT_SR2 (\regs))
436	SAVE_SP  (%sr3, PT_SR3 (\regs))
437	SAVE_SP  (%sr4, PT_SR4 (\regs))
438	SAVE_SP  (%sr5, PT_SR5 (\regs))
439	SAVE_SP  (%sr6, PT_SR6 (\regs))
440	SAVE_SP  (%sr7, PT_SR7 (\regs))
441
442	SAVE_CR  (%cr17, PT_IASQ0(\regs))
443	mtctl	 %r0,	%cr17
444	SAVE_CR  (%cr17, PT_IASQ1(\regs))
445
446	SAVE_CR  (%cr18, PT_IAOQ0(\regs))
447	mtctl	 %r0,	%cr18
448	SAVE_CR  (%cr18, PT_IAOQ1(\regs))
449
450#ifdef CONFIG_64BIT
451	/* cr11 (sar) is a funny one.  5 bits on PA1.1 and 6 bit on PA2.0
452	 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
453	 * reads 5 bits.  Use mfctl,w to read all six bits.  Otherwise
454	 * we lose the 6th bit on a save/restore over interrupt.
455	 */
456	mfctl,w  %cr11, %r1
457	STREG    %r1, PT_SAR (\regs)
458#else
459	SAVE_CR  (%cr11, PT_SAR  (\regs))
460#endif
461	SAVE_CR  (%cr19, PT_IIR  (\regs))
462
463	/*
464	 * Code immediately following this macro (in intr_save) relies
465	 * on r8 containing ipsw.
466	 */
467	mfctl    %cr22, %r8
468	STREG    %r8,   PT_PSW(\regs)
469	.endm
470
471	.macro	rest_specials	regs
472
473	REST_SP  (%sr0, PT_SR0 (\regs))
474	REST_SP  (%sr1, PT_SR1 (\regs))
475	REST_SP  (%sr2, PT_SR2 (\regs))
476	REST_SP  (%sr3, PT_SR3 (\regs))
477	REST_SP  (%sr4, PT_SR4 (\regs))
478	REST_SP  (%sr5, PT_SR5 (\regs))
479	REST_SP  (%sr6, PT_SR6 (\regs))
480	REST_SP  (%sr7, PT_SR7 (\regs))
481
482	REST_CR	(%cr17, PT_IASQ0(\regs))
483	REST_CR	(%cr17, PT_IASQ1(\regs))
484
485	REST_CR	(%cr18, PT_IAOQ0(\regs))
486	REST_CR	(%cr18, PT_IAOQ1(\regs))
487
488	REST_CR (%cr11, PT_SAR	(\regs))
489
490	REST_CR	(%cr22, PT_PSW	(\regs))
491	.endm
492
493
494	/* First step to create a "relied upon translation"
495	 * See PA 2.0 Arch. page F-4 and F-5.
496	 *
497	 * The ssm was originally necessary due to a "PCxT bug".
498	 * But someone decided it needed to be added to the architecture
499	 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
500	 * It's been carried forward into PA 2.0 Arch as well. :^(
501	 *
502	 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
503	 * rsm/ssm prevents the ifetch unit from speculatively fetching
504	 * instructions past this line in the code stream.
505	 * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
506	 */
507	.macro	pcxt_ssm_bug
508	rsm	PSW_SM_I,%r0
509	nop	/* 1 */
510	nop	/* 2 */
511	nop	/* 3 */
512	nop	/* 4 */
513	nop	/* 5 */
514	nop	/* 6 */
515	nop	/* 7 */
516	.endm
517
518#endif /* __ASSEMBLY__ */
519#endif
520