1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * MAC constants and macros File: sb1250_mac.h 5 * 6 * This module contains constants and macros for the SB1250's 7 * ethernet controllers. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 ********************************************************************* */ 31 32 33#ifndef _SB1250_MAC_H 34#define _SB1250_MAC_H 35 36#include "sb1250_defs.h" 37 38/* ********************************************************************* 39 * Ethernet MAC Registers 40 ********************************************************************* */ 41 42/* 43 * MAC Configuration Register (Table 9-13) 44 * Register: MAC_CFG_0 45 * Register: MAC_CFG_1 46 * Register: MAC_CFG_2 47 */ 48 49 50#define M_MAC_RESERVED0 _SB_MAKEMASK1(0) 51#define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1) 52#define M_MAC_RETRY_EN _SB_MAKEMASK1(2) 53#define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3) 54#define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4) 55#define M_MAC_BURST_EN _SB_MAKEMASK1(5) 56 57#define S_MAC_TX_PAUSE _SB_MAKE64(6) 58#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE) 59#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE) 60 61#define K_MAC_TX_PAUSE_CNT_512 0 62#define K_MAC_TX_PAUSE_CNT_1K 1 63#define K_MAC_TX_PAUSE_CNT_2K 2 64#define K_MAC_TX_PAUSE_CNT_4K 3 65#define K_MAC_TX_PAUSE_CNT_8K 4 66#define K_MAC_TX_PAUSE_CNT_16K 5 67#define K_MAC_TX_PAUSE_CNT_32K 6 68#define K_MAC_TX_PAUSE_CNT_64K 7 69 70#define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512) 71#define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K) 72#define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K) 73#define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K) 74#define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K) 75#define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K) 76#define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) 77#define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) 78 79#define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) 80 81#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) 82 83#if SIBYTE_HDR_FEATURE_CHIP(1480) 84#define M_MAC_TIMESTAMP _SB_MAKEMASK1(18) 85#endif 86#define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) 87#define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) 88#define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) 89#define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22) 90#define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23) 91#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) 92#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) 93 94#define M_MAC_RESERVED3 _SB_MAKEMASK(6,26) 95 96#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) 97#define M_MAC_HDX_EN _SB_MAKEMASK1(33) 98 99#define S_MAC_SPEED_SEL _SB_MAKE64(34) 100#define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL) 101#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL) 102#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL) 103 104#define K_MAC_SPEED_SEL_10MBPS 0 105#define K_MAC_SPEED_SEL_100MBPS 1 106#define K_MAC_SPEED_SEL_1000MBPS 2 107#define K_MAC_SPEED_SEL_RESERVED 3 108 109#define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS) 110#define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS) 111#define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS) 112#define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED) 113 114#define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36) 115#define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37) 116#define M_MAC_FAST_SYNC _SB_MAKEMASK1(38) 117#define M_MAC_SS_EN _SB_MAKEMASK1(39) 118 119#define S_MAC_BYPASS_CFG _SB_MAKE64(40) 120#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG) 121#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG) 122#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG) 123 124#define K_MAC_BYPASS_GMII 0 125#define K_MAC_BYPASS_ENCODED 1 126#define K_MAC_BYPASS_SOP 2 127#define K_MAC_BYPASS_EOP 3 128 129#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) 130#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) 131 132#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 133 SIBYTE_HDR_FEATURE_CHIP(1480) 134#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) 135#endif /* 1250 PASS2 || 112x PASS1 || 1480*/ 136 137#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 138 SIBYTE_HDR_FEATURE_CHIP(1480) 139#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) 140#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 141 142#define S_MAC_BYPASS_IFG _SB_MAKE64(46) 143#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) 144#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG) 145#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG) 146 147#define K_MAC_FC_CMD_DISABLED 0 148#define K_MAC_FC_CMD_ENABLED 1 149#define K_MAC_FC_CMD_ENAB_FALSECARR 2 150 151#define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED) 152#define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED) 153#define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR) 154 155#define M_MAC_FC_SEL _SB_MAKEMASK1(54) 156 157#define S_MAC_FC_CMD _SB_MAKE64(55) 158#define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD) 159#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD) 160#define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD) 161 162#define S_MAC_RX_CH_SEL _SB_MAKE64(57) 163#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL) 164#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL) 165#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL) 166 167 168/* 169 * MAC Enable Registers 170 * Register: MAC_ENABLE_0 171 * Register: MAC_ENABLE_1 172 * Register: MAC_ENABLE_2 173 */ 174 175#define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0) 176#define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1) 177#define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4) 178#define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5) 179 180#define M_MAC_PORT_RESET _SB_MAKEMASK1(8) 181 182#if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) 183#define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) 184#define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) 185#define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) 186#define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) 187#endif 188 189/* 190 * MAC reset information register (1280/1255) 191 */ 192#if SIBYTE_HDR_FEATURE_CHIP(1480) 193#define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8) 194#define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16) 195#define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24) 196#define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32) 197#endif 198 199/* 200 * MAC DMA Control Register 201 * Register: MAC_TXD_CTL_0 202 * Register: MAC_TXD_CTL_1 203 * Register: MAC_TXD_CTL_2 204 */ 205 206#define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) 207#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0) 208#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0) 209#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0) 210 211#define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) 212#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1) 213#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1) 214#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1) 215 216/* 217 * MAC Fifo Threshhold registers (Table 9-14) 218 * Register: MAC_THRSH_CFG_0 219 * Register: MAC_THRSH_CFG_1 220 * Register: MAC_THRSH_CFG_2 221 */ 222 223#define S_MAC_TX_WR_THRSH _SB_MAKE64(0) 224#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 225/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ 226#endif /* up to 1250 PASS1 */ 227#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 228 SIBYTE_HDR_FEATURE_CHIP(1480) 229#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) 230#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 231#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) 232#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) 233 234#define S_MAC_TX_RD_THRSH _SB_MAKE64(8) 235#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 236/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ 237#endif /* up to 1250 PASS1 */ 238#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 239 SIBYTE_HDR_FEATURE_CHIP(1480) 240#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) 241#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 242#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) 243#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) 244 245#define S_MAC_TX_RL_THRSH _SB_MAKE64(16) 246#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH) 247#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH) 248#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH) 249 250#define S_MAC_RX_PL_THRSH _SB_MAKE64(24) 251#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH) 252#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH) 253#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH) 254 255#define S_MAC_RX_RD_THRSH _SB_MAKE64(32) 256#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH) 257#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH) 258#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH) 259 260#define S_MAC_RX_RL_THRSH _SB_MAKE64(40) 261#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH) 262#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) 263#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) 264 265#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 266 SIBYTE_HDR_FEATURE_CHIP(1480) 267#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) 268#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) 269#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) 270#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) 271#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 272 273/* 274 * MAC Frame Configuration Registers (Table 9-15) 275 * Register: MAC_FRAME_CFG_0 276 * Register: MAC_FRAME_CFG_1 277 * Register: MAC_FRAME_CFG_2 278 */ 279 280/* XXXCGD: ??? Unused in pass2? */ 281#define S_MAC_IFG_RX _SB_MAKE64(0) 282#define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX) 283#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) 284#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) 285 286#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 287 SIBYTE_HDR_FEATURE_CHIP(1480) 288#define S_MAC_PRE_LEN _SB_MAKE64(0) 289#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) 290#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) 291#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) 292#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 293 294#define S_MAC_IFG_TX _SB_MAKE64(6) 295#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) 296#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX) 297#define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX) 298 299#define S_MAC_IFG_THRSH _SB_MAKE64(12) 300#define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH) 301#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH) 302#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH) 303 304#define S_MAC_BACKOFF_SEL _SB_MAKE64(18) 305#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL) 306#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL) 307#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL) 308 309#define S_MAC_LFSR_SEED _SB_MAKE64(22) 310#define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED) 311#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED) 312#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED) 313 314#define S_MAC_SLOT_SIZE _SB_MAKE64(30) 315#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE) 316#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE) 317#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE) 318 319#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) 320#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ) 321#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ) 322#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ) 323 324#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) 325#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ) 326#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ) 327#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ) 328 329/* 330 * These constants are used to configure the fields within the Frame 331 * Configuration Register. 332 */ 333 334#define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ 335#define K_MAC_IFG_RX_100 _SB_MAKE64(0) 336#define K_MAC_IFG_RX_1000 _SB_MAKE64(0) 337 338#define K_MAC_IFG_TX_10 _SB_MAKE64(20) 339#define K_MAC_IFG_TX_100 _SB_MAKE64(20) 340#define K_MAC_IFG_TX_1000 _SB_MAKE64(8) 341 342#define K_MAC_IFG_THRSH_10 _SB_MAKE64(4) 343#define K_MAC_IFG_THRSH_100 _SB_MAKE64(4) 344#define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0) 345 346#define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) 347#define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) 348#define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) 349 350#define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10) 351#define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100) 352#define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000) 353 354#define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10) 355#define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100) 356#define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000) 357 358#define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10) 359#define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100) 360#define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000) 361 362#define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10) 363#define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100) 364#define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000) 365 366#define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9) 367#define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64) 368#define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518) 369#define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216) 370 371#define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO) 372#define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT) 373#define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT) 374#define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO) 375 376/* 377 * MAC VLAN Tag Registers (Table 9-16) 378 * Register: MAC_VLANTAG_0 379 * Register: MAC_VLANTAG_1 380 * Register: MAC_VLANTAG_2 381 */ 382 383#define S_MAC_VLAN_TAG _SB_MAKE64(0) 384#define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG) 385#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG) 386#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG) 387 388#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 389#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) 390#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET) 391#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET) 392#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET) 393 394#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) 395#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET) 396#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET) 397#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET) 398 399#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) 400#endif /* 1250 PASS3 || 112x PASS1 */ 401 402/* 403 * MAC Status Registers (Table 9-17) 404 * Also used for the MAC Interrupt Mask Register (Table 9-18) 405 * Register: MAC_STATUS_0 406 * Register: MAC_STATUS_1 407 * Register: MAC_STATUS_2 408 * Register: MAC_INT_MASK_0 409 * Register: MAC_INT_MASK_1 410 * Register: MAC_INT_MASK_2 411 */ 412 413/* 414 * Use these constants to shift the appropriate channel 415 * into the CH0 position so the same tests can be used 416 * on each channel. 417 */ 418 419#define S_MAC_RX_CH0 _SB_MAKE64(0) 420#define S_MAC_RX_CH1 _SB_MAKE64(8) 421#define S_MAC_TX_CH0 _SB_MAKE64(16) 422#define S_MAC_TX_CH1 _SB_MAKE64(24) 423 424#define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */ 425#define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ 426 427/* 428 * These are the same as RX channel 0. The idea here 429 * is that you'll use one of the "S_" things above 430 * and pass just the six bits to a DMA-channel-specific ISR 431 */ 432#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0) 433#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) 434#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) 435#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) 436#define M_MAC_INT_HWM _SB_MAKEMASK1(3) 437#define M_MAC_INT_LWM _SB_MAKEMASK1(4) 438#define M_MAC_INT_DSCR _SB_MAKEMASK1(5) 439#define M_MAC_INT_ERR _SB_MAKEMASK1(6) 440#define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */ 441#define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */ 442 443/* 444 * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see 445 * also DMA_TX/DMA_RX in sb_regs.h). 446 */ 447#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) 448 449#define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx)) 450#define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 451#define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 452#define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 453#define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 454#define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 455#define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 456#define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 457#define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 458#define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 459#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40) 460 461 462#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) 463#define M_MAC_RX_OVRFL _SB_MAKEMASK1(41) 464#define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42) 465#define M_MAC_TX_OVRFL _SB_MAKEMASK1(43) 466#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) 467#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) 468#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) 469#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 470 SIBYTE_HDR_FEATURE_CHIP(1480) 471#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ 472#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 473 474#define S_MAC_COUNTER_ADDR _SB_MAKE64(47) 475#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) 476#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) 477#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) 478 479#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 480 SIBYTE_HDR_FEATURE_CHIP(1480) 481#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) 482#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 483 484/* 485 * MAC Fifo Pointer Registers (Table 9-19) [Debug register] 486 * Register: MAC_FIFO_PTRS_0 487 * Register: MAC_FIFO_PTRS_1 488 * Register: MAC_FIFO_PTRS_2 489 */ 490 491#define S_MAC_TX_WRPTR _SB_MAKE64(0) 492#define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR) 493#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR) 494#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR) 495 496#define S_MAC_TX_RDPTR _SB_MAKE64(8) 497#define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR) 498#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR) 499#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR) 500 501#define S_MAC_RX_WRPTR _SB_MAKE64(16) 502#define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR) 503#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR) 504#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR) 505 506#define S_MAC_RX_RDPTR _SB_MAKE64(24) 507#define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR) 508#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR) 509#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR) 510 511/* 512 * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] 513 * Register: MAC_EOPCNT_0 514 * Register: MAC_EOPCNT_1 515 * Register: MAC_EOPCNT_2 516 */ 517 518#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) 519#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER) 520#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER) 521#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER) 522 523#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) 524#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER) 525#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER) 526#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER) 527 528/* 529 * MAC Recieve Address Filter Exact Match Registers (Table 9-21) 530 * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 531 * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 532 * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 533 */ 534 535/* No bitfields */ 536 537/* 538 * MAC Receive Address Filter Mask Registers 539 * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1 540 * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1 541 * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1 542 */ 543 544/* No bitfields */ 545 546/* 547 * MAC Recieve Address Filter Hash Match Registers (Table 9-22) 548 * Registers: MAC_HASH0_0 through MAC_HASH7_0 549 * Registers: MAC_HASH0_1 through MAC_HASH7_1 550 * Registers: MAC_HASH0_2 through MAC_HASH7_2 551 */ 552 553/* No bitfields */ 554 555/* 556 * MAC Transmit Source Address Registers (Table 9-23) 557 * Register: MAC_ETHERNET_ADDR_0 558 * Register: MAC_ETHERNET_ADDR_1 559 * Register: MAC_ETHERNET_ADDR_2 560 */ 561 562/* No bitfields */ 563 564/* 565 * MAC Packet Type Configuration Register 566 * Register: MAC_TYPE_CFG_0 567 * Register: MAC_TYPE_CFG_1 568 * Register: MAC_TYPE_CFG_2 569 */ 570 571#define S_TYPECFG_TYPESIZE _SB_MAKE64(16) 572 573#define S_TYPECFG_TYPE0 _SB_MAKE64(0) 574#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0) 575#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0) 576#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0) 577 578#define S_TYPECFG_TYPE1 _SB_MAKE64(0) 579#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1) 580#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1) 581#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1) 582 583#define S_TYPECFG_TYPE2 _SB_MAKE64(0) 584#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2) 585#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2) 586#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2) 587 588#define S_TYPECFG_TYPE3 _SB_MAKE64(0) 589#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3) 590#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3) 591#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3) 592 593/* 594 * MAC Receive Address Filter Control Registers (Table 9-24) 595 * Register: MAC_ADFILTER_CFG_0 596 * Register: MAC_ADFILTER_CFG_1 597 * Register: MAC_ADFILTER_CFG_2 598 */ 599 600#define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0) 601#define M_MAC_UCAST_EN _SB_MAKEMASK1(1) 602#define M_MAC_UCAST_INV _SB_MAKEMASK1(2) 603#define M_MAC_MCAST_EN _SB_MAKEMASK1(3) 604#define M_MAC_MCAST_INV _SB_MAKEMASK1(4) 605#define M_MAC_BCAST_EN _SB_MAKEMASK1(5) 606#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) 607#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 608 SIBYTE_HDR_FEATURE_CHIP(1480) 609#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) 610#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 611 612#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) 613#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) 614#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) 615#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) 616 617#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 618 SIBYTE_HDR_FEATURE_CHIP(1480) 619#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) 620#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) 621#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) 622#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET) 623 624#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) 625#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET) 626#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET) 627#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET) 628 629#define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) 630#define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) 631 632#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) 633#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) 634#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) 635#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) 636#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 637 638/* 639 * MAC Receive Channel Select Registers (Table 9-25) 640 */ 641 642/* no bitfields */ 643 644/* 645 * MAC MII Management Interface Registers (Table 9-26) 646 * Register: MAC_MDIO_0 647 * Register: MAC_MDIO_1 648 * Register: MAC_MDIO_2 649 */ 650 651#define S_MAC_MDC 0 652#define S_MAC_MDIO_DIR 1 653#define S_MAC_MDIO_OUT 2 654#define S_MAC_GENC 3 655#define S_MAC_MDIO_IN 4 656 657#define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC) 658#define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR) 659#define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR) 660#define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT) 661#define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC) 662#define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN) 663 664#endif 665