1/* ********************************************************************* 2 * BCM1280/BCM1480 Board Support Package 3 * 4 * Memory Controller constants File: bcm1480_mc.h 5 * 6 * This module contains constants and macros useful for 7 * programming the memory controller. 8 * 9 * BCM1400 specification level: 1280-UM100-D1 (11/14/03 Review Copy) 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 ********************************************************************* */ 31 32 33#ifndef _BCM1480_MC_H 34#define _BCM1480_MC_H 35 36#include "sb1250_defs.h" 37 38/* 39 * Memory Channel Configuration Register (Table 81) 40 */ 41 42#define S_BCM1480_MC_INTLV0 0 43#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) 44#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) 45#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) 46#define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) 47 48#define S_BCM1480_MC_INTLV1 8 49#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) 50#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) 51#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) 52#define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) 53 54#define S_BCM1480_MC_INTLV2 16 55#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV2) 56#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV2) 57#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV2,M_BCM1480_MC_INTLV2) 58#define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) 59 60#define S_BCM1480_MC_CS_MODE 32 61#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8,S_BCM1480_MC_CS_MODE) 62#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS_MODE) 63#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_CS_MODE,M_BCM1480_MC_CS_MODE) 64#define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) 65 66#define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ 67 V_BCM1480_MC_INTLV1_DEFAULT | \ 68 V_BCM1480_MC_INTLV2_DEFAULT | \ 69 V_BCM1480_MC_CS_MODE_DEFAULT) 70 71#define K_BCM1480_MC_CS01_MODE 0x03 72#define K_BCM1480_MC_CS02_MODE 0x05 73#define K_BCM1480_MC_CS0123_MODE 0x0F 74#define K_BCM1480_MC_CS0246_MODE 0x55 75#define K_BCM1480_MC_CS0145_MODE 0x33 76#define K_BCM1480_MC_CS0167_MODE 0xC3 77#define K_BCM1480_MC_CSFULL_MODE 0xFF 78 79/* 80 * Chip Select Start Address Register (Table 82) 81 */ 82 83#define S_BCM1480_MC_CS0_START 0 84#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12,S_BCM1480_MC_CS0_START) 85#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_START) 86#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_START,M_BCM1480_MC_CS0_START) 87 88#define S_BCM1480_MC_CS1_START 16 89#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12,S_BCM1480_MC_CS1_START) 90#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_START) 91#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_START,M_BCM1480_MC_CS1_START) 92 93#define S_BCM1480_MC_CS2_START 32 94#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12,S_BCM1480_MC_CS2_START) 95#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_START) 96#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_START,M_BCM1480_MC_CS2_START) 97 98#define S_BCM1480_MC_CS3_START 48 99#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12,S_BCM1480_MC_CS3_START) 100#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_START) 101#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_START,M_BCM1480_MC_CS3_START) 102 103/* 104 * Chip Select End Address Register (Table 83) 105 */ 106 107#define S_BCM1480_MC_CS0_END 0 108#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12,S_BCM1480_MC_CS0_END) 109#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_END) 110#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_END,M_BCM1480_MC_CS0_END) 111 112#define S_BCM1480_MC_CS1_END 16 113#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12,S_BCM1480_MC_CS1_END) 114#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_END) 115#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_END,M_BCM1480_MC_CS1_END) 116 117#define S_BCM1480_MC_CS2_END 32 118#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12,S_BCM1480_MC_CS2_END) 119#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_END) 120#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_END,M_BCM1480_MC_CS2_END) 121 122#define S_BCM1480_MC_CS3_END 48 123#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12,S_BCM1480_MC_CS3_END) 124#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_END) 125#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_END,M_BCM1480_MC_CS3_END) 126 127/* 128 * Row Address Bit Select Register 0 (Table 84) 129 */ 130 131#define S_BCM1480_MC_ROW00 0 132#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6,S_BCM1480_MC_ROW00) 133#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW00) 134#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW00,M_BCM1480_MC_ROW00) 135 136#define S_BCM1480_MC_ROW01 8 137#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6,S_BCM1480_MC_ROW01) 138#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW01) 139#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW01,M_BCM1480_MC_ROW01) 140 141#define S_BCM1480_MC_ROW02 16 142#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6,S_BCM1480_MC_ROW02) 143#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW02) 144#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW02,M_BCM1480_MC_ROW02) 145 146#define S_BCM1480_MC_ROW03 24 147#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6,S_BCM1480_MC_ROW03) 148#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW03) 149#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW03,M_BCM1480_MC_ROW03) 150 151#define S_BCM1480_MC_ROW04 32 152#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6,S_BCM1480_MC_ROW04) 153#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW04) 154#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW04,M_BCM1480_MC_ROW04) 155 156#define S_BCM1480_MC_ROW05 40 157#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6,S_BCM1480_MC_ROW05) 158#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW05) 159#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW05,M_BCM1480_MC_ROW05) 160 161#define S_BCM1480_MC_ROW06 48 162#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6,S_BCM1480_MC_ROW06) 163#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW06) 164#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW06,M_BCM1480_MC_ROW06) 165 166#define S_BCM1480_MC_ROW07 56 167#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6,S_BCM1480_MC_ROW07) 168#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW07) 169#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW07,M_BCM1480_MC_ROW07) 170 171/* 172 * Row Address Bit Select Register 1 (Table 85) 173 */ 174 175#define S_BCM1480_MC_ROW08 0 176#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6,S_BCM1480_MC_ROW08) 177#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW08) 178#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW08,M_BCM1480_MC_ROW08) 179 180#define S_BCM1480_MC_ROW09 8 181#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6,S_BCM1480_MC_ROW09) 182#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW09) 183#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW09,M_BCM1480_MC_ROW09) 184 185#define S_BCM1480_MC_ROW10 16 186#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6,S_BCM1480_MC_ROW10) 187#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW10) 188#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW10,M_BCM1480_MC_ROW10) 189 190#define S_BCM1480_MC_ROW11 24 191#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6,S_BCM1480_MC_ROW11) 192#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW11) 193#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW11,M_BCM1480_MC_ROW11) 194 195#define S_BCM1480_MC_ROW12 32 196#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6,S_BCM1480_MC_ROW12) 197#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW12) 198#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW12,M_BCM1480_MC_ROW12) 199 200#define S_BCM1480_MC_ROW13 40 201#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6,S_BCM1480_MC_ROW13) 202#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW13) 203#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW13,M_BCM1480_MC_ROW13) 204 205#define S_BCM1480_MC_ROW14 48 206#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6,S_BCM1480_MC_ROW14) 207#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW14) 208#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW14,M_BCM1480_MC_ROW14) 209 210#define K_BCM1480_MC_ROWX_BIT_SPACING 8 211 212/* 213 * Column Address Bit Select Register 0 (Table 86) 214 */ 215 216#define S_BCM1480_MC_COL00 0 217#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6,S_BCM1480_MC_COL00) 218#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL00) 219#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x,S_BCM1480_MC_COL00,M_BCM1480_MC_COL00) 220 221#define S_BCM1480_MC_COL01 8 222#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6,S_BCM1480_MC_COL01) 223#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL01) 224#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x,S_BCM1480_MC_COL01,M_BCM1480_MC_COL01) 225 226#define S_BCM1480_MC_COL02 16 227#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6,S_BCM1480_MC_COL02) 228#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL02) 229#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x,S_BCM1480_MC_COL02,M_BCM1480_MC_COL02) 230 231#define S_BCM1480_MC_COL03 24 232#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6,S_BCM1480_MC_COL03) 233#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL03) 234#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x,S_BCM1480_MC_COL03,M_BCM1480_MC_COL03) 235 236#define S_BCM1480_MC_COL04 32 237#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6,S_BCM1480_MC_COL04) 238#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL04) 239#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x,S_BCM1480_MC_COL04,M_BCM1480_MC_COL04) 240 241#define S_BCM1480_MC_COL05 40 242#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6,S_BCM1480_MC_COL05) 243#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL05) 244#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05) 245 246#define S_BCM1480_MC_COL06 48 247#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6,S_BCM1480_MC_COL06) 248#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL06) 249#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06) 250 251#define S_BCM1480_MC_COL07 56 252#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6,S_BCM1480_MC_COL07) 253#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL07) 254#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07) 255 256/* 257 * Column Address Bit Select Register 1 (Table 87) 258 */ 259 260#define S_BCM1480_MC_COL08 0 261#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6,S_BCM1480_MC_COL08) 262#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL08) 263#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08) 264 265#define S_BCM1480_MC_COL09 8 266#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6,S_BCM1480_MC_COL09) 267#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL09) 268#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09) 269 270#define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ 271 272#define S_BCM1480_MC_COL11 24 273#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6,S_BCM1480_MC_COL11) 274#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL11) 275#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11) 276 277#define S_BCM1480_MC_COL12 32 278#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6,S_BCM1480_MC_COL12) 279#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL12) 280#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12) 281 282#define S_BCM1480_MC_COL13 40 283#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6,S_BCM1480_MC_COL13) 284#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL13) 285#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13) 286 287#define S_BCM1480_MC_COL14 48 288#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6,S_BCM1480_MC_COL14) 289#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL14) 290#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14) 291 292#define K_BCM1480_MC_COLX_BIT_SPACING 8 293 294/* 295 * CS0 and CS1 Bank Address Bit Select Register (Table 88) 296 */ 297 298#define S_BCM1480_MC_CS01_BANK0 0 299#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0) 300#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0) 301#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0) 302 303#define S_BCM1480_MC_CS01_BANK1 8 304#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1) 305#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1) 306#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1) 307 308#define S_BCM1480_MC_CS01_BANK2 16 309#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2) 310#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2) 311#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2) 312 313/* 314 * CS2 and CS3 Bank Address Bit Select Register (Table 89) 315 */ 316 317#define S_BCM1480_MC_CS23_BANK0 0 318#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0) 319#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0) 320#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0) 321 322#define S_BCM1480_MC_CS23_BANK1 8 323#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1) 324#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1) 325#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1) 326 327#define S_BCM1480_MC_CS23_BANK2 16 328#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2) 329#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2) 330#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2) 331 332#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 333 334/* 335 * DRAM Command Register (Table 90) 336 */ 337 338#define S_BCM1480_MC_COMMAND 0 339#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND) 340#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND) 341#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND) 342 343#define K_BCM1480_MC_COMMAND_EMRS 0 344#define K_BCM1480_MC_COMMAND_MRS 1 345#define K_BCM1480_MC_COMMAND_PRE 2 346#define K_BCM1480_MC_COMMAND_AR 3 347#define K_BCM1480_MC_COMMAND_SETRFSH 4 348#define K_BCM1480_MC_COMMAND_CLRRFSH 5 349#define K_BCM1480_MC_COMMAND_SETPWRDN 6 350#define K_BCM1480_MC_COMMAND_CLRPWRDN 7 351 352#if SIBYTE_HDR_FEATURE(1480, PASS2) 353#define K_BCM1480_MC_COMMAND_EMRS2 8 354#define K_BCM1480_MC_COMMAND_EMRS3 9 355#define K_BCM1480_MC_COMMAND_ENABLE_MCLK 10 356#define K_BCM1480_MC_COMMAND_DISABLE_MCLK 11 357#endif 358 359#define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS) 360#define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS) 361#define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE) 362#define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR) 363#define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH) 364#define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH) 365#define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN) 366#define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN) 367 368#if SIBYTE_HDR_FEATURE(1480, PASS2) 369#define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2) 370#define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3) 371#define V_BCM1480_MC_COMMAND_ENABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK) 372#define V_BCM1480_MC_COMMAND_DISABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK) 373#endif 374 375#define S_BCM1480_MC_CS0 4 376#define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4) 377#define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5) 378#define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6) 379#define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7) 380#define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8) 381#define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9) 382#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) 383#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) 384 385#define M_BCM1480_MC_CS _SB_MAKEMASK(8,S_BCM1480_MC_CS0) 386#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0) 387#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0,M_BCM1480_MC_CS0) 388 389#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) 390 391/* 392 * DRAM Mode Register (Table 91) 393 */ 394 395#define S_BCM1480_MC_EMODE 0 396#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15,S_BCM1480_MC_EMODE) 397#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE) 398#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE) 399#define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) 400 401#define S_BCM1480_MC_MODE 16 402#define M_BCM1480_MC_MODE _SB_MAKEMASK(15,S_BCM1480_MC_MODE) 403#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MODE) 404#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE) 405#define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) 406 407#define S_BCM1480_MC_DRAM_TYPE 32 408#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE) 409#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE) 410#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE) 411 412#define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 413#define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 414 415#if SIBYTE_HDR_FEATURE(1480, PASS2) 416#define K_BCM1480_MC_DRAM_TYPE_DDR2 2 417#endif 418 419#define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1 0 420 421#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC) 422#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM) 423 424#if SIBYTE_HDR_FEATURE(1480, PASS2) 425#define V_BCM1480_MC_DRAM_TYPE_DDR2 V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2) 426#endif 427 428#define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36) 429#define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37) 430#define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38) 431#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) 432 433#define S_BCM1480_MC_PG_POLICY 40 434#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY) 435#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY) 436#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY) 437 438#define K_BCM1480_MC_PG_POLICY_CLOSED 0 439#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 440 441#define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED) 442#define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) 443 444#if SIBYTE_HDR_FEATURE(1480, PASS2) 445#define M_BCM1480_MC_2T_CMD _SB_MAKEMASK1(42) 446#define M_BCM1480_MC_ECC_COR_DIS _SB_MAKEMASK1(43) 447#endif 448 449#define V_BCM1480_MC_DRAMMODE_DEFAULT V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \ 450 V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) 451 452/* 453 * Memory Clock Configuration Register (Table 92) 454 */ 455 456#define S_BCM1480_MC_CLK_RATIO 0 457#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO) 458#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO) 459#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO) 460 461#define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) 462 463#define S_BCM1480_MC_REF_RATE 8 464#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE) 465#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE) 466#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE) 467 468#define K_BCM1480_MC_REF_RATE_100MHz 0x31 469#define K_BCM1480_MC_REF_RATE_200MHz 0x62 470#define K_BCM1480_MC_REF_RATE_400MHz 0xC4 471 472#define V_BCM1480_MC_REF_RATE_100MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz) 473#define V_BCM1480_MC_REF_RATE_200MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz) 474#define V_BCM1480_MC_REF_RATE_400MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz) 475#define V_BCM1480_MC_REF_RATE_DEFAULT V_BCM1480_MC_REF_RATE_400MHz 476 477#if SIBYTE_HDR_FEATURE(1480, PASS2) 478#define M_BCM1480_MC_AUTO_REF_DIS _SB_MAKEMASK1(16) 479#endif 480 481/* 482 * ODT Register (Table 99) 483 */ 484 485#if SIBYTE_HDR_FEATURE(1480, PASS2) 486#define M_BCM1480_MC_RD_ODT0_CS0 _SB_MAKEMASK1(0) 487#define M_BCM1480_MC_RD_ODT0_CS2 _SB_MAKEMASK1(1) 488#define M_BCM1480_MC_RD_ODT0_CS4 _SB_MAKEMASK1(2) 489#define M_BCM1480_MC_RD_ODT0_CS6 _SB_MAKEMASK1(3) 490#define M_BCM1480_MC_WR_ODT0_CS0 _SB_MAKEMASK1(4) 491#define M_BCM1480_MC_WR_ODT0_CS2 _SB_MAKEMASK1(5) 492#define M_BCM1480_MC_WR_ODT0_CS4 _SB_MAKEMASK1(6) 493#define M_BCM1480_MC_WR_ODT0_CS6 _SB_MAKEMASK1(7) 494#define M_BCM1480_MC_RD_ODT2_CS0 _SB_MAKEMASK1(8) 495#define M_BCM1480_MC_RD_ODT2_CS2 _SB_MAKEMASK1(9) 496#define M_BCM1480_MC_RD_ODT2_CS4 _SB_MAKEMASK1(10) 497#define M_BCM1480_MC_RD_ODT2_CS6 _SB_MAKEMASK1(11) 498#define M_BCM1480_MC_WR_ODT2_CS0 _SB_MAKEMASK1(12) 499#define M_BCM1480_MC_WR_ODT2_CS2 _SB_MAKEMASK1(13) 500#define M_BCM1480_MC_WR_ODT2_CS4 _SB_MAKEMASK1(14) 501#define M_BCM1480_MC_WR_ODT2_CS6 _SB_MAKEMASK1(15) 502#define M_BCM1480_MC_RD_ODT4_CS0 _SB_MAKEMASK1(16) 503#define M_BCM1480_MC_RD_ODT4_CS2 _SB_MAKEMASK1(17) 504#define M_BCM1480_MC_RD_ODT4_CS4 _SB_MAKEMASK1(18) 505#define M_BCM1480_MC_RD_ODT4_CS6 _SB_MAKEMASK1(19) 506#define M_BCM1480_MC_WR_ODT4_CS0 _SB_MAKEMASK1(20) 507#define M_BCM1480_MC_WR_ODT4_CS2 _SB_MAKEMASK1(21) 508#define M_BCM1480_MC_WR_ODT4_CS4 _SB_MAKEMASK1(22) 509#define M_BCM1480_MC_WR_ODT4_CS6 _SB_MAKEMASK1(23) 510#define M_BCM1480_MC_RD_ODT6_CS0 _SB_MAKEMASK1(24) 511#define M_BCM1480_MC_RD_ODT6_CS2 _SB_MAKEMASK1(25) 512#define M_BCM1480_MC_RD_ODT6_CS4 _SB_MAKEMASK1(26) 513#define M_BCM1480_MC_RD_ODT6_CS6 _SB_MAKEMASK1(27) 514#define M_BCM1480_MC_WR_ODT6_CS0 _SB_MAKEMASK1(28) 515#define M_BCM1480_MC_WR_ODT6_CS2 _SB_MAKEMASK1(29) 516#define M_BCM1480_MC_WR_ODT6_CS4 _SB_MAKEMASK1(30) 517#define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31) 518 519#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) 520 521#define S_BCM1480_MC_ODT0 0 522#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8,S_BCM1480_MC_ODT0) 523#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT0) 524 525#define S_BCM1480_MC_ODT2 8 526#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8,S_BCM1480_MC_ODT2) 527#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT2) 528 529#define S_BCM1480_MC_ODT4 16 530#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8,S_BCM1480_MC_ODT4) 531#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT4) 532 533#define S_BCM1480_MC_ODT6 24 534#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8,S_BCM1480_MC_ODT6) 535#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT6) 536#endif 537 538/* 539 * Memory DLL Configuration Register (Table 93) 540 */ 541 542#define S_BCM1480_MC_ADDR_COARSE_ADJ 0 543#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_ADDR_COARSE_ADJ) 544#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ) 545#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ,M_BCM1480_MC_ADDR_COARSE_ADJ) 546#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) 547 548#if SIBYTE_HDR_FEATURE(1480, PASS2) 549#define S_BCM1480_MC_ADDR_FREQ_RANGE 8 550#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FREQ_RANGE) 551#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE) 552#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE,M_BCM1480_MC_ADDR_FREQ_RANGE) 553#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) 554#endif 555 556#define S_BCM1480_MC_ADDR_FINE_ADJ 8 557#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FINE_ADJ) 558#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ) 559#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ,M_BCM1480_MC_ADDR_FINE_ADJ) 560#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) 561 562#define S_BCM1480_MC_DQI_COARSE_ADJ 16 563#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQI_COARSE_ADJ) 564#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ) 565#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ,M_BCM1480_MC_DQI_COARSE_ADJ) 566#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) 567 568#if SIBYTE_HDR_FEATURE(1480, PASS2) 569#define S_BCM1480_MC_DQI_FREQ_RANGE 24 570#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FREQ_RANGE) 571#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE) 572#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE,M_BCM1480_MC_DQI_FREQ_RANGE) 573#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) 574#endif 575 576#define S_BCM1480_MC_DQI_FINE_ADJ 24 577#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FINE_ADJ) 578#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ) 579#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ,M_BCM1480_MC_DQI_FINE_ADJ) 580#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) 581 582#define S_BCM1480_MC_DQO_COARSE_ADJ 32 583#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQO_COARSE_ADJ) 584#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ) 585#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ,M_BCM1480_MC_DQO_COARSE_ADJ) 586#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) 587 588#if SIBYTE_HDR_FEATURE(1480, PASS2) 589#define S_BCM1480_MC_DQO_FREQ_RANGE 40 590#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FREQ_RANGE) 591#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE) 592#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE,M_BCM1480_MC_DQO_FREQ_RANGE) 593#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) 594#endif 595 596#define S_BCM1480_MC_DQO_FINE_ADJ 40 597#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FINE_ADJ) 598#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ) 599#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ,M_BCM1480_MC_DQO_FINE_ADJ) 600#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) 601 602#if SIBYTE_HDR_FEATURE(1480, PASS2) 603#define S_BCM1480_MC_DLL_PDSEL 44 604#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_PDSEL) 605#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_PDSEL) 606#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_PDSEL,M_BCM1480_MC_DLL_PDSEL) 607#define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) 608 609#define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) 610#define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47) 611#endif 612 613#define S_BCM1480_MC_DLL_DEFAULT 48 614#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT) 615#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT) 616#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT) 617#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) 618 619#if SIBYTE_HDR_FEATURE(1480, PASS2) 620#define S_BCM1480_MC_DLL_REGCTRL 54 621#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_REGCTRL) 622#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_REGCTRL) 623#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_REGCTRL,M_BCM1480_MC_DLL_REGCTRL) 624#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) 625#endif 626 627#if SIBYTE_HDR_FEATURE(1480, PASS2) 628#define S_BCM1480_MC_DLL_FREQ_RANGE 56 629#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_FREQ_RANGE) 630#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE) 631#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE,M_BCM1480_MC_DLL_FREQ_RANGE) 632#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) 633#endif 634 635#define S_BCM1480_MC_DLL_STEP_SIZE 56 636#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_STEP_SIZE) 637#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE) 638#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE,M_BCM1480_MC_DLL_STEP_SIZE) 639#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) 640 641#if SIBYTE_HDR_FEATURE(1480, PASS2) 642#define S_BCM1480_MC_DLL_BGCTRL 60 643#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_BGCTRL) 644#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_BGCTRL) 645#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_BGCTRL,M_BCM1480_MC_DLL_BGCTRL) 646#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) 647#endif 648 649#define M_BCM1480_MC_DLL_BYPASS _SB_MAKEMASK1(63) 650 651/* 652 * Memory Drive Configuration Register (Table 94) 653 */ 654 655#define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 656#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLDOWN) 657#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN) 658#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN,M_BCM1480_MC_RTT_BYP_PULLDOWN) 659 660#define S_BCM1480_MC_RTT_BYP_PULLUP 6 661#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLUP) 662#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP) 663#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP,M_BCM1480_MC_RTT_BYP_PULLUP) 664 665#define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) 666#define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) 667 668#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 669#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) 670#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) 671#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN,M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) 672 673#define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 674#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLUP) 675#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP) 676#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP,M_BCM1480_MC_PVT_BYP_C1_PULLUP) 677 678#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20 679#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) 680#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) 681#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN,M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) 682 683#define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 684#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLUP) 685#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP) 686#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP,M_BCM1480_MC_PVT_BYP_C2_PULLUP) 687 688#define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) 689#define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) 690 691#define M_BCM1480_MC_CLK_CLASS _SB_MAKEMASK1(34) 692#define M_BCM1480_MC_DATA_CLASS _SB_MAKEMASK1(35) 693#define M_BCM1480_MC_ADDR_CLASS _SB_MAKEMASK1(36) 694 695#define M_BCM1480_MC_DQ_ODT_75 _SB_MAKEMASK1(37) 696#define M_BCM1480_MC_DQ_ODT_150 _SB_MAKEMASK1(38) 697#define M_BCM1480_MC_DQS_ODT_75 _SB_MAKEMASK1(39) 698#define M_BCM1480_MC_DQS_ODT_150 _SB_MAKEMASK1(40) 699#define M_BCM1480_MC_DQS_DIFF _SB_MAKEMASK1(41) 700 701/* 702 * ECC Test Data Register (Table 95) 703 */ 704 705#define S_BCM1480_MC_DATA_INVERT 0 706#define M_DATA_ECC_INVERT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_INVERT) 707 708/* 709 * ECC Test ECC Register (Table 96) 710 */ 711 712#define S_BCM1480_MC_ECC_INVERT 0 713#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8,S_BCM1480_MC_ECC_INVERT) 714 715/* 716 * SDRAM Timing Register (Table 97) 717 */ 718 719#define S_BCM1480_MC_tRCD 0 720#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4,S_BCM1480_MC_tRCD) 721#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCD) 722#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCD,M_BCM1480_MC_tRCD) 723#define K_BCM1480_MC_tRCD_DEFAULT 3 724#define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) 725 726#define S_BCM1480_MC_tCL 4 727#define M_BCM1480_MC_tCL _SB_MAKEMASK(4,S_BCM1480_MC_tCL) 728#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCL) 729#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x,S_BCM1480_MC_tCL,M_BCM1480_MC_tCL) 730#define K_BCM1480_MC_tCL_DEFAULT 2 731#define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) 732 733#define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) 734 735#define S_BCM1480_MC_tWR 9 736#define M_BCM1480_MC_tWR _SB_MAKEMASK(3,S_BCM1480_MC_tWR) 737#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tWR) 738#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x,S_BCM1480_MC_tWR,M_BCM1480_MC_tWR) 739#define K_BCM1480_MC_tWR_DEFAULT 2 740#define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) 741 742#define S_BCM1480_MC_tCwD 12 743#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4,S_BCM1480_MC_tCwD) 744#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCwD) 745#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x,S_BCM1480_MC_tCwD,M_BCM1480_MC_tCwD) 746#define K_BCM1480_MC_tCwD_DEFAULT 1 747#define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) 748 749#define S_BCM1480_MC_tRP 16 750#define M_BCM1480_MC_tRP _SB_MAKEMASK(4,S_BCM1480_MC_tRP) 751#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRP) 752#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRP,M_BCM1480_MC_tRP) 753#define K_BCM1480_MC_tRP_DEFAULT 4 754#define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) 755 756#define S_BCM1480_MC_tRRD 20 757#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4,S_BCM1480_MC_tRRD) 758#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRRD) 759#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRRD,M_BCM1480_MC_tRRD) 760#define K_BCM1480_MC_tRRD_DEFAULT 2 761#define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) 762 763#define S_BCM1480_MC_tRCw 24 764#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5,S_BCM1480_MC_tRCw) 765#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCw) 766#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCw,M_BCM1480_MC_tRCw) 767#define K_BCM1480_MC_tRCw_DEFAULT 10 768#define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) 769 770#define S_BCM1480_MC_tRCr 32 771#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5,S_BCM1480_MC_tRCr) 772#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCr) 773#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCr,M_BCM1480_MC_tRCr) 774#define K_BCM1480_MC_tRCr_DEFAULT 9 775#define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) 776 777#if SIBYTE_HDR_FEATURE(1480, PASS2) 778#define S_BCM1480_MC_tFAW 40 779#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6,S_BCM1480_MC_tFAW) 780#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFAW) 781#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x,S_BCM1480_MC_tFAW,M_BCM1480_MC_tFAW) 782#define K_BCM1480_MC_tFAW_DEFAULT 0 783#define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) 784#endif 785 786#define S_BCM1480_MC_tRFC 48 787#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7,S_BCM1480_MC_tRFC) 788#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRFC) 789#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x,S_BCM1480_MC_tRFC,M_BCM1480_MC_tRFC) 790#define K_BCM1480_MC_tRFC_DEFAULT 12 791#define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) 792 793#define S_BCM1480_MC_tFIFO 56 794#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2,S_BCM1480_MC_tFIFO) 795#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFIFO) 796#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x,S_BCM1480_MC_tFIFO,M_BCM1480_MC_tFIFO) 797#define K_BCM1480_MC_tFIFO_DEFAULT 0 798#define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) 799 800#define S_BCM1480_MC_tW2R 58 801#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2,S_BCM1480_MC_tW2R) 802#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2R) 803#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2R,M_BCM1480_MC_tW2R) 804#define K_BCM1480_MC_tW2R_DEFAULT 1 805#define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) 806 807#define S_BCM1480_MC_tR2W 60 808#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2,S_BCM1480_MC_tR2W) 809#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tR2W) 810#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tR2W,M_BCM1480_MC_tR2W) 811#define K_BCM1480_MC_tR2W_DEFAULT 0 812#define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) 813 814#define M_BCM1480_MC_tR2R _SB_MAKEMASK1(62) 815 816#define V_BCM1480_MC_TIMING_DEFAULT (M_BCM1480_MC_tR2R | \ 817 V_BCM1480_MC_tFIFO_DEFAULT | \ 818 V_BCM1480_MC_tR2W_DEFAULT | \ 819 V_BCM1480_MC_tW2R_DEFAULT | \ 820 V_BCM1480_MC_tRFC_DEFAULT | \ 821 V_BCM1480_MC_tRCr_DEFAULT | \ 822 V_BCM1480_MC_tRCw_DEFAULT | \ 823 V_BCM1480_MC_tRRD_DEFAULT | \ 824 V_BCM1480_MC_tRP_DEFAULT | \ 825 V_BCM1480_MC_tCwD_DEFAULT | \ 826 V_BCM1480_MC_tWR_DEFAULT | \ 827 M_BCM1480_MC_tCrDh | \ 828 V_BCM1480_MC_tCL_DEFAULT | \ 829 V_BCM1480_MC_tRCD_DEFAULT) 830 831/* 832 * SDRAM Timing Register 2 833 */ 834 835#if SIBYTE_HDR_FEATURE(1480, PASS2) 836 837#define S_BCM1480_MC_tAL 0 838#define M_BCM1480_MC_tAL _SB_MAKEMASK(4,S_BCM1480_MC_tAL) 839#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tAL) 840#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x,S_BCM1480_MC_tAL,M_BCM1480_MC_tAL) 841#define K_BCM1480_MC_tAL_DEFAULT 0 842#define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) 843 844#define S_BCM1480_MC_tRTP 4 845#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3,S_BCM1480_MC_tRTP) 846#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRTP) 847#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRTP,M_BCM1480_MC_tRTP) 848#define K_BCM1480_MC_tRTP_DEFAULT 2 849#define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) 850 851#define S_BCM1480_MC_tW2W 8 852#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2,S_BCM1480_MC_tW2W) 853#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2W) 854#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2W,M_BCM1480_MC_tW2W) 855#define K_BCM1480_MC_tW2W_DEFAULT 0 856#define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) 857 858#define S_BCM1480_MC_tRAP 12 859#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4,S_BCM1480_MC_tRAP) 860#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRAP) 861#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRAP,M_BCM1480_MC_tRAP) 862#define K_BCM1480_MC_tRAP_DEFAULT 0 863#define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) 864 865#endif 866 867 868 869/* 870 * Global Registers: single instances per BCM1480 871 */ 872 873/* 874 * Global Configuration Register (Table 99) 875 */ 876 877#define S_BCM1480_MC_BLK_SET_MARK 8 878#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_SET_MARK) 879#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_SET_MARK) 880#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_SET_MARK,M_BCM1480_MC_BLK_SET_MARK) 881 882#define S_BCM1480_MC_BLK_CLR_MARK 12 883#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_CLR_MARK) 884#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_CLR_MARK) 885#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_CLR_MARK,M_BCM1480_MC_BLK_CLR_MARK) 886 887#define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) 888 889#define S_BCM1480_MC_MAX_AGE 20 890#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4,S_BCM1480_MC_MAX_AGE) 891#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MAX_AGE) 892#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x,S_BCM1480_MC_MAX_AGE,M_BCM1480_MC_MAX_AGE) 893 894#define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) 895#define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) 896#define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) 897 898#define S_BCM1480_MC_SLEW 33 899#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2,S_BCM1480_MC_SLEW) 900#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_SLEW) 901#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x,S_BCM1480_MC_SLEW,M_BCM1480_MC_SLEW) 902 903#define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) 904 905/* 906 * Global Channel Interleave Register (Table 100) 907 */ 908 909#define S_BCM1480_MC_INTLV0 0 910#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) 911#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) 912#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) 913 914#define S_BCM1480_MC_INTLV1 8 915#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) 916#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) 917#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) 918 919#define S_BCM1480_MC_INTLV_MODE 16 920#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3,S_BCM1480_MC_INTLV_MODE) 921#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV_MODE) 922#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV_MODE,M_BCM1480_MC_INTLV_MODE) 923 924#define K_BCM1480_MC_INTLV_MODE_NONE 0x0 925#define K_BCM1480_MC_INTLV_MODE_01 0x1 926#define K_BCM1480_MC_INTLV_MODE_23 0x2 927#define K_BCM1480_MC_INTLV_MODE_01_23 0x3 928#define K_BCM1480_MC_INTLV_MODE_0123 0x4 929 930#define V_BCM1480_MC_INTLV_MODE_NONE V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE) 931#define V_BCM1480_MC_INTLV_MODE_01 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01) 932#define V_BCM1480_MC_INTLV_MODE_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23) 933#define V_BCM1480_MC_INTLV_MODE_01_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23) 934#define V_BCM1480_MC_INTLV_MODE_0123 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123) 935 936/* 937 * ECC Status Register 938 */ 939 940#define S_BCM1480_MC_ECC_ERR_ADDR 0 941#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_ERR_ADDR) 942#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR) 943#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR,M_BCM1480_MC_ECC_ERR_ADDR) 944 945#if SIBYTE_HDR_FEATURE(1480, PASS2) 946#define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) 947#endif 948 949#define M_BCM1480_MC_ECC_MULT_ERR_DET _SB_MAKEMASK1(61) 950#define M_BCM1480_MC_ECC_UERR_DET _SB_MAKEMASK1(62) 951#define M_BCM1480_MC_ECC_CERR_DET _SB_MAKEMASK1(63) 952 953/* 954 * Global ECC Address Register (Table 102) 955 */ 956 957#define S_BCM1480_MC_ECC_CORR_ADDR 0 958#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_CORR_ADDR) 959#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR) 960#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR,M_BCM1480_MC_ECC_CORR_ADDR) 961 962/* 963 * Global ECC Correction Register (Table 103) 964 */ 965 966#define S_BCM1480_MC_ECC_CORRECT 0 967#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_CORRECT) 968#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORRECT) 969#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORRECT,M_BCM1480_MC_ECC_CORRECT) 970 971/* 972 * Global ECC Performance Counters Control Register (Table 104) 973 */ 974 975#define S_BCM1480_MC_CHANNEL_SELECT 0 976#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4,S_BCM1480_MC_CHANNEL_SELECT) 977#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CHANNEL_SELECT) 978#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x,S_BCM1480_MC_CHANNEL_SELECT,M_BCM1480_MC_CHANNEL_SELECT) 979#define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 980#define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 981#define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 982#define K_BCM1480_MC_CHANNEL_SELECT_3 0x8 983 984#endif /* _BCM1480_MC_H */ 985