1/* 2 * AMD Alchemy Semi PB1550 Referrence Board 3 * Board Registers defines. 4 * 5 * Copyright 2004 Embedded Edge LLC. 6 * Copyright 2005 Ralf Baechle (ralf@linux-mips.org) 7 * 8 * ######################################################################## 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 22 * 23 * ######################################################################## 24 * 25 * 26 */ 27#ifndef __ASM_PB1550_H 28#define __ASM_PB1550_H 29 30#include <linux/types.h> 31 32#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 33#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 34#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX 35#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX 36 37#define SPI_PSC_BASE PSC0_BASE_ADDR 38#define AC97_PSC_BASE PSC1_BASE_ADDR 39#define SMBUS_PSC_BASE PSC2_BASE_ADDR 40#define I2S_PSC_BASE PSC3_BASE_ADDR 41 42#define BCSR_PHYS_ADDR 0xAF000000 43 44typedef volatile struct 45{ 46 /*00*/ u16 whoami; 47 u16 reserved0; 48 /*04*/ u16 status; 49 u16 reserved1; 50 /*08*/ u16 switches; 51 u16 reserved2; 52 /*0C*/ u16 resets; 53 u16 reserved3; 54 /*10*/ u16 pcmcia; 55 u16 reserved4; 56 /*14*/ u16 pci; 57 u16 reserved5; 58 /*18*/ u16 leds; 59 u16 reserved6; 60 /*1C*/ u16 system; 61 u16 reserved7; 62 63} BCSR; 64 65static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR; 66 67/* 68 * Register bit definitions for the BCSRs 69 */ 70#define BCSR_WHOAMI_DCID 0x000F 71#define BCSR_WHOAMI_CPLD 0x00F0 72#define BCSR_WHOAMI_BOARD 0x0F00 73 74#define BCSR_STATUS_PCMCIA0VS 0x0003 75#define BCSR_STATUS_PCMCIA1VS 0x000C 76#define BCSR_STATUS_PCMCIA0FI 0x0010 77#define BCSR_STATUS_PCMCIA1FI 0x0020 78#define BCSR_STATUS_SWAPBOOT 0x0040 79#define BCSR_STATUS_SRAMWIDTH 0x0080 80#define BCSR_STATUS_FLASHBUSY 0x0100 81#define BCSR_STATUS_ROMBUSY 0x0200 82#define BCSR_STATUS_USBOTGID 0x0800 83#define BCSR_STATUS_U0RXD 0x1000 84#define BCSR_STATUS_U1RXD 0x2000 85#define BCSR_STATUS_U3RXD 0x8000 86 87#define BCSR_SWITCHES_OCTAL 0x00FF 88#define BCSR_SWITCHES_DIP_1 0x0080 89#define BCSR_SWITCHES_DIP_2 0x0040 90#define BCSR_SWITCHES_DIP_3 0x0020 91#define BCSR_SWITCHES_DIP_4 0x0010 92#define BCSR_SWITCHES_DIP_5 0x0008 93#define BCSR_SWITCHES_DIP_6 0x0004 94#define BCSR_SWITCHES_DIP_7 0x0002 95#define BCSR_SWITCHES_DIP_8 0x0001 96#define BCSR_SWITCHES_ROTARY 0x0F00 97 98#define BCSR_RESETS_PHY0 0x0001 99#define BCSR_RESETS_PHY1 0x0002 100#define BCSR_RESETS_DC 0x0004 101#define BCSR_RESETS_WSC 0x2000 102#define BCSR_RESETS_SPISEL 0x4000 103#define BCSR_RESETS_DMAREQ 0x8000 104 105#define BCSR_PCMCIA_PC0VPP 0x0003 106#define BCSR_PCMCIA_PC0VCC 0x000C 107#define BCSR_PCMCIA_PC0DRVEN 0x0010 108#define BCSR_PCMCIA_PC0RST 0x0080 109#define BCSR_PCMCIA_PC1VPP 0x0300 110#define BCSR_PCMCIA_PC1VCC 0x0C00 111#define BCSR_PCMCIA_PC1DRVEN 0x1000 112#define BCSR_PCMCIA_PC1RST 0x8000 113 114#define BCSR_PCI_M66EN 0x0001 115#define BCSR_PCI_M33 0x0100 116#define BCSR_PCI_EXTERNARB 0x0200 117#define BCSR_PCI_GPIO200RST 0x0400 118#define BCSR_PCI_CLKOUT 0x0800 119#define BCSR_PCI_CFGHOST 0x1000 120 121#define BCSR_LEDS_DECIMALS 0x00FF 122#define BCSR_LEDS_LED0 0x0100 123#define BCSR_LEDS_LED1 0x0200 124#define BCSR_LEDS_LED2 0x0400 125#define BCSR_LEDS_LED3 0x0800 126 127#define BCSR_SYSTEM_VDDI 0x001F 128#define BCSR_SYSTEM_POWEROFF 0x4000 129#define BCSR_SYSTEM_RESET 0x8000 130 131#define PCMCIA_MAX_SOCK 1 132#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 133 134/* VPP/VCC */ 135#define SET_VCC_VPP(VCC, VPP, SLOT)\ 136 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 137 138#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) 139#define PB1550_BOTH_BANKS 140#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER) 141#define PB1550_BOOT_ONLY 142#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) 143#define PB1550_USER_ONLY 144#endif 145 146/* Timing values as described in databook, * ns value stripped of 147 * lower 2 bits. 148 * These defines are here rather than an SOC1550 generic file because 149 * the parts chosen on another board may be different and may require 150 * different timings. 151 */ 152#define NAND_T_H (18 >> 2) 153#define NAND_T_PUL (30 >> 2) 154#define NAND_T_SU (30 >> 2) 155#define NAND_T_WH (30 >> 2) 156 157/* Bitfield shift amounts */ 158#define NAND_T_H_SHIFT 0 159#define NAND_T_PUL_SHIFT 4 160#define NAND_T_SU_SHIFT 8 161#define NAND_T_WH_SHIFT 12 162 163#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ 164 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ 165 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 166 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) 167 168#define NAND_CS 1 169 170/* should be done by yamon */ 171#define NAND_STCFG 0x00400005 /* 8-bit NAND */ 172#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */ 173#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ 174 175#endif /* __ASM_PB1550_H */ 176