1/* 2 * 3 * BRIEF MODULE DESCRIPTION 4 * Include file for Alchemy Semiconductor's Au1k CPU. 5 * 6 * Copyright 2000,2001 MontaVista Software Inc. 7 * Author: MontaVista Software, Inc. 8 * ppopov@mvista.com or source@mvista.com 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * You should have received a copy of the GNU General Public License along 27 * with this program; if not, write to the Free Software Foundation, Inc., 28 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 */ 30 31 /* 32 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp 33 */ 34 35#ifndef _AU1000_H_ 36#define _AU1000_H_ 37 38 39#ifndef _LANGUAGE_ASSEMBLY 40 41#include <linux/delay.h> 42#include <linux/types.h> 43#include <asm/io.h> 44 45/* cpu pipeline flush */ 46void static inline au_sync(void) 47{ 48 __asm__ volatile ("sync"); 49} 50 51void static inline au_sync_udelay(int us) 52{ 53 __asm__ volatile ("sync"); 54 udelay(us); 55} 56 57void static inline au_sync_delay(int ms) 58{ 59 __asm__ volatile ("sync"); 60 mdelay(ms); 61} 62 63void static inline au_writeb(u8 val, unsigned long reg) 64{ 65 *(volatile u8 *)(reg) = val; 66} 67 68void static inline au_writew(u16 val, unsigned long reg) 69{ 70 *(volatile u16 *)(reg) = val; 71} 72 73void static inline au_writel(u32 val, unsigned long reg) 74{ 75 *(volatile u32 *)(reg) = val; 76} 77 78static inline u8 au_readb(unsigned long reg) 79{ 80 return (*(volatile u8 *)reg); 81} 82 83static inline u16 au_readw(unsigned long reg) 84{ 85 return (*(volatile u16 *)reg); 86} 87 88static inline u32 au_readl(unsigned long reg) 89{ 90 return (*(volatile u32 *)reg); 91} 92 93 94static __inline__ int au_ffz(unsigned int x) 95{ 96 if ((x = ~x) == 0) 97 return 32; 98 return __ilog2(x & -x); 99} 100 101/* 102 * ffs: find first bit set. This is defined the same way as 103 * the libc and compiler builtin ffs routines, therefore 104 * differs in spirit from the above ffz (man ffs). 105 */ 106static __inline__ int au_ffs(int x) 107{ 108 return __ilog2(x & -x) + 1; 109} 110 111/* arch/mips/au1000/common/clocks.c */ 112extern void set_au1x00_speed(unsigned int new_freq); 113extern unsigned int get_au1x00_speed(void); 114extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); 115extern unsigned long get_au1x00_uart_baud_base(void); 116extern void set_au1x00_lcd_clock(void); 117extern unsigned int get_au1x00_lcd_clock(void); 118 119/* 120 * Every board describes its IRQ mapping with this table. 121 */ 122typedef struct au1xxx_irqmap { 123 int im_irq; 124 int im_type; 125 int im_request; 126} au1xxx_irq_map_t; 127 128/* 129 * init_IRQ looks for a table with this name. 130 */ 131extern au1xxx_irq_map_t au1xxx_irq_map[]; 132 133#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 134 135#ifdef CONFIG_PM 136/* no CP0 timer irq */ 137#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) 138#else 139#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) 140#endif 141 142/* 143 * SDRAM Register Offsets 144 */ 145#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \ 146 defined(CONFIG_SOC_AU1100) 147#define MEM_SDMODE0 (0x0000) 148#define MEM_SDMODE1 (0x0004) 149#define MEM_SDMODE2 (0x0008) 150#define MEM_SDADDR0 (0x000C) 151#define MEM_SDADDR1 (0x0010) 152#define MEM_SDADDR2 (0x0014) 153#define MEM_SDREFCFG (0x0018) 154#define MEM_SDPRECMD (0x001C) 155#define MEM_SDAUTOREF (0x0020) 156#define MEM_SDWRMD0 (0x0024) 157#define MEM_SDWRMD1 (0x0028) 158#define MEM_SDWRMD2 (0x002C) 159#define MEM_SDSLEEP (0x0030) 160#define MEM_SDSMCKE (0x0034) 161 162/* 163 * MEM_SDMODE register content definitions 164 */ 165#define MEM_SDMODE_F (1<<22) 166#define MEM_SDMODE_SR (1<<21) 167#define MEM_SDMODE_BS (1<<20) 168#define MEM_SDMODE_RS (3<<18) 169#define MEM_SDMODE_CS (7<<15) 170#define MEM_SDMODE_TRAS (15<<11) 171#define MEM_SDMODE_TMRD (3<<9) 172#define MEM_SDMODE_TWR (3<<7) 173#define MEM_SDMODE_TRP (3<<5) 174#define MEM_SDMODE_TRCD (3<<3) 175#define MEM_SDMODE_TCL (7<<0) 176 177#define MEM_SDMODE_BS_2Bank (0<<20) 178#define MEM_SDMODE_BS_4Bank (1<<20) 179#define MEM_SDMODE_RS_11Row (0<<18) 180#define MEM_SDMODE_RS_12Row (1<<18) 181#define MEM_SDMODE_RS_13Row (2<<18) 182#define MEM_SDMODE_RS_N(N) ((N)<<18) 183#define MEM_SDMODE_CS_7Col (0<<15) 184#define MEM_SDMODE_CS_8Col (1<<15) 185#define MEM_SDMODE_CS_9Col (2<<15) 186#define MEM_SDMODE_CS_10Col (3<<15) 187#define MEM_SDMODE_CS_11Col (4<<15) 188#define MEM_SDMODE_CS_N(N) ((N)<<15) 189#define MEM_SDMODE_TRAS_N(N) ((N)<<11) 190#define MEM_SDMODE_TMRD_N(N) ((N)<<9) 191#define MEM_SDMODE_TWR_N(N) ((N)<<7) 192#define MEM_SDMODE_TRP_N(N) ((N)<<5) 193#define MEM_SDMODE_TRCD_N(N) ((N)<<3) 194#define MEM_SDMODE_TCL_N(N) ((N)<<0) 195 196/* 197 * MEM_SDADDR register contents definitions 198 */ 199#define MEM_SDADDR_E (1<<20) 200#define MEM_SDADDR_CSBA (0x03FF<<10) 201#define MEM_SDADDR_CSMASK (0x03FF<<0) 202#define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12) 203#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22) 204 205/* 206 * MEM_SDREFCFG register content definitions 207 */ 208#define MEM_SDREFCFG_TRC (15<<28) 209#define MEM_SDREFCFG_TRPM (3<<26) 210#define MEM_SDREFCFG_E (1<<25) 211#define MEM_SDREFCFG_RE (0x1ffffff<<0) 212#define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC) 213#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM) 214#define MEM_SDREFCFG_REF_N(N) (N) 215#endif 216 217/***********************************************************************/ 218 219/* 220 * Au1550 SDRAM Register Offsets 221 */ 222 223/***********************************************************************/ 224 225#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 226#define MEM_SDMODE0 (0x0800) 227#define MEM_SDMODE1 (0x0808) 228#define MEM_SDMODE2 (0x0810) 229#define MEM_SDADDR0 (0x0820) 230#define MEM_SDADDR1 (0x0828) 231#define MEM_SDADDR2 (0x0830) 232#define MEM_SDCONFIGA (0x0840) 233#define MEM_SDCONFIGB (0x0848) 234#define MEM_SDSTAT (0x0850) 235#define MEM_SDERRADDR (0x0858) 236#define MEM_SDSTRIDE0 (0x0860) 237#define MEM_SDSTRIDE1 (0x0868) 238#define MEM_SDSTRIDE2 (0x0870) 239#define MEM_SDWRMD0 (0x0880) 240#define MEM_SDWRMD1 (0x0888) 241#define MEM_SDWRMD2 (0x0890) 242#define MEM_SDPRECMD (0x08C0) 243#define MEM_SDAUTOREF (0x08C8) 244#define MEM_SDSREF (0x08D0) 245#define MEM_SDSLEEP MEM_SDSREF 246 247#endif 248 249/* 250 * Physical base addresses for integrated peripherals 251 */ 252 253#ifdef CONFIG_SOC_AU1000 254#define MEM_PHYS_ADDR 0x14000000 255#define STATIC_MEM_PHYS_ADDR 0x14001000 256#define DMA0_PHYS_ADDR 0x14002000 257#define DMA1_PHYS_ADDR 0x14002100 258#define DMA2_PHYS_ADDR 0x14002200 259#define DMA3_PHYS_ADDR 0x14002300 260#define DMA4_PHYS_ADDR 0x14002400 261#define DMA5_PHYS_ADDR 0x14002500 262#define DMA6_PHYS_ADDR 0x14002600 263#define DMA7_PHYS_ADDR 0x14002700 264#define IC0_PHYS_ADDR 0x10400000 265#define IC1_PHYS_ADDR 0x11800000 266#define AC97_PHYS_ADDR 0x10000000 267#define USBH_PHYS_ADDR 0x10100000 268#define USBD_PHYS_ADDR 0x10200000 269#define IRDA_PHYS_ADDR 0x10300000 270#define MAC0_PHYS_ADDR 0x10500000 271#define MAC1_PHYS_ADDR 0x10510000 272#define MACEN_PHYS_ADDR 0x10520000 273#define MACDMA0_PHYS_ADDR 0x14004000 274#define MACDMA1_PHYS_ADDR 0x14004200 275#define I2S_PHYS_ADDR 0x11000000 276#define UART0_PHYS_ADDR 0x11100000 277#define UART1_PHYS_ADDR 0x11200000 278#define UART2_PHYS_ADDR 0x11300000 279#define UART3_PHYS_ADDR 0x11400000 280#define SSI0_PHYS_ADDR 0x11600000 281#define SSI1_PHYS_ADDR 0x11680000 282#define SYS_PHYS_ADDR 0x11900000 283#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 284#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 285#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 286#endif 287 288/********************************************************************/ 289 290#ifdef CONFIG_SOC_AU1500 291#define MEM_PHYS_ADDR 0x14000000 292#define STATIC_MEM_PHYS_ADDR 0x14001000 293#define DMA0_PHYS_ADDR 0x14002000 294#define DMA1_PHYS_ADDR 0x14002100 295#define DMA2_PHYS_ADDR 0x14002200 296#define DMA3_PHYS_ADDR 0x14002300 297#define DMA4_PHYS_ADDR 0x14002400 298#define DMA5_PHYS_ADDR 0x14002500 299#define DMA6_PHYS_ADDR 0x14002600 300#define DMA7_PHYS_ADDR 0x14002700 301#define IC0_PHYS_ADDR 0x10400000 302#define IC1_PHYS_ADDR 0x11800000 303#define AC97_PHYS_ADDR 0x10000000 304#define USBH_PHYS_ADDR 0x10100000 305#define USBD_PHYS_ADDR 0x10200000 306#define PCI_PHYS_ADDR 0x14005000 307#define MAC0_PHYS_ADDR 0x11500000 308#define MAC1_PHYS_ADDR 0x11510000 309#define MACEN_PHYS_ADDR 0x11520000 310#define MACDMA0_PHYS_ADDR 0x14004000 311#define MACDMA1_PHYS_ADDR 0x14004200 312#define I2S_PHYS_ADDR 0x11000000 313#define UART0_PHYS_ADDR 0x11100000 314#define UART3_PHYS_ADDR 0x11400000 315#define GPIO2_PHYS_ADDR 0x11700000 316#define SYS_PHYS_ADDR 0x11900000 317#define PCI_MEM_PHYS_ADDR 0x400000000ULL 318#define PCI_IO_PHYS_ADDR 0x500000000ULL 319#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL 320#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL 321#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 322#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 323#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 324#endif 325 326/********************************************************************/ 327 328#ifdef CONFIG_SOC_AU1100 329#define MEM_PHYS_ADDR 0x14000000 330#define STATIC_MEM_PHYS_ADDR 0x14001000 331#define DMA0_PHYS_ADDR 0x14002000 332#define DMA1_PHYS_ADDR 0x14002100 333#define DMA2_PHYS_ADDR 0x14002200 334#define DMA3_PHYS_ADDR 0x14002300 335#define DMA4_PHYS_ADDR 0x14002400 336#define DMA5_PHYS_ADDR 0x14002500 337#define DMA6_PHYS_ADDR 0x14002600 338#define DMA7_PHYS_ADDR 0x14002700 339#define IC0_PHYS_ADDR 0x10400000 340#define SD0_PHYS_ADDR 0x10600000 341#define SD1_PHYS_ADDR 0x10680000 342#define IC1_PHYS_ADDR 0x11800000 343#define AC97_PHYS_ADDR 0x10000000 344#define USBH_PHYS_ADDR 0x10100000 345#define USBD_PHYS_ADDR 0x10200000 346#define IRDA_PHYS_ADDR 0x10300000 347#define MAC0_PHYS_ADDR 0x10500000 348#define MACEN_PHYS_ADDR 0x10520000 349#define MACDMA0_PHYS_ADDR 0x14004000 350#define MACDMA1_PHYS_ADDR 0x14004200 351#define I2S_PHYS_ADDR 0x11000000 352#define UART0_PHYS_ADDR 0x11100000 353#define UART1_PHYS_ADDR 0x11200000 354#define UART3_PHYS_ADDR 0x11400000 355#define SSI0_PHYS_ADDR 0x11600000 356#define SSI1_PHYS_ADDR 0x11680000 357#define GPIO2_PHYS_ADDR 0x11700000 358#define SYS_PHYS_ADDR 0x11900000 359#define LCD_PHYS_ADDR 0x15000000 360#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 361#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 362#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 363#endif 364 365/***********************************************************************/ 366 367#ifdef CONFIG_SOC_AU1550 368#define MEM_PHYS_ADDR 0x14000000 369#define STATIC_MEM_PHYS_ADDR 0x14001000 370#define IC0_PHYS_ADDR 0x10400000 371#define IC1_PHYS_ADDR 0x11800000 372#define USBH_PHYS_ADDR 0x14020000 373#define USBD_PHYS_ADDR 0x10200000 374#define PCI_PHYS_ADDR 0x14005000 375#define MAC0_PHYS_ADDR 0x10500000 376#define MAC1_PHYS_ADDR 0x10510000 377#define MACEN_PHYS_ADDR 0x10520000 378#define MACDMA0_PHYS_ADDR 0x14004000 379#define MACDMA1_PHYS_ADDR 0x14004200 380#define UART0_PHYS_ADDR 0x11100000 381#define UART1_PHYS_ADDR 0x11200000 382#define UART3_PHYS_ADDR 0x11400000 383#define GPIO2_PHYS_ADDR 0x11700000 384#define SYS_PHYS_ADDR 0x11900000 385#define DDMA_PHYS_ADDR 0x14002000 386#define PE_PHYS_ADDR 0x14008000 387#define PSC0_PHYS_ADDR 0x11A00000 388#define PSC1_PHYS_ADDR 0x11B00000 389#define PSC2_PHYS_ADDR 0x10A00000 390#define PSC3_PHYS_ADDR 0x10B00000 391#define PCI_MEM_PHYS_ADDR 0x400000000ULL 392#define PCI_IO_PHYS_ADDR 0x500000000ULL 393#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL 394#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL 395#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 396#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 397#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 398#endif 399 400/***********************************************************************/ 401 402#ifdef CONFIG_SOC_AU1200 403#define MEM_PHYS_ADDR 0x14000000 404#define STATIC_MEM_PHYS_ADDR 0x14001000 405#define AES_PHYS_ADDR 0x10300000 406#define CIM_PHYS_ADDR 0x14004000 407#define IC0_PHYS_ADDR 0x10400000 408#define IC1_PHYS_ADDR 0x11800000 409#define USBM_PHYS_ADDR 0x14020000 410#define USBH_PHYS_ADDR 0x14020100 411#define UART0_PHYS_ADDR 0x11100000 412#define UART1_PHYS_ADDR 0x11200000 413#define GPIO2_PHYS_ADDR 0x11700000 414#define SYS_PHYS_ADDR 0x11900000 415#define DDMA_PHYS_ADDR 0x14002000 416#define PSC0_PHYS_ADDR 0x11A00000 417#define PSC1_PHYS_ADDR 0x11B00000 418#define SD0_PHYS_ADDR 0x10600000 419#define SD1_PHYS_ADDR 0x10680000 420#define LCD_PHYS_ADDR 0x15000000 421#define SWCNT_PHYS_ADDR 0x1110010C 422#define MAEFE_PHYS_ADDR 0x14012000 423#define MAEBE_PHYS_ADDR 0x14010000 424#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 425#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 426#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 427#endif 428 429 430/* Static Bus Controller */ 431#define MEM_STCFG0 0xB4001000 432#define MEM_STTIME0 0xB4001004 433#define MEM_STADDR0 0xB4001008 434 435#define MEM_STCFG1 0xB4001010 436#define MEM_STTIME1 0xB4001014 437#define MEM_STADDR1 0xB4001018 438 439#define MEM_STCFG2 0xB4001020 440#define MEM_STTIME2 0xB4001024 441#define MEM_STADDR2 0xB4001028 442 443#define MEM_STCFG3 0xB4001030 444#define MEM_STTIME3 0xB4001034 445#define MEM_STADDR3 0xB4001038 446 447#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 448#define MEM_STNDCTL 0xB4001100 449#define MEM_STSTAT 0xB4001104 450 451#define MEM_STNAND_CMD (0x0) 452#define MEM_STNAND_ADDR (0x4) 453#define MEM_STNAND_DATA (0x20) 454#endif 455 456/* Interrupt Controller 0 */ 457#define IC0_CFG0RD 0xB0400040 458#define IC0_CFG0SET 0xB0400040 459#define IC0_CFG0CLR 0xB0400044 460 461#define IC0_CFG1RD 0xB0400048 462#define IC0_CFG1SET 0xB0400048 463#define IC0_CFG1CLR 0xB040004C 464 465#define IC0_CFG2RD 0xB0400050 466#define IC0_CFG2SET 0xB0400050 467#define IC0_CFG2CLR 0xB0400054 468 469#define IC0_REQ0INT 0xB0400054 470#define IC0_SRCRD 0xB0400058 471#define IC0_SRCSET 0xB0400058 472#define IC0_SRCCLR 0xB040005C 473#define IC0_REQ1INT 0xB040005C 474 475#define IC0_ASSIGNRD 0xB0400060 476#define IC0_ASSIGNSET 0xB0400060 477#define IC0_ASSIGNCLR 0xB0400064 478 479#define IC0_WAKERD 0xB0400068 480#define IC0_WAKESET 0xB0400068 481#define IC0_WAKECLR 0xB040006C 482 483#define IC0_MASKRD 0xB0400070 484#define IC0_MASKSET 0xB0400070 485#define IC0_MASKCLR 0xB0400074 486 487#define IC0_RISINGRD 0xB0400078 488#define IC0_RISINGCLR 0xB0400078 489#define IC0_FALLINGRD 0xB040007C 490#define IC0_FALLINGCLR 0xB040007C 491 492#define IC0_TESTBIT 0xB0400080 493 494/* Interrupt Controller 1 */ 495#define IC1_CFG0RD 0xB1800040 496#define IC1_CFG0SET 0xB1800040 497#define IC1_CFG0CLR 0xB1800044 498 499#define IC1_CFG1RD 0xB1800048 500#define IC1_CFG1SET 0xB1800048 501#define IC1_CFG1CLR 0xB180004C 502 503#define IC1_CFG2RD 0xB1800050 504#define IC1_CFG2SET 0xB1800050 505#define IC1_CFG2CLR 0xB1800054 506 507#define IC1_REQ0INT 0xB1800054 508#define IC1_SRCRD 0xB1800058 509#define IC1_SRCSET 0xB1800058 510#define IC1_SRCCLR 0xB180005C 511#define IC1_REQ1INT 0xB180005C 512 513#define IC1_ASSIGNRD 0xB1800060 514#define IC1_ASSIGNSET 0xB1800060 515#define IC1_ASSIGNCLR 0xB1800064 516 517#define IC1_WAKERD 0xB1800068 518#define IC1_WAKESET 0xB1800068 519#define IC1_WAKECLR 0xB180006C 520 521#define IC1_MASKRD 0xB1800070 522#define IC1_MASKSET 0xB1800070 523#define IC1_MASKCLR 0xB1800074 524 525#define IC1_RISINGRD 0xB1800078 526#define IC1_RISINGCLR 0xB1800078 527#define IC1_FALLINGRD 0xB180007C 528#define IC1_FALLINGCLR 0xB180007C 529 530#define IC1_TESTBIT 0xB1800080 531 532/* Interrupt Configuration Modes */ 533#define INTC_INT_DISABLED 0 534#define INTC_INT_RISE_EDGE 0x1 535#define INTC_INT_FALL_EDGE 0x2 536#define INTC_INT_RISE_AND_FALL_EDGE 0x3 537#define INTC_INT_HIGH_LEVEL 0x5 538#define INTC_INT_LOW_LEVEL 0x6 539#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 540 541/* Interrupt Numbers */ 542/* Au1000 */ 543#ifdef CONFIG_SOC_AU1000 544#define AU1000_UART0_INT 0 545#define AU1000_UART1_INT 1 /* au1000 */ 546#define AU1000_UART2_INT 2 /* au1000 */ 547#define AU1000_UART3_INT 3 548#define AU1000_SSI0_INT 4 /* au1000 */ 549#define AU1000_SSI1_INT 5 /* au1000 */ 550#define AU1000_DMA_INT_BASE 6 551#define AU1000_TOY_INT 14 552#define AU1000_TOY_MATCH0_INT 15 553#define AU1000_TOY_MATCH1_INT 16 554#define AU1000_TOY_MATCH2_INT 17 555#define AU1000_RTC_INT 18 556#define AU1000_RTC_MATCH0_INT 19 557#define AU1000_RTC_MATCH1_INT 20 558#define AU1000_RTC_MATCH2_INT 21 559#define AU1000_IRDA_TX_INT 22 /* au1000 */ 560#define AU1000_IRDA_RX_INT 23 /* au1000 */ 561#define AU1000_USB_DEV_REQ_INT 24 562#define AU1000_USB_DEV_SUS_INT 25 563#define AU1000_USB_HOST_INT 26 564#define AU1000_ACSYNC_INT 27 565#define AU1000_MAC0_DMA_INT 28 566#define AU1000_MAC1_DMA_INT 29 567#define AU1000_I2S_UO_INT 30 /* au1000 */ 568#define AU1000_AC97C_INT 31 569#define AU1000_GPIO_0 32 570#define AU1000_GPIO_1 33 571#define AU1000_GPIO_2 34 572#define AU1000_GPIO_3 35 573#define AU1000_GPIO_4 36 574#define AU1000_GPIO_5 37 575#define AU1000_GPIO_6 38 576#define AU1000_GPIO_7 39 577#define AU1000_GPIO_8 40 578#define AU1000_GPIO_9 41 579#define AU1000_GPIO_10 42 580#define AU1000_GPIO_11 43 581#define AU1000_GPIO_12 44 582#define AU1000_GPIO_13 45 583#define AU1000_GPIO_14 46 584#define AU1000_GPIO_15 47 585#define AU1000_GPIO_16 48 586#define AU1000_GPIO_17 49 587#define AU1000_GPIO_18 50 588#define AU1000_GPIO_19 51 589#define AU1000_GPIO_20 52 590#define AU1000_GPIO_21 53 591#define AU1000_GPIO_22 54 592#define AU1000_GPIO_23 55 593#define AU1000_GPIO_24 56 594#define AU1000_GPIO_25 57 595#define AU1000_GPIO_26 58 596#define AU1000_GPIO_27 59 597#define AU1000_GPIO_28 60 598#define AU1000_GPIO_29 61 599#define AU1000_GPIO_30 62 600#define AU1000_GPIO_31 63 601 602#define UART0_ADDR 0xB1100000 603#define UART1_ADDR 0xB1200000 604#define UART2_ADDR 0xB1300000 605#define UART3_ADDR 0xB1400000 606 607#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap 608#define USB_HOST_CONFIG 0xB017fffc 609 610#define AU1000_ETH0_BASE 0xB0500000 611#define AU1000_ETH1_BASE 0xB0510000 612#define AU1000_MAC0_ENABLE 0xB0520000 613#define AU1000_MAC1_ENABLE 0xB0520004 614#define NUM_ETH_INTERFACES 2 615#endif /* CONFIG_SOC_AU1000 */ 616 617/* Au1500 */ 618#ifdef CONFIG_SOC_AU1500 619#define AU1500_UART0_INT 0 620#define AU1000_PCI_INTA 1 /* au1500 */ 621#define AU1000_PCI_INTB 2 /* au1500 */ 622#define AU1500_UART3_INT 3 623#define AU1000_PCI_INTC 4 /* au1500 */ 624#define AU1000_PCI_INTD 5 /* au1500 */ 625#define AU1000_DMA_INT_BASE 6 626#define AU1000_TOY_INT 14 627#define AU1000_TOY_MATCH0_INT 15 628#define AU1000_TOY_MATCH1_INT 16 629#define AU1000_TOY_MATCH2_INT 17 630#define AU1000_RTC_INT 18 631#define AU1000_RTC_MATCH0_INT 19 632#define AU1000_RTC_MATCH1_INT 20 633#define AU1000_RTC_MATCH2_INT 21 634#define AU1500_PCI_ERR_INT 22 635#define AU1000_USB_DEV_REQ_INT 24 636#define AU1000_USB_DEV_SUS_INT 25 637#define AU1000_USB_HOST_INT 26 638#define AU1000_ACSYNC_INT 27 639#define AU1500_MAC0_DMA_INT 28 640#define AU1500_MAC1_DMA_INT 29 641#define AU1000_AC97C_INT 31 642#define AU1000_GPIO_0 32 643#define AU1000_GPIO_1 33 644#define AU1000_GPIO_2 34 645#define AU1000_GPIO_3 35 646#define AU1000_GPIO_4 36 647#define AU1000_GPIO_5 37 648#define AU1000_GPIO_6 38 649#define AU1000_GPIO_7 39 650#define AU1000_GPIO_8 40 651#define AU1000_GPIO_9 41 652#define AU1000_GPIO_10 42 653#define AU1000_GPIO_11 43 654#define AU1000_GPIO_12 44 655#define AU1000_GPIO_13 45 656#define AU1000_GPIO_14 46 657#define AU1000_GPIO_15 47 658#define AU1500_GPIO_200 48 659#define AU1500_GPIO_201 49 660#define AU1500_GPIO_202 50 661#define AU1500_GPIO_203 51 662#define AU1500_GPIO_20 52 663#define AU1500_GPIO_204 53 664#define AU1500_GPIO_205 54 665#define AU1500_GPIO_23 55 666#define AU1500_GPIO_24 56 667#define AU1500_GPIO_25 57 668#define AU1500_GPIO_26 58 669#define AU1500_GPIO_27 59 670#define AU1500_GPIO_28 60 671#define AU1500_GPIO_206 61 672#define AU1500_GPIO_207 62 673#define AU1500_GPIO_208_215 63 674 675/* shortcuts */ 676#define INTA AU1000_PCI_INTA 677#define INTB AU1000_PCI_INTB 678#define INTC AU1000_PCI_INTC 679#define INTD AU1000_PCI_INTD 680 681#define UART0_ADDR 0xB1100000 682#define UART3_ADDR 0xB1400000 683 684#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap 685#define USB_HOST_CONFIG 0xB017fffc 686 687#define AU1500_ETH0_BASE 0xB1500000 688#define AU1500_ETH1_BASE 0xB1510000 689#define AU1500_MAC0_ENABLE 0xB1520000 690#define AU1500_MAC1_ENABLE 0xB1520004 691#define NUM_ETH_INTERFACES 2 692#endif /* CONFIG_SOC_AU1500 */ 693 694/* Au1100 */ 695#ifdef CONFIG_SOC_AU1100 696#define AU1100_UART0_INT 0 697#define AU1100_UART1_INT 1 698#define AU1100_SD_INT 2 699#define AU1100_UART3_INT 3 700#define AU1000_SSI0_INT 4 701#define AU1000_SSI1_INT 5 702#define AU1000_DMA_INT_BASE 6 703#define AU1000_TOY_INT 14 704#define AU1000_TOY_MATCH0_INT 15 705#define AU1000_TOY_MATCH1_INT 16 706#define AU1000_TOY_MATCH2_INT 17 707#define AU1000_RTC_INT 18 708#define AU1000_RTC_MATCH0_INT 19 709#define AU1000_RTC_MATCH1_INT 20 710#define AU1000_RTC_MATCH2_INT 21 711#define AU1000_IRDA_TX_INT 22 712#define AU1000_IRDA_RX_INT 23 713#define AU1000_USB_DEV_REQ_INT 24 714#define AU1000_USB_DEV_SUS_INT 25 715#define AU1000_USB_HOST_INT 26 716#define AU1000_ACSYNC_INT 27 717#define AU1100_MAC0_DMA_INT 28 718#define AU1100_GPIO_208_215 29 719#define AU1100_LCD_INT 30 720#define AU1000_AC97C_INT 31 721#define AU1000_GPIO_0 32 722#define AU1000_GPIO_1 33 723#define AU1000_GPIO_2 34 724#define AU1000_GPIO_3 35 725#define AU1000_GPIO_4 36 726#define AU1000_GPIO_5 37 727#define AU1000_GPIO_6 38 728#define AU1000_GPIO_7 39 729#define AU1000_GPIO_8 40 730#define AU1000_GPIO_9 41 731#define AU1000_GPIO_10 42 732#define AU1000_GPIO_11 43 733#define AU1000_GPIO_12 44 734#define AU1000_GPIO_13 45 735#define AU1000_GPIO_14 46 736#define AU1000_GPIO_15 47 737#define AU1000_GPIO_16 48 738#define AU1000_GPIO_17 49 739#define AU1000_GPIO_18 50 740#define AU1000_GPIO_19 51 741#define AU1000_GPIO_20 52 742#define AU1000_GPIO_21 53 743#define AU1000_GPIO_22 54 744#define AU1000_GPIO_23 55 745#define AU1000_GPIO_24 56 746#define AU1000_GPIO_25 57 747#define AU1000_GPIO_26 58 748#define AU1000_GPIO_27 59 749#define AU1000_GPIO_28 60 750#define AU1000_GPIO_29 61 751#define AU1000_GPIO_30 62 752#define AU1000_GPIO_31 63 753 754#define UART0_ADDR 0xB1100000 755#define UART1_ADDR 0xB1200000 756#define UART3_ADDR 0xB1400000 757 758#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap 759#define USB_HOST_CONFIG 0xB017fffc 760 761#define AU1100_ETH0_BASE 0xB0500000 762#define AU1100_MAC0_ENABLE 0xB0520000 763#define NUM_ETH_INTERFACES 1 764#endif /* CONFIG_SOC_AU1100 */ 765 766#ifdef CONFIG_SOC_AU1550 767#define AU1550_UART0_INT 0 768#define AU1550_PCI_INTA 1 769#define AU1550_PCI_INTB 2 770#define AU1550_DDMA_INT 3 771#define AU1550_CRYPTO_INT 4 772#define AU1550_PCI_INTC 5 773#define AU1550_PCI_INTD 6 774#define AU1550_PCI_RST_INT 7 775#define AU1550_UART1_INT 8 776#define AU1550_UART3_INT 9 777#define AU1550_PSC0_INT 10 778#define AU1550_PSC1_INT 11 779#define AU1550_PSC2_INT 12 780#define AU1550_PSC3_INT 13 781#define AU1000_TOY_INT 14 782#define AU1000_TOY_MATCH0_INT 15 783#define AU1000_TOY_MATCH1_INT 16 784#define AU1000_TOY_MATCH2_INT 17 785#define AU1000_RTC_INT 18 786#define AU1000_RTC_MATCH0_INT 19 787#define AU1000_RTC_MATCH1_INT 20 788#define AU1000_RTC_MATCH2_INT 21 789#define AU1550_NAND_INT 23 790#define AU1550_USB_DEV_REQ_INT 24 791#define AU1550_USB_DEV_SUS_INT 25 792#define AU1550_USB_HOST_INT 26 793#define AU1000_USB_DEV_REQ_INT AU1550_USB_DEV_REQ_INT 794#define AU1000_USB_DEV_SUS_INT AU1550_USB_DEV_SUS_INT 795#define AU1000_USB_HOST_INT AU1550_USB_HOST_INT 796#define AU1550_MAC0_DMA_INT 27 797#define AU1550_MAC1_DMA_INT 28 798#define AU1000_GPIO_0 32 799#define AU1000_GPIO_1 33 800#define AU1000_GPIO_2 34 801#define AU1000_GPIO_3 35 802#define AU1000_GPIO_4 36 803#define AU1000_GPIO_5 37 804#define AU1000_GPIO_6 38 805#define AU1000_GPIO_7 39 806#define AU1000_GPIO_8 40 807#define AU1000_GPIO_9 41 808#define AU1000_GPIO_10 42 809#define AU1000_GPIO_11 43 810#define AU1000_GPIO_12 44 811#define AU1000_GPIO_13 45 812#define AU1000_GPIO_14 46 813#define AU1000_GPIO_15 47 814#define AU1550_GPIO_200 48 815#define AU1500_GPIO_201_205 49 // Logical or of GPIO201:205 816#define AU1500_GPIO_16 50 817#define AU1500_GPIO_17 51 818#define AU1500_GPIO_20 52 819#define AU1500_GPIO_21 53 820#define AU1500_GPIO_22 54 821#define AU1500_GPIO_23 55 822#define AU1500_GPIO_24 56 823#define AU1500_GPIO_25 57 824#define AU1500_GPIO_26 58 825#define AU1500_GPIO_27 59 826#define AU1500_GPIO_28 60 827#define AU1500_GPIO_206 61 828#define AU1500_GPIO_207 62 829#define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218 830 831/* shortcuts */ 832#define INTA AU1550_PCI_INTA 833#define INTB AU1550_PCI_INTB 834#define INTC AU1550_PCI_INTC 835#define INTD AU1550_PCI_INTD 836 837#define UART0_ADDR 0xB1100000 838#define UART1_ADDR 0xB1200000 839#define UART3_ADDR 0xB1400000 840 841#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap 842#define USB_OHCI_LEN 0x00060000 843#define USB_HOST_CONFIG 0xB4027ffc 844 845#define AU1550_ETH0_BASE 0xB0500000 846#define AU1550_ETH1_BASE 0xB0510000 847#define AU1550_MAC0_ENABLE 0xB0520000 848#define AU1550_MAC1_ENABLE 0xB0520004 849#define NUM_ETH_INTERFACES 2 850#endif /* CONFIG_SOC_AU1550 */ 851 852#ifdef CONFIG_SOC_AU1200 853#define AU1200_UART0_INT 0 854#define AU1200_SWT_INT 1 855#define AU1200_SD_INT 2 856#define AU1200_DDMA_INT 3 857#define AU1200_MAE_BE_INT 4 858#define AU1200_GPIO_200 5 859#define AU1200_GPIO_201 6 860#define AU1200_GPIO_202 7 861#define AU1200_UART1_INT 8 862#define AU1200_MAE_FE_INT 9 863#define AU1200_PSC0_INT 10 864#define AU1200_PSC1_INT 11 865#define AU1200_AES_INT 12 866#define AU1200_CAMERA_INT 13 867#define AU1000_TOY_INT 14 868#define AU1000_TOY_MATCH0_INT 15 869#define AU1000_TOY_MATCH1_INT 16 870#define AU1000_TOY_MATCH2_INT 17 871#define AU1000_RTC_INT 18 872#define AU1000_RTC_MATCH0_INT 19 873#define AU1000_RTC_MATCH1_INT 20 874#define AU1000_RTC_MATCH2_INT 21 875#define AU1200_NAND_INT 23 876#define AU1200_GPIO_204 24 877#define AU1200_GPIO_205 25 878#define AU1200_GPIO_206 26 879#define AU1200_GPIO_207 27 880#define AU1200_GPIO_208_215 28 // Logical OR of 208:215 881#define AU1200_USB_INT 29 882#define AU1000_USB_HOST_INT AU1200_USB_INT 883#define AU1200_LCD_INT 30 884#define AU1200_MAE_BOTH_INT 31 885#define AU1000_GPIO_0 32 886#define AU1000_GPIO_1 33 887#define AU1000_GPIO_2 34 888#define AU1000_GPIO_3 35 889#define AU1000_GPIO_4 36 890#define AU1000_GPIO_5 37 891#define AU1000_GPIO_6 38 892#define AU1000_GPIO_7 39 893#define AU1000_GPIO_8 40 894#define AU1000_GPIO_9 41 895#define AU1000_GPIO_10 42 896#define AU1000_GPIO_11 43 897#define AU1000_GPIO_12 44 898#define AU1000_GPIO_13 45 899#define AU1000_GPIO_14 46 900#define AU1000_GPIO_15 47 901#define AU1000_GPIO_16 48 902#define AU1000_GPIO_17 49 903#define AU1000_GPIO_18 50 904#define AU1000_GPIO_19 51 905#define AU1000_GPIO_20 52 906#define AU1000_GPIO_21 53 907#define AU1000_GPIO_22 54 908#define AU1000_GPIO_23 55 909#define AU1000_GPIO_24 56 910#define AU1000_GPIO_25 57 911#define AU1000_GPIO_26 58 912#define AU1000_GPIO_27 59 913#define AU1000_GPIO_28 60 914#define AU1000_GPIO_29 61 915#define AU1000_GPIO_30 62 916#define AU1000_GPIO_31 63 917 918#define UART0_ADDR 0xB1100000 919#define UART1_ADDR 0xB1200000 920 921#define USB_UOC_BASE 0x14020020 922#define USB_UOC_LEN 0x20 923#define USB_OHCI_BASE 0x14020100 924#define USB_OHCI_LEN 0x100 925#define USB_EHCI_BASE 0x14020200 926#define USB_EHCI_LEN 0x100 927#define USB_UDC_BASE 0x14022000 928#define USB_UDC_LEN 0x2000 929#define USB_MSR_BASE 0xB4020000 930#define USB_MSR_MCFG 4 931#define USBMSRMCFG_OMEMEN 0 932#define USBMSRMCFG_OBMEN 1 933#define USBMSRMCFG_EMEMEN 2 934#define USBMSRMCFG_EBMEN 3 935#define USBMSRMCFG_DMEMEN 4 936#define USBMSRMCFG_DBMEN 5 937#define USBMSRMCFG_GMEMEN 6 938#define USBMSRMCFG_OHCCLKEN 16 939#define USBMSRMCFG_EHCCLKEN 17 940#define USBMSRMCFG_UDCCLKEN 18 941#define USBMSRMCFG_PHYPLLEN 19 942#define USBMSRMCFG_RDCOMB 30 943#define USBMSRMCFG_PFEN 31 944 945#endif /* CONFIG_SOC_AU1200 */ 946 947#define AU1000_LAST_INTC0_INT 31 948#define AU1000_LAST_INTC1_INT 63 949#define AU1000_MAX_INTR 63 950#define INTX 0xFF /* not valid */ 951 952/* Programmable Counters 0 and 1 */ 953#define SYS_BASE 0xB1900000 954#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 955 #define SYS_CNTRL_E1S (1<<23) 956 #define SYS_CNTRL_T1S (1<<20) 957 #define SYS_CNTRL_M21 (1<<19) 958 #define SYS_CNTRL_M11 (1<<18) 959 #define SYS_CNTRL_M01 (1<<17) 960 #define SYS_CNTRL_C1S (1<<16) 961 #define SYS_CNTRL_BP (1<<14) 962 #define SYS_CNTRL_EN1 (1<<13) 963 #define SYS_CNTRL_BT1 (1<<12) 964 #define SYS_CNTRL_EN0 (1<<11) 965 #define SYS_CNTRL_BT0 (1<<10) 966 #define SYS_CNTRL_E0 (1<<8) 967 #define SYS_CNTRL_E0S (1<<7) 968 #define SYS_CNTRL_32S (1<<5) 969 #define SYS_CNTRL_T0S (1<<4) 970 #define SYS_CNTRL_M20 (1<<3) 971 #define SYS_CNTRL_M10 (1<<2) 972 #define SYS_CNTRL_M00 (1<<1) 973 #define SYS_CNTRL_C0S (1<<0) 974 975/* Programmable Counter 0 Registers */ 976#define SYS_TOYTRIM (SYS_BASE + 0) 977#define SYS_TOYWRITE (SYS_BASE + 4) 978#define SYS_TOYMATCH0 (SYS_BASE + 8) 979#define SYS_TOYMATCH1 (SYS_BASE + 0xC) 980#define SYS_TOYMATCH2 (SYS_BASE + 0x10) 981#define SYS_TOYREAD (SYS_BASE + 0x40) 982 983/* Programmable Counter 1 Registers */ 984#define SYS_RTCTRIM (SYS_BASE + 0x44) 985#define SYS_RTCWRITE (SYS_BASE + 0x48) 986#define SYS_RTCMATCH0 (SYS_BASE + 0x4C) 987#define SYS_RTCMATCH1 (SYS_BASE + 0x50) 988#define SYS_RTCMATCH2 (SYS_BASE + 0x54) 989#define SYS_RTCREAD (SYS_BASE + 0x58) 990 991/* I2S Controller */ 992#define I2S_DATA 0xB1000000 993 #define I2S_DATA_MASK (0xffffff) 994#define I2S_CONFIG 0xB1000004 995 #define I2S_CONFIG_XU (1<<25) 996 #define I2S_CONFIG_XO (1<<24) 997 #define I2S_CONFIG_RU (1<<23) 998 #define I2S_CONFIG_RO (1<<22) 999 #define I2S_CONFIG_TR (1<<21) 1000 #define I2S_CONFIG_TE (1<<20) 1001 #define I2S_CONFIG_TF (1<<19) 1002 #define I2S_CONFIG_RR (1<<18) 1003 #define I2S_CONFIG_RE (1<<17) 1004 #define I2S_CONFIG_RF (1<<16) 1005 #define I2S_CONFIG_PD (1<<11) 1006 #define I2S_CONFIG_LB (1<<10) 1007 #define I2S_CONFIG_IC (1<<9) 1008 #define I2S_CONFIG_FM_BIT 7 1009 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) 1010 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) 1011 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) 1012 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) 1013 #define I2S_CONFIG_TN (1<<6) 1014 #define I2S_CONFIG_RN (1<<5) 1015 #define I2S_CONFIG_SZ_BIT 0 1016 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) 1017 1018#define I2S_CONTROL 0xB1000008 1019 #define I2S_CONTROL_D (1<<1) 1020 #define I2S_CONTROL_CE (1<<0) 1021 1022/* USB Host Controller */ 1023#ifndef USB_OHCI_LEN 1024#define USB_OHCI_LEN 0x00100000 1025#endif 1026 1027#ifndef CONFIG_SOC_AU1200 1028 1029/* USB Device Controller */ 1030#define USBD_EP0RD 0xB0200000 1031#define USBD_EP0WR 0xB0200004 1032#define USBD_EP2WR 0xB0200008 1033#define USBD_EP3WR 0xB020000C 1034#define USBD_EP4RD 0xB0200010 1035#define USBD_EP5RD 0xB0200014 1036#define USBD_INTEN 0xB0200018 1037#define USBD_INTSTAT 0xB020001C 1038 #define USBDEV_INT_SOF (1<<12) 1039 #define USBDEV_INT_HF_BIT 6 1040 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) 1041 #define USBDEV_INT_CMPLT_BIT 0 1042 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) 1043#define USBD_CONFIG 0xB0200020 1044#define USBD_EP0CS 0xB0200024 1045#define USBD_EP2CS 0xB0200028 1046#define USBD_EP3CS 0xB020002C 1047#define USBD_EP4CS 0xB0200030 1048#define USBD_EP5CS 0xB0200034 1049 #define USBDEV_CS_SU (1<<14) 1050 #define USBDEV_CS_NAK (1<<13) 1051 #define USBDEV_CS_ACK (1<<12) 1052 #define USBDEV_CS_BUSY (1<<11) 1053 #define USBDEV_CS_TSIZE_BIT 1 1054 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) 1055 #define USBDEV_CS_STALL (1<<0) 1056#define USBD_EP0RDSTAT 0xB0200040 1057#define USBD_EP0WRSTAT 0xB0200044 1058#define USBD_EP2WRSTAT 0xB0200048 1059#define USBD_EP3WRSTAT 0xB020004C 1060#define USBD_EP4RDSTAT 0xB0200050 1061#define USBD_EP5RDSTAT 0xB0200054 1062 #define USBDEV_FSTAT_FLUSH (1<<6) 1063 #define USBDEV_FSTAT_UF (1<<5) 1064 #define USBDEV_FSTAT_OF (1<<4) 1065 #define USBDEV_FSTAT_FCNT_BIT 0 1066 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) 1067#define USBD_ENABLE 0xB0200058 1068 #define USBDEV_ENABLE (1<<1) 1069 #define USBDEV_CE (1<<0) 1070 1071#endif /* !CONFIG_SOC_AU1200 */ 1072 1073/* Ethernet Controllers */ 1074 1075/* 4 byte offsets from AU1000_ETH_BASE */ 1076#define MAC_CONTROL 0x0 1077 #define MAC_RX_ENABLE (1<<2) 1078 #define MAC_TX_ENABLE (1<<3) 1079 #define MAC_DEF_CHECK (1<<5) 1080 #define MAC_SET_BL(X) (((X)&0x3)<<6) 1081 #define MAC_AUTO_PAD (1<<8) 1082 #define MAC_DISABLE_RETRY (1<<10) 1083 #define MAC_DISABLE_BCAST (1<<11) 1084 #define MAC_LATE_COL (1<<12) 1085 #define MAC_HASH_MODE (1<<13) 1086 #define MAC_HASH_ONLY (1<<15) 1087 #define MAC_PASS_ALL (1<<16) 1088 #define MAC_INVERSE_FILTER (1<<17) 1089 #define MAC_PROMISCUOUS (1<<18) 1090 #define MAC_PASS_ALL_MULTI (1<<19) 1091 #define MAC_FULL_DUPLEX (1<<20) 1092 #define MAC_NORMAL_MODE 0 1093 #define MAC_INT_LOOPBACK (1<<21) 1094 #define MAC_EXT_LOOPBACK (1<<22) 1095 #define MAC_DISABLE_RX_OWN (1<<23) 1096 #define MAC_BIG_ENDIAN (1<<30) 1097 #define MAC_RX_ALL (1<<31) 1098#define MAC_ADDRESS_HIGH 0x4 1099#define MAC_ADDRESS_LOW 0x8 1100#define MAC_MCAST_HIGH 0xC 1101#define MAC_MCAST_LOW 0x10 1102#define MAC_MII_CNTRL 0x14 1103 #define MAC_MII_BUSY (1<<0) 1104 #define MAC_MII_READ 0 1105 #define MAC_MII_WRITE (1<<1) 1106 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) 1107 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) 1108#define MAC_MII_DATA 0x18 1109#define MAC_FLOW_CNTRL 0x1C 1110 #define MAC_FLOW_CNTRL_BUSY (1<<0) 1111 #define MAC_FLOW_CNTRL_ENABLE (1<<1) 1112 #define MAC_PASS_CONTROL (1<<2) 1113 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) 1114#define MAC_VLAN1_TAG 0x20 1115#define MAC_VLAN2_TAG 0x24 1116 1117/* Ethernet Controller Enable */ 1118 1119 #define MAC_EN_CLOCK_ENABLE (1<<0) 1120 #define MAC_EN_RESET0 (1<<1) 1121 #define MAC_EN_TOSS (0<<2) 1122 #define MAC_EN_CACHEABLE (1<<3) 1123 #define MAC_EN_RESET1 (1<<4) 1124 #define MAC_EN_RESET2 (1<<5) 1125 #define MAC_DMA_RESET (1<<6) 1126 1127/* Ethernet Controller DMA Channels */ 1128 1129#define MAC0_TX_DMA_ADDR 0xB4004000 1130#define MAC1_TX_DMA_ADDR 0xB4004200 1131/* offsets from MAC_TX_RING_ADDR address */ 1132#define MAC_TX_BUFF0_STATUS 0x0 1133 #define TX_FRAME_ABORTED (1<<0) 1134 #define TX_JAB_TIMEOUT (1<<1) 1135 #define TX_NO_CARRIER (1<<2) 1136 #define TX_LOSS_CARRIER (1<<3) 1137 #define TX_EXC_DEF (1<<4) 1138 #define TX_LATE_COLL_ABORT (1<<5) 1139 #define TX_EXC_COLL (1<<6) 1140 #define TX_UNDERRUN (1<<7) 1141 #define TX_DEFERRED (1<<8) 1142 #define TX_LATE_COLL (1<<9) 1143 #define TX_COLL_CNT_MASK (0xF<<10) 1144 #define TX_PKT_RETRY (1<<31) 1145#define MAC_TX_BUFF0_ADDR 0x4 1146 #define TX_DMA_ENABLE (1<<0) 1147 #define TX_T_DONE (1<<1) 1148 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 1149#define MAC_TX_BUFF0_LEN 0x8 1150#define MAC_TX_BUFF1_STATUS 0x10 1151#define MAC_TX_BUFF1_ADDR 0x14 1152#define MAC_TX_BUFF1_LEN 0x18 1153#define MAC_TX_BUFF2_STATUS 0x20 1154#define MAC_TX_BUFF2_ADDR 0x24 1155#define MAC_TX_BUFF2_LEN 0x28 1156#define MAC_TX_BUFF3_STATUS 0x30 1157#define MAC_TX_BUFF3_ADDR 0x34 1158#define MAC_TX_BUFF3_LEN 0x38 1159 1160#define MAC0_RX_DMA_ADDR 0xB4004100 1161#define MAC1_RX_DMA_ADDR 0xB4004300 1162/* offsets from MAC_RX_RING_ADDR */ 1163#define MAC_RX_BUFF0_STATUS 0x0 1164 #define RX_FRAME_LEN_MASK 0x3fff 1165 #define RX_WDOG_TIMER (1<<14) 1166 #define RX_RUNT (1<<15) 1167 #define RX_OVERLEN (1<<16) 1168 #define RX_COLL (1<<17) 1169 #define RX_ETHER (1<<18) 1170 #define RX_MII_ERROR (1<<19) 1171 #define RX_DRIBBLING (1<<20) 1172 #define RX_CRC_ERROR (1<<21) 1173 #define RX_VLAN1 (1<<22) 1174 #define RX_VLAN2 (1<<23) 1175 #define RX_LEN_ERROR (1<<24) 1176 #define RX_CNTRL_FRAME (1<<25) 1177 #define RX_U_CNTRL_FRAME (1<<26) 1178 #define RX_MCAST_FRAME (1<<27) 1179 #define RX_BCAST_FRAME (1<<28) 1180 #define RX_FILTER_FAIL (1<<29) 1181 #define RX_PACKET_FILTER (1<<30) 1182 #define RX_MISSED_FRAME (1<<31) 1183 1184 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ 1185 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ 1186 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 1187#define MAC_RX_BUFF0_ADDR 0x4 1188 #define RX_DMA_ENABLE (1<<0) 1189 #define RX_T_DONE (1<<1) 1190 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 1191 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) 1192#define MAC_RX_BUFF1_STATUS 0x10 1193#define MAC_RX_BUFF1_ADDR 0x14 1194#define MAC_RX_BUFF2_STATUS 0x20 1195#define MAC_RX_BUFF2_ADDR 0x24 1196#define MAC_RX_BUFF3_STATUS 0x30 1197#define MAC_RX_BUFF3_ADDR 0x34 1198 1199 1200/* UARTS 0-3 */ 1201#define UART_BASE UART0_ADDR 1202#ifdef CONFIG_SOC_AU1200 1203#define UART_DEBUG_BASE UART1_ADDR 1204#else 1205#define UART_DEBUG_BASE UART3_ADDR 1206#endif 1207 1208#define UART_RX 0 /* Receive buffer */ 1209#define UART_TX 4 /* Transmit buffer */ 1210#define UART_IER 8 /* Interrupt Enable Register */ 1211#define UART_IIR 0xC /* Interrupt ID Register */ 1212#define UART_FCR 0x10 /* FIFO Control Register */ 1213#define UART_LCR 0x14 /* Line Control Register */ 1214#define UART_MCR 0x18 /* Modem Control Register */ 1215#define UART_LSR 0x1C /* Line Status Register */ 1216#define UART_MSR 0x20 /* Modem Status Register */ 1217#define UART_CLK 0x28 /* Baud Rate Clock Divider */ 1218#define UART_MOD_CNTRL 0x100 /* Module Control */ 1219 1220#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ 1221#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 1222#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 1223#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 1224#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ 1225#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ 1226#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ 1227#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ 1228#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ 1229#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ 1230#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ 1231#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ 1232#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ 1233 1234/* 1235 * These are the definitions for the Line Control Register 1236 */ 1237#define UART_LCR_SBC 0x40 /* Set break control */ 1238#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ 1239#define UART_LCR_EPAR 0x10 /* Even parity select */ 1240#define UART_LCR_PARITY 0x08 /* Parity Enable */ 1241#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ 1242#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ 1243#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ 1244#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ 1245#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ 1246 1247/* 1248 * These are the definitions for the Line Status Register 1249 */ 1250#define UART_LSR_TEMT 0x40 /* Transmitter empty */ 1251#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 1252#define UART_LSR_BI 0x10 /* Break interrupt indicator */ 1253#define UART_LSR_FE 0x08 /* Frame error indicator */ 1254#define UART_LSR_PE 0x04 /* Parity error indicator */ 1255#define UART_LSR_OE 0x02 /* Overrun error indicator */ 1256#define UART_LSR_DR 0x01 /* Receiver data ready */ 1257 1258/* 1259 * These are the definitions for the Interrupt Identification Register 1260 */ 1261#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 1262#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 1263#define UART_IIR_MSI 0x00 /* Modem status interrupt */ 1264#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 1265#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 1266#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 1267 1268/* 1269 * These are the definitions for the Interrupt Enable Register 1270 */ 1271#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 1272#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 1273#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 1274#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 1275 1276/* 1277 * These are the definitions for the Modem Control Register 1278 */ 1279#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 1280#define UART_MCR_OUT2 0x08 /* Out2 complement */ 1281#define UART_MCR_OUT1 0x04 /* Out1 complement */ 1282#define UART_MCR_RTS 0x02 /* RTS complement */ 1283#define UART_MCR_DTR 0x01 /* DTR complement */ 1284 1285/* 1286 * These are the definitions for the Modem Status Register 1287 */ 1288#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 1289#define UART_MSR_RI 0x40 /* Ring Indicator */ 1290#define UART_MSR_DSR 0x20 /* Data Set Ready */ 1291#define UART_MSR_CTS 0x10 /* Clear to Send */ 1292#define UART_MSR_DDCD 0x08 /* Delta DCD */ 1293#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 1294#define UART_MSR_DDSR 0x02 /* Delta DSR */ 1295#define UART_MSR_DCTS 0x01 /* Delta CTS */ 1296#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ 1297 1298 1299 1300/* SSIO */ 1301#define SSI0_STATUS 0xB1600000 1302 #define SSI_STATUS_BF (1<<4) 1303 #define SSI_STATUS_OF (1<<3) 1304 #define SSI_STATUS_UF (1<<2) 1305 #define SSI_STATUS_D (1<<1) 1306 #define SSI_STATUS_B (1<<0) 1307#define SSI0_INT 0xB1600004 1308 #define SSI_INT_OI (1<<3) 1309 #define SSI_INT_UI (1<<2) 1310 #define SSI_INT_DI (1<<1) 1311#define SSI0_INT_ENABLE 0xB1600008 1312 #define SSI_INTE_OIE (1<<3) 1313 #define SSI_INTE_UIE (1<<2) 1314 #define SSI_INTE_DIE (1<<1) 1315#define SSI0_CONFIG 0xB1600020 1316 #define SSI_CONFIG_AO (1<<24) 1317 #define SSI_CONFIG_DO (1<<23) 1318 #define SSI_CONFIG_ALEN_BIT 20 1319 #define SSI_CONFIG_ALEN_MASK (0x7<<20) 1320 #define SSI_CONFIG_DLEN_BIT 16 1321 #define SSI_CONFIG_DLEN_MASK (0x7<<16) 1322 #define SSI_CONFIG_DD (1<<11) 1323 #define SSI_CONFIG_AD (1<<10) 1324 #define SSI_CONFIG_BM_BIT 8 1325 #define SSI_CONFIG_BM_MASK (0x3<<8) 1326 #define SSI_CONFIG_CE (1<<7) 1327 #define SSI_CONFIG_DP (1<<6) 1328 #define SSI_CONFIG_DL (1<<5) 1329 #define SSI_CONFIG_EP (1<<4) 1330#define SSI0_ADATA 0xB1600024 1331 #define SSI_AD_D (1<<24) 1332 #define SSI_AD_ADDR_BIT 16 1333 #define SSI_AD_ADDR_MASK (0xff<<16) 1334 #define SSI_AD_DATA_BIT 0 1335 #define SSI_AD_DATA_MASK (0xfff<<0) 1336#define SSI0_CLKDIV 0xB1600028 1337#define SSI0_CONTROL 0xB1600100 1338 #define SSI_CONTROL_CD (1<<1) 1339 #define SSI_CONTROL_E (1<<0) 1340 1341/* SSI1 */ 1342#define SSI1_STATUS 0xB1680000 1343#define SSI1_INT 0xB1680004 1344#define SSI1_INT_ENABLE 0xB1680008 1345#define SSI1_CONFIG 0xB1680020 1346#define SSI1_ADATA 0xB1680024 1347#define SSI1_CLKDIV 0xB1680028 1348#define SSI1_ENABLE 0xB1680100 1349 1350/* 1351 * Register content definitions 1352 */ 1353#define SSI_STATUS_BF (1<<4) 1354#define SSI_STATUS_OF (1<<3) 1355#define SSI_STATUS_UF (1<<2) 1356#define SSI_STATUS_D (1<<1) 1357#define SSI_STATUS_B (1<<0) 1358 1359/* SSI_INT */ 1360#define SSI_INT_OI (1<<3) 1361#define SSI_INT_UI (1<<2) 1362#define SSI_INT_DI (1<<1) 1363 1364/* SSI_INTEN */ 1365#define SSI_INTEN_OIE (1<<3) 1366#define SSI_INTEN_UIE (1<<2) 1367#define SSI_INTEN_DIE (1<<1) 1368 1369#define SSI_CONFIG_AO (1<<24) 1370#define SSI_CONFIG_DO (1<<23) 1371#define SSI_CONFIG_ALEN (7<<20) 1372#define SSI_CONFIG_DLEN (15<<16) 1373#define SSI_CONFIG_DD (1<<11) 1374#define SSI_CONFIG_AD (1<<10) 1375#define SSI_CONFIG_BM (3<<8) 1376#define SSI_CONFIG_CE (1<<7) 1377#define SSI_CONFIG_DP (1<<6) 1378#define SSI_CONFIG_DL (1<<5) 1379#define SSI_CONFIG_EP (1<<4) 1380#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20) 1381#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16) 1382#define SSI_CONFIG_BM_HI (0<<8) 1383#define SSI_CONFIG_BM_LO (1<<8) 1384#define SSI_CONFIG_BM_CY (2<<8) 1385 1386#define SSI_ADATA_D (1<<24) 1387#define SSI_ADATA_ADDR (0xFF<<16) 1388#define SSI_ADATA_DATA (0x0FFF) 1389#define SSI_ADATA_ADDR_N(N) (N<<16) 1390 1391#define SSI_ENABLE_CD (1<<1) 1392#define SSI_ENABLE_E (1<<0) 1393 1394 1395/* IrDA Controller */ 1396#define IRDA_BASE 0xB0300000 1397#define IR_RING_PTR_STATUS (IRDA_BASE+0x00) 1398#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) 1399#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) 1400#define IR_RING_SIZE (IRDA_BASE+0x0C) 1401#define IR_RING_PROMPT (IRDA_BASE+0x10) 1402#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) 1403#define IR_INT_CLEAR (IRDA_BASE+0x18) 1404#define IR_CONFIG_1 (IRDA_BASE+0x20) 1405 #define IR_RX_INVERT_LED (1<<0) 1406 #define IR_TX_INVERT_LED (1<<1) 1407 #define IR_ST (1<<2) 1408 #define IR_SF (1<<3) 1409 #define IR_SIR (1<<4) 1410 #define IR_MIR (1<<5) 1411 #define IR_FIR (1<<6) 1412 #define IR_16CRC (1<<7) 1413 #define IR_TD (1<<8) 1414 #define IR_RX_ALL (1<<9) 1415 #define IR_DMA_ENABLE (1<<10) 1416 #define IR_RX_ENABLE (1<<11) 1417 #define IR_TX_ENABLE (1<<12) 1418 #define IR_LOOPBACK (1<<14) 1419 #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ 1420 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) 1421#define IR_SIR_FLAGS (IRDA_BASE+0x24) 1422#define IR_ENABLE (IRDA_BASE+0x28) 1423 #define IR_RX_STATUS (1<<9) 1424 #define IR_TX_STATUS (1<<10) 1425#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) 1426#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) 1427#define IR_MAX_PKT_LEN (IRDA_BASE+0x34) 1428#define IR_RX_BYTE_CNT (IRDA_BASE+0x38) 1429#define IR_CONFIG_2 (IRDA_BASE+0x3C) 1430 #define IR_MODE_INV (1<<0) 1431 #define IR_ONE_PIN (1<<1) 1432#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) 1433 1434/* GPIO */ 1435#define SYS_PINFUNC 0xB190002C 1436 #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ 1437 #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ 1438 #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ 1439 #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ 1440 #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ 1441 #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ 1442 #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ 1443 #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ 1444 #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ 1445 #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ 1446 #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ 1447 #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ 1448 #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ 1449 #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ 1450 #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ 1451 #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ 1452 1453/* Au1100 Only */ 1454 #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ 1455 #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ 1456 #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ 1457 #define SYS_PF_EX0 (1<<9) /* gpio2/clock */ 1458 1459/* Au1550 Only. Redefines lots of pins */ 1460 #define SYS_PF_PSC2_MASK (7 << 17) 1461 #define SYS_PF_PSC2_AC97 (0) 1462 #define SYS_PF_PSC2_SPI (0) 1463 #define SYS_PF_PSC2_I2S (1 << 17) 1464 #define SYS_PF_PSC2_SMBUS (3 << 17) 1465 #define SYS_PF_PSC2_GPIO (7 << 17) 1466 #define SYS_PF_PSC3_MASK (7 << 20) 1467 #define SYS_PF_PSC3_AC97 (0) 1468 #define SYS_PF_PSC3_SPI (0) 1469 #define SYS_PF_PSC3_I2S (1 << 20) 1470 #define SYS_PF_PSC3_SMBUS (3 << 20) 1471 #define SYS_PF_PSC3_GPIO (7 << 20) 1472 #define SYS_PF_PSC1_S1 (1 << 1) 1473 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1474 1475/* Au1200 Only */ 1476#ifdef CONFIG_SOC_AU1200 1477#define SYS_PINFUNC_DMA (1<<31) 1478#define SYS_PINFUNC_S0A (1<<30) 1479#define SYS_PINFUNC_S1A (1<<29) 1480#define SYS_PINFUNC_LP0 (1<<28) 1481#define SYS_PINFUNC_LP1 (1<<27) 1482#define SYS_PINFUNC_LD16 (1<<26) 1483#define SYS_PINFUNC_LD8 (1<<25) 1484#define SYS_PINFUNC_LD1 (1<<24) 1485#define SYS_PINFUNC_LD0 (1<<23) 1486#define SYS_PINFUNC_P1A (3<<21) 1487#define SYS_PINFUNC_P1B (1<<20) 1488#define SYS_PINFUNC_FS3 (1<<19) 1489#define SYS_PINFUNC_P0A (3<<17) 1490#define SYS_PINFUNC_CS (1<<16) 1491#define SYS_PINFUNC_CIM (1<<15) 1492#define SYS_PINFUNC_P1C (1<<14) 1493#define SYS_PINFUNC_U1T (1<<12) 1494#define SYS_PINFUNC_U1R (1<<11) 1495#define SYS_PINFUNC_EX1 (1<<10) 1496#define SYS_PINFUNC_EX0 (1<<9) 1497#define SYS_PINFUNC_U0R (1<<8) 1498#define SYS_PINFUNC_MC (1<<7) 1499#define SYS_PINFUNC_S0B (1<<6) 1500#define SYS_PINFUNC_S0C (1<<5) 1501#define SYS_PINFUNC_P0B (1<<4) 1502#define SYS_PINFUNC_U0T (1<<3) 1503#define SYS_PINFUNC_S1B (1<<2) 1504#endif 1505 1506#define SYS_TRIOUTRD 0xB1900100 1507#define SYS_TRIOUTCLR 0xB1900100 1508#define SYS_OUTPUTRD 0xB1900108 1509#define SYS_OUTPUTSET 0xB1900108 1510#define SYS_OUTPUTCLR 0xB190010C 1511#define SYS_PINSTATERD 0xB1900110 1512#define SYS_PININPUTEN 0xB1900110 1513 1514/* GPIO2, Au1500, Au1550 only */ 1515#define GPIO2_BASE 0xB1700000 1516#define GPIO2_DIR (GPIO2_BASE + 0) 1517#define GPIO2_OUTPUT (GPIO2_BASE + 8) 1518#define GPIO2_PINSTATE (GPIO2_BASE + 0xC) 1519#define GPIO2_INTENABLE (GPIO2_BASE + 0x10) 1520#define GPIO2_ENABLE (GPIO2_BASE + 0x14) 1521 1522/* Power Management */ 1523#define SYS_SCRATCH0 0xB1900018 1524#define SYS_SCRATCH1 0xB190001C 1525#define SYS_WAKEMSK 0xB1900034 1526#define SYS_ENDIAN 0xB1900038 1527#define SYS_POWERCTRL 0xB190003C 1528#define SYS_WAKESRC 0xB190005C 1529#define SYS_SLPPWR 0xB1900078 1530#define SYS_SLEEP 0xB190007C 1531 1532/* Clock Controller */ 1533#define SYS_FREQCTRL0 0xB1900020 1534 #define SYS_FC_FRDIV2_BIT 22 1535 #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) 1536 #define SYS_FC_FE2 (1<<21) 1537 #define SYS_FC_FS2 (1<<20) 1538 #define SYS_FC_FRDIV1_BIT 12 1539 #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) 1540 #define SYS_FC_FE1 (1<<11) 1541 #define SYS_FC_FS1 (1<<10) 1542 #define SYS_FC_FRDIV0_BIT 2 1543 #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) 1544 #define SYS_FC_FE0 (1<<1) 1545 #define SYS_FC_FS0 (1<<0) 1546#define SYS_FREQCTRL1 0xB1900024 1547 #define SYS_FC_FRDIV5_BIT 22 1548 #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) 1549 #define SYS_FC_FE5 (1<<21) 1550 #define SYS_FC_FS5 (1<<20) 1551 #define SYS_FC_FRDIV4_BIT 12 1552 #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) 1553 #define SYS_FC_FE4 (1<<11) 1554 #define SYS_FC_FS4 (1<<10) 1555 #define SYS_FC_FRDIV3_BIT 2 1556 #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) 1557 #define SYS_FC_FE3 (1<<1) 1558 #define SYS_FC_FS3 (1<<0) 1559#define SYS_CLKSRC 0xB1900028 1560 #define SYS_CS_ME1_BIT 27 1561 #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) 1562 #define SYS_CS_DE1 (1<<26) 1563 #define SYS_CS_CE1 (1<<25) 1564 #define SYS_CS_ME0_BIT 22 1565 #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) 1566 #define SYS_CS_DE0 (1<<21) 1567 #define SYS_CS_CE0 (1<<20) 1568 #define SYS_CS_MI2_BIT 17 1569 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) 1570 #define SYS_CS_DI2 (1<<16) 1571 #define SYS_CS_CI2 (1<<15) 1572#ifdef CONFIG_SOC_AU1100 1573 #define SYS_CS_ML_BIT 7 1574 #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) 1575 #define SYS_CS_DL (1<<6) 1576 #define SYS_CS_CL (1<<5) 1577#else 1578 #define SYS_CS_MUH_BIT 12 1579 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) 1580 #define SYS_CS_DUH (1<<11) 1581 #define SYS_CS_CUH (1<<10) 1582 #define SYS_CS_MUD_BIT 7 1583 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) 1584 #define SYS_CS_DUD (1<<6) 1585 #define SYS_CS_CUD (1<<5) 1586#endif 1587 #define SYS_CS_MIR_BIT 2 1588 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) 1589 #define SYS_CS_DIR (1<<1) 1590 #define SYS_CS_CIR (1<<0) 1591 1592 #define SYS_CS_MUX_AUX 0x1 1593 #define SYS_CS_MUX_FQ0 0x2 1594 #define SYS_CS_MUX_FQ1 0x3 1595 #define SYS_CS_MUX_FQ2 0x4 1596 #define SYS_CS_MUX_FQ3 0x5 1597 #define SYS_CS_MUX_FQ4 0x6 1598 #define SYS_CS_MUX_FQ5 0x7 1599#define SYS_CPUPLL 0xB1900060 1600#define SYS_AUXPLL 0xB1900064 1601 1602/* AC97 Controller */ 1603#define AC97C_CONFIG 0xB0000000 1604 #define AC97C_RECV_SLOTS_BIT 13 1605 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) 1606 #define AC97C_XMIT_SLOTS_BIT 3 1607 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) 1608 #define AC97C_SG (1<<2) 1609 #define AC97C_SYNC (1<<1) 1610 #define AC97C_RESET (1<<0) 1611#define AC97C_STATUS 0xB0000004 1612 #define AC97C_XU (1<<11) 1613 #define AC97C_XO (1<<10) 1614 #define AC97C_RU (1<<9) 1615 #define AC97C_RO (1<<8) 1616 #define AC97C_READY (1<<7) 1617 #define AC97C_CP (1<<6) 1618 #define AC97C_TR (1<<5) 1619 #define AC97C_TE (1<<4) 1620 #define AC97C_TF (1<<3) 1621 #define AC97C_RR (1<<2) 1622 #define AC97C_RE (1<<1) 1623 #define AC97C_RF (1<<0) 1624#define AC97C_DATA 0xB0000008 1625#define AC97C_CMD 0xB000000C 1626 #define AC97C_WD_BIT 16 1627 #define AC97C_READ (1<<7) 1628 #define AC97C_INDEX_MASK 0x7f 1629#define AC97C_CNTRL 0xB0000010 1630 #define AC97C_RS (1<<1) 1631 #define AC97C_CE (1<<0) 1632 1633 1634/* Secure Digital (SD) Controller */ 1635#define SD0_XMIT_FIFO 0xB0600000 1636#define SD0_RECV_FIFO 0xB0600004 1637#define SD1_XMIT_FIFO 0xB0680000 1638#define SD1_RECV_FIFO 0xB0680004 1639 1640#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 1641/* Au1500 PCI Controller */ 1642#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr 1643#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) 1644#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) 1645 #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) 1646#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) 1647#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) 1648#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) 1649#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) 1650#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) 1651#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) 1652#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) 1653#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) 1654#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) 1655#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) 1656#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) 1657#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) 1658 1659#define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr 1660 1661/* All of our structures, like pci resource, have 32 bit members. 1662 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's 1663 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch 1664 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and 1665 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM 1666 * addresses. For PCI IO, it's simpler because we get to do the ioremap 1667 * ourselves and then adjust the device's resources. 1668 */ 1669#define Au1500_EXT_CFG 0x600000000ULL 1670#define Au1500_EXT_CFG_TYPE1 0x680000000ULL 1671#define Au1500_PCI_IO_START 0x500000000ULL 1672#define Au1500_PCI_IO_END 0x5000FFFFFULL 1673#define Au1500_PCI_MEM_START 0x440000000ULL 1674#define Au1500_PCI_MEM_END 0x44FFFFFFFULL 1675 1676#define PCI_IO_START (Au1500_PCI_IO_START + 0x1000) 1677#define PCI_IO_END (Au1500_PCI_IO_END) 1678#define PCI_MEM_START (Au1500_PCI_MEM_START) 1679#define PCI_MEM_END (Au1500_PCI_MEM_END) 1680#define PCI_FIRST_DEVFN (0<<3) 1681#define PCI_LAST_DEVFN (19<<3) 1682 1683#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ 1684#define IOPORT_RESOURCE_END 0xffffffff 1685#define IOMEM_RESOURCE_START 0x10000000 1686#define IOMEM_RESOURCE_END 0xffffffff 1687 1688 /* 1689 * Borrowed from the PPC arch: 1690 * The following macro is used to lookup irqs in a standard table 1691 * format for those PPC systems that do not already have PCI 1692 * interrupts properly routed. 1693 */ 1694#define PCI_IRQ_TABLE_LOOKUP \ 1695 ({ long _ctl_ = -1; \ 1696 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ 1697 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ 1698 _ctl_; }) 1699 1700 1701#else /* Au1000 and Au1100 and Au1200 */ 1702 1703/* don't allow any legacy ports probing */ 1704#define IOPORT_RESOURCE_START 0x10000000 1705#define IOPORT_RESOURCE_END 0xffffffff 1706#define IOMEM_RESOURCE_START 0x10000000 1707#define IOMEM_RESOURCE_END 0xffffffff 1708 1709#define PCI_IO_START 0 1710#define PCI_IO_END 0 1711#define PCI_MEM_START 0 1712#define PCI_MEM_END 0 1713#define PCI_FIRST_DEVFN 0 1714#define PCI_LAST_DEVFN 0 1715 1716#endif 1717 1718#ifndef _LANGUAGE_ASSEMBLY 1719typedef volatile struct 1720{ 1721 /* 0x0000 */ u32 toytrim; 1722 /* 0x0004 */ u32 toywrite; 1723 /* 0x0008 */ u32 toymatch0; 1724 /* 0x000C */ u32 toymatch1; 1725 /* 0x0010 */ u32 toymatch2; 1726 /* 0x0014 */ u32 cntrctrl; 1727 /* 0x0018 */ u32 scratch0; 1728 /* 0x001C */ u32 scratch1; 1729 /* 0x0020 */ u32 freqctrl0; 1730 /* 0x0024 */ u32 freqctrl1; 1731 /* 0x0028 */ u32 clksrc; 1732 /* 0x002C */ u32 pinfunc; 1733 /* 0x0030 */ u32 reserved0; 1734 /* 0x0034 */ u32 wakemsk; 1735 /* 0x0038 */ u32 endian; 1736 /* 0x003C */ u32 powerctrl; 1737 /* 0x0040 */ u32 toyread; 1738 /* 0x0044 */ u32 rtctrim; 1739 /* 0x0048 */ u32 rtcwrite; 1740 /* 0x004C */ u32 rtcmatch0; 1741 /* 0x0050 */ u32 rtcmatch1; 1742 /* 0x0054 */ u32 rtcmatch2; 1743 /* 0x0058 */ u32 rtcread; 1744 /* 0x005C */ u32 wakesrc; 1745 /* 0x0060 */ u32 cpupll; 1746 /* 0x0064 */ u32 auxpll; 1747 /* 0x0068 */ u32 reserved1; 1748 /* 0x006C */ u32 reserved2; 1749 /* 0x0070 */ u32 reserved3; 1750 /* 0x0074 */ u32 reserved4; 1751 /* 0x0078 */ u32 slppwr; 1752 /* 0x007C */ u32 sleep; 1753 /* 0x0080 */ u32 reserved5[32]; 1754 /* 0x0100 */ u32 trioutrd; 1755#define trioutclr trioutrd 1756 /* 0x0104 */ u32 reserved6; 1757 /* 0x0108 */ u32 outputrd; 1758#define outputset outputrd 1759 /* 0x010C */ u32 outputclr; 1760 /* 0x0110 */ u32 pinstaterd; 1761#define pininputen pinstaterd 1762 1763} AU1X00_SYS; 1764 1765static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE; 1766 1767#endif 1768/* Processor information base on prid. 1769 * Copied from PowerPC. 1770 */ 1771#ifndef _LANGUAGE_ASSEMBLY 1772struct cpu_spec { 1773 /* CPU is matched via (PRID & prid_mask) == prid_value */ 1774 unsigned int prid_mask; 1775 unsigned int prid_value; 1776 1777 char *cpu_name; 1778 unsigned char cpu_od; /* Set Config[OD] */ 1779 unsigned char cpu_bclk; /* Enable BCLK switching */ 1780}; 1781 1782extern struct cpu_spec cpu_specs[]; 1783extern struct cpu_spec *cur_cpu_spec[]; 1784#endif 1785 1786#endif 1787