1/* 2 * Copyright 2001 MontaVista Software Inc. 3 * Author: jsun@mvista.com or jsun@junsun.net 4 * 5 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> 6 * Sony Software Development Center Europe (SDCE), Brussels 7 * 8 * include/asm-mips/ddb5xxx/ddb5xxx.h 9 * Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 */ 17 18#ifndef __ASM_DDB5XXX_DDB5XXX_H 19#define __ASM_DDB5XXX_DDB5XXX_H 20 21#include <linux/types.h> 22 23/* 24 * This file is based on the following documentation: 25 * 26 * NEC Vrc 5074 System Controller Data Sheet, June 1998 27 * 28 * [jsun] It is modified so that this file only contains the macros 29 * that are true for all DDB 5xxx boards. The modification is based on 30 * 31 * uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke) 32 * Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000 33 * 34 */ 35 36 37#define DDB_BASE 0xbfa00000 38#define DDB_SIZE 0x00200000 /* 2 MB */ 39 40 41/* 42 * Physical Device Address Registers (PDARs) 43 */ 44 45#define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ 46#define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ 47#define DDB_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ 48#define DDB_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ 49#define DDB_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ 50#define DDB_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ 51#define DDB_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ 52#define DDB_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ 53#define DDB_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ 54#define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ 55#define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ 56#define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */ 57 /* [R/W] */ 58#define DDB_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ 59/* Vrc5477 has two more, IOPCIW0, IOPCIW1 */ 60 61/* 62 * CPU Interface Registers 63 */ 64#define DDB_CPUSTAT 0x0080 /* CPU Status [R/W] */ 65#define DDB_INTCTRL 0x0088 /* Interrupt Control [R/W] */ 66#define DDB_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ 67#define DDB_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ 68 /* Enable [R/W] */ 69#define DDB_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ 70#define DDB_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ 71 72 73/* 74 * Memory-Interface Registers 75 */ 76#define DDB_MEMCTRL 0x00C0 /* Memory Control */ 77#define DDB_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ 78#define DDB_CHKERR 0x00D0 /* Memory Check Error Status [R] */ 79 80 81/* 82 * PCI-Bus Registers 83 */ 84#define DDB_PCICTRL 0x00E0 /* PCI Control [R/W] */ 85#define DDB_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ 86#define DDB_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ 87#define DDB_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ 88#define DDB_PCIERR 0x00B8 /* PCI Error [R/W] */ 89 90 91/* 92 * Local-Bus Registers 93 */ 94#define DDB_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ 95#define DDB_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ 96#define DDB_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ 97#define DDB_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ 98#define DDB_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ 99#define DDB_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ 100#define DDB_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ 101#define DDB_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ 102#define DDB_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ 103 /* Enables [R/W] */ 104#define DDB_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ 105#define DDB_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ 106 107 108/* 109 * DMA Registers 110 */ 111#define DDB_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ 112#define DDB_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ 113#define DDB_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ 114#define DDB_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ 115#define DDB_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ 116#define DDB_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ 117 118 119/* 120 * Timer Registers 121 */ 122#define DDB_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ 123#define DDB_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ 124#define DDB_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ 125#define DDB_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ 126#define DDB_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ 127#define DDB_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ 128#define DDB_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ 129#define DDB_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ 130 131 132/* 133 * PCI Configuration Space Registers 134 */ 135#define DDB_PCI_BASE 0x0200 136 137#define DDB_VID 0x0200 /* PCI Vendor ID [R] */ 138#define DDB_DID 0x0202 /* PCI Device ID [R] */ 139#define DDB_PCICMD 0x0204 /* PCI Command [R/W] */ 140#define DDB_PCISTS 0x0206 /* PCI Status [R/W] */ 141#define DDB_REVID 0x0208 /* PCI Revision ID [R] */ 142#define DDB_CLASS 0x0209 /* PCI Class Code [R] */ 143#define DDB_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ 144#define DDB_MLTIM 0x020D /* PCI Latency Timer [R/W] */ 145#define DDB_HTYPE 0x020E /* PCI Header Type [R] */ 146#define DDB_BIST 0x020F /* BIST [R] (unimplemented) */ 147#define DDB_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ 148#define DDB_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ 149#define DDB_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ 150#define DDB_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ 151 /* (unimplemented) */ 152#define DDB_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ 153#define DDB_SSID 0x022E /* PCI Sub-System ID [R/W] */ 154#define DDB_ROM 0x0230 /* Expansion ROM Base Address [R] */ 155 /* (unimplemented) */ 156#define DDB_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ 157#define DDB_INTPIN 0x023D /* PCI Interrupt Pin [R] */ 158#define DDB_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ 159#define DDB_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ 160#define DDB_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ 161#define DDB_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ 162#define DDB_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ 163#define DDB_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ 164#define DDB_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ 165#define DDB_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ 166#define DDB_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ 167#define DDB_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ 168 169 170/* 171 * Nile 4 Register Access 172 */ 173 174static inline void ddb_sync(void) 175{ 176 volatile u32 *p = (volatile u32 *)0xbfc00000; 177 (void)(*p); 178} 179 180static inline void ddb_out32(u32 offset, u32 val) 181{ 182 *(volatile u32 *)(DDB_BASE+offset) = val; 183 ddb_sync(); 184} 185 186static inline u32 ddb_in32(u32 offset) 187{ 188 u32 val = *(volatile u32 *)(DDB_BASE+offset); 189 ddb_sync(); 190 return val; 191} 192 193static inline void ddb_out16(u32 offset, u16 val) 194{ 195 *(volatile u16 *)(DDB_BASE+offset) = val; 196 ddb_sync(); 197} 198 199static inline u16 ddb_in16(u32 offset) 200{ 201 u16 val = *(volatile u16 *)(DDB_BASE+offset); 202 ddb_sync(); 203 return val; 204} 205 206static inline void ddb_out8(u32 offset, u8 val) 207{ 208 *(volatile u8 *)(DDB_BASE+offset) = val; 209 ddb_sync(); 210} 211 212static inline u8 ddb_in8(u32 offset) 213{ 214 u8 val = *(volatile u8 *)(DDB_BASE+offset); 215 ddb_sync(); 216 return val; 217} 218 219 220/* 221 * Physical Device Address Registers 222 */ 223 224extern u32 225ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible); 226extern void 227ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width, 228 int on_memory_bus, int pci_visible); 229 230/* 231 * PCI Master Registers 232 */ 233 234#define DDB_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ 235#define DDB_PCICMD_IO 1 /* PCI I/O Space */ 236#define DDB_PCICMD_MEM 3 /* PCI Memory Space */ 237#define DDB_PCICMD_CFG 5 /* PCI Configuration Space */ 238 239/* 240 * additional options for pci init reg (no shifting needed) 241 */ 242#define DDB_PCI_CFGTYPE1 0x200 /* for pci init0/1 regs */ 243#define DDB_PCI_ACCESS_32 0x10 /* for pci init0/1 regs */ 244 245 246extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options); 247 248/* 249 * we need to reset pci bus when we start up and shutdown 250 */ 251extern void ddb_pci_reset_bus(void); 252 253 254/* 255 * include the board dependent part 256 */ 257#if defined(CONFIG_DDB5477) 258#include <asm/ddb5xxx/ddb5477.h> 259#else 260#error "Unknown DDB board!" 261#endif 262 263#endif /* __ASM_DDB5XXX_DDB5XXX_H */ 264