1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 * Copyright (C) 2004  Maciej W. Rozycki
11 */
12#ifndef __ASM_CPU_INFO_H
13#define __ASM_CPU_INFO_H
14
15#include <asm/cache.h>
16
17#ifdef CONFIG_SGI_IP27
18#include <asm/sn/types.h>
19#endif
20
21/*
22 * Descriptor for a cache
23 */
24struct cache_desc {
25	unsigned int waysize;	/* Bytes per way */
26	unsigned short sets;	/* Number of lines per set */
27	unsigned char ways;	/* Number of ways */
28	unsigned char linesz;	/* Size of line in bytes */
29	unsigned char waybit;	/* Bits to select in a cache set */
30	unsigned char flags;	/* Flags describing cache properties */
31};
32
33/*
34 * Flag definitions
35 */
36#define MIPS_CACHE_NOT_PRESENT	0x00000001
37#define MIPS_CACHE_VTAG		0x00000002	/* Virtually tagged cache */
38#define MIPS_CACHE_ALIASES	0x00000004	/* Cache could have aliases */
39#define MIPS_CACHE_IC_F_DC	0x00000008	/* Ic can refill from D-cache */
40#define MIPS_IC_SNOOPS_REMOTE	0x00000010	/* Ic snoops remote stores */
41#define MIPS_CACHE_PINDEX	0x00000020	/* Physically indexed cache */
42
43struct cpuinfo_mips {
44	unsigned long		udelay_val;
45	unsigned long		asid_cache;
46#if defined(CONFIG_SGI_IP27)
47//	cpuid_t		p_cpuid;	/* PROM assigned cpuid */
48	cnodeid_t	p_nodeid;	/* my node ID in compact-id-space */
49	nasid_t		p_nasid;	/* my node ID in numa-as-id-space */
50	unsigned char	p_slice;	/* Physical position on node board */
51#endif
52
53	/*
54	 * Capability and feature descriptor structure for MIPS CPU
55	 */
56	unsigned long		options;
57	unsigned long		ases;
58	unsigned int		processor_id;
59	unsigned int		fpu_id;
60	unsigned int		cputype;
61	int			isa_level;
62	int			tlbsize;
63	struct cache_desc	icache;	/* Primary I-cache */
64	struct cache_desc	dcache;	/* Primary D or combined I/D cache */
65	struct cache_desc	scache;	/* Secondary cache */
66	struct cache_desc	tcache;	/* Tertiary/split secondary cache */
67#if defined(CONFIG_MIPS_MT_SMTC)
68	/*
69	 * In the MIPS MT "SMTC" model, each TC is considered
70	 * to be a "CPU" for the purposes of scheduling, but
71	 * exception resources, ASID spaces, etc, are common
72	 * to all TCs within the same VPE.
73	 */
74	int			vpe_id;  /* Virtual Processor number */
75	int			tc_id;   /* Thread Context number */
76#endif /* CONFIG_MIPS_MT */
77	void 			*data;	/* Additional data */
78} __attribute__((aligned(SMP_CACHE_BYTES)));
79
80extern struct cpuinfo_mips cpu_data[];
81#define current_cpu_data cpu_data[smp_processor_id()]
82#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
83
84extern void cpu_probe(void);
85extern void cpu_report(void);
86
87#endif /* __ASM_CPU_INFO_H */
88