1/****************************************************************************/
2
3/*
4 *	mcfpit.h -- ColdFire internal PIT timer support defines.
5 *
6 *	(C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/****************************************************************************/
10#ifndef	mcfpit_h
11#define	mcfpit_h
12/****************************************************************************/
13
14
15/*
16 *	Get address specific defines for the 5270/5271, 5280/5282, and 5208.
17 */
18#if defined(CONFIG_M520x)
19#define	MCFPIT_BASE1		0x00080000	/* Base address of TIMER1 */
20#define	MCFPIT_BASE2		0x00084000	/* Base address of TIMER2 */
21#else
22#define	MCFPIT_BASE1		0x00150000	/* Base address of TIMER1 */
23#define	MCFPIT_BASE2		0x00160000	/* Base address of TIMER2 */
24#define	MCFPIT_BASE3		0x00170000	/* Base address of TIMER3 */
25#define	MCFPIT_BASE4		0x00180000	/* Base address of TIMER4 */
26#endif
27
28/*
29 *	Define the PIT timer register set addresses.
30 */
31#define	MCFPIT_PCSR		0x0		/* PIT control register */
32#define	MCFPIT_PMR		0x2		/* PIT modulus register */
33#define	MCFPIT_PCNTR		0x4		/* PIT count register */
34
35/*
36 *	Bit definitions for the PIT Control and Status register.
37 */
38#define	MCFPIT_PCSR_CLK1	0x0000		/* System clock divisor */
39#define	MCFPIT_PCSR_CLK2	0x0100		/* System clock divisor */
40#define	MCFPIT_PCSR_CLK4	0x0200		/* System clock divisor */
41#define	MCFPIT_PCSR_CLK8	0x0300		/* System clock divisor */
42#define	MCFPIT_PCSR_CLK16	0x0400		/* System clock divisor */
43#define	MCFPIT_PCSR_CLK32	0x0500		/* System clock divisor */
44#define	MCFPIT_PCSR_CLK64	0x0600		/* System clock divisor */
45#define	MCFPIT_PCSR_CLK128	0x0700		/* System clock divisor */
46#define	MCFPIT_PCSR_CLK256	0x0800		/* System clock divisor */
47#define	MCFPIT_PCSR_CLK512	0x0900		/* System clock divisor */
48#define	MCFPIT_PCSR_CLK1024	0x0a00		/* System clock divisor */
49#define	MCFPIT_PCSR_CLK2048	0x0b00		/* System clock divisor */
50#define	MCFPIT_PCSR_CLK4096	0x0c00		/* System clock divisor */
51#define	MCFPIT_PCSR_CLK8192	0x0d00		/* System clock divisor */
52#define	MCFPIT_PCSR_CLK16384	0x0e00		/* System clock divisor */
53#define	MCFPIT_PCSR_CLK32768	0x0f00		/* System clock divisor */
54#define	MCFPIT_PCSR_DOZE	0x0040		/* Clock run in doze mode */
55#define	MCFPIT_PCSR_HALTED	0x0020		/* Clock run in halt mode */
56#define	MCFPIT_PCSR_OVW		0x0010		/* Overwrite PIT counter now */
57#define	MCFPIT_PCSR_PIE		0x0008		/* Enable PIT interrupt */
58#define	MCFPIT_PCSR_PIF		0x0004		/* PIT interrupt flag */
59#define	MCFPIT_PCSR_RLD		0x0002		/* Reload counter */
60#define	MCFPIT_PCSR_EN		0x0001		/* Enable PIT */
61#define	MCFPIT_PCSR_DISABLE	0x0000		/* Disable PIT */
62
63/****************************************************************************/
64#endif	/* mcfpit_h */
65