1#ifndef _MVME147HW_H_
2#define _MVME147HW_H_
3
4#include <asm/irq.h>
5
6typedef struct {
7	unsigned char
8		ctrl,
9		bcd_sec,
10		bcd_min,
11		bcd_hr,
12		bcd_dow,
13		bcd_dom,
14		bcd_mth,
15		bcd_year;
16} MK48T02;
17
18#define RTC_WRITE	0x80
19#define RTC_READ	0x40
20#define RTC_STOP	0x20
21
22#define m147_rtc ((MK48T02 * volatile)0xfffe07f8)
23
24
25struct pcc_regs {
26   volatile u_long	dma_tadr;
27   volatile u_long	dma_dadr;
28   volatile u_long	dma_bcr;
29   volatile u_long	dma_hr;
30   volatile u_short	t1_preload;
31   volatile u_short	t1_count;
32   volatile u_short	t2_preload;
33   volatile u_short	t2_count;
34   volatile u_char	t1_int_cntrl;
35   volatile u_char	t1_cntrl;
36   volatile u_char	t2_int_cntrl;
37   volatile u_char	t2_cntrl;
38   volatile u_char	ac_fail;
39   volatile u_char	watchdog;
40   volatile u_char	lpt_intr;
41   volatile u_char	lpt_cntrl;
42   volatile u_char	dma_intr;
43   volatile u_char	dma_cntrl;
44   volatile u_char	bus_error;
45   volatile u_char	dma_status;
46   volatile u_char	abort;
47   volatile u_char	ta_fnctl;
48   volatile u_char	serial_cntrl;
49   volatile u_char	general_cntrl;
50   volatile u_char	lan_cntrl;
51   volatile u_char	general_status;
52   volatile u_char	scsi_interrupt;
53   volatile u_char	slave;
54   volatile u_char	soft1_cntrl;
55   volatile u_char	int_base;
56   volatile u_char	soft2_cntrl;
57   volatile u_char	revision_level;
58   volatile u_char	lpt_data;
59   volatile u_char	lpt_status;
60   };
61
62#define m147_pcc ((struct pcc_regs * volatile)0xfffe1000)
63
64
65#define PCC_INT_ENAB		0x08
66
67#define PCC_TIMER_INT_CLR	0x80
68#define PCC_TIMER_PRELOAD	63936l
69
70#define PCC_LEVEL_ABORT		0x07
71#define PCC_LEVEL_SERIAL	0x04
72#define PCC_LEVEL_ETH		0x04
73#define PCC_LEVEL_TIMER1	0x04
74#define PCC_LEVEL_SCSI_PORT	0x04
75#define PCC_LEVEL_SCSI_DMA	0x04
76
77#define PCC_IRQ_AC_FAIL		(IRQ_USER+0)
78#define PCC_IRQ_BERR		(IRQ_USER+1)
79#define PCC_IRQ_ABORT		(IRQ_USER+2)
80/* #define PCC_IRQ_SERIAL	(IRQ_USER+3) */
81#define PCC_IRQ_PRINTER		(IRQ_USER+7)
82#define PCC_IRQ_TIMER1		(IRQ_USER+8)
83#define PCC_IRQ_TIMER2		(IRQ_USER+9)
84#define PCC_IRQ_SOFTWARE1	(IRQ_USER+10)
85#define PCC_IRQ_SOFTWARE2	(IRQ_USER+11)
86
87
88#define M147_SCC_A_ADDR		0xfffe3002
89#define M147_SCC_B_ADDR		0xfffe3000
90#define M147_SCC_PCLK		5000000
91
92#define MVME147_IRQ_SCSI_PORT	(IRQ_USER+0x45)
93#define MVME147_IRQ_SCSI_DMA	(IRQ_USER+0x46)
94
95/* SCC interrupts, for MVME147 */
96
97#define MVME147_IRQ_TYPE_PRIO	0
98#define MVME147_IRQ_SCC_BASE		(IRQ_USER+32)
99#define MVME147_IRQ_SCCB_TX		(IRQ_USER+32)
100#define MVME147_IRQ_SCCB_STAT		(IRQ_USER+34)
101#define MVME147_IRQ_SCCB_RX		(IRQ_USER+36)
102#define MVME147_IRQ_SCCB_SPCOND		(IRQ_USER+38)
103#define MVME147_IRQ_SCCA_TX		(IRQ_USER+40)
104#define MVME147_IRQ_SCCA_STAT		(IRQ_USER+42)
105#define MVME147_IRQ_SCCA_RX		(IRQ_USER+44)
106#define MVME147_IRQ_SCCA_SPCOND		(IRQ_USER+46)
107
108#define MVME147_LANCE_BASE	0xfffe1800
109#define MVME147_LANCE_IRQ	(IRQ_USER+4)
110
111#define ETHERNET_ADDRESS 0xfffe0778
112
113#endif
114