1#ifndef _ASM_IA64_PGTABLE_H 2#define _ASM_IA64_PGTABLE_H 3 4/* 5 * This file contains the functions and defines necessary to modify and use 6 * the IA-64 page table tree. 7 * 8 * This hopefully works with any (fixed) IA-64 page-size, as defined 9 * in <asm/page.h>. 10 * 11 * Copyright (C) 1998-2005 Hewlett-Packard Co 12 * David Mosberger-Tang <davidm@hpl.hp.com> 13 */ 14 15 16#include <asm/mman.h> 17#include <asm/page.h> 18#include <asm/processor.h> 19#include <asm/system.h> 20#include <asm/types.h> 21 22#define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */ 23 24/* 25 * First, define the various bits in a PTE. Note that the PTE format 26 * matches the VHPT short format, the firt doubleword of the VHPD long 27 * format, and the first doubleword of the TLB insertion format. 28 */ 29#define _PAGE_P_BIT 0 30#define _PAGE_A_BIT 5 31#define _PAGE_D_BIT 6 32 33#define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */ 34#define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */ 35#define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */ 36#define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */ 37#define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */ 38#define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */ 39#define _PAGE_MA_MASK (0x7 << 2) 40#define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */ 41#define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */ 42#define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */ 43#define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */ 44#define _PAGE_PL_MASK (3 << 7) 45#define _PAGE_AR_R (0 << 9) /* read only */ 46#define _PAGE_AR_RX (1 << 9) /* read & execute */ 47#define _PAGE_AR_RW (2 << 9) /* read & write */ 48#define _PAGE_AR_RWX (3 << 9) /* read, write & execute */ 49#define _PAGE_AR_R_RW (4 << 9) /* read / read & write */ 50#define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */ 51#define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */ 52#define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */ 53#define _PAGE_AR_MASK (7 << 9) 54#define _PAGE_AR_SHIFT 9 55#define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */ 56#define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */ 57#define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL) 58#define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */ 59#define _PAGE_PROTNONE (__IA64_UL(1) << 63) 60 61/* Valid only for a PTE with the present bit cleared: */ 62#define _PAGE_FILE (1 << 1) /* see swap & file pte remarks below */ 63 64#define _PFN_MASK _PAGE_PPN_MASK 65/* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */ 66#define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED) 67 68#define _PAGE_SIZE_4K 12 69#define _PAGE_SIZE_8K 13 70#define _PAGE_SIZE_16K 14 71#define _PAGE_SIZE_64K 16 72#define _PAGE_SIZE_256K 18 73#define _PAGE_SIZE_1M 20 74#define _PAGE_SIZE_4M 22 75#define _PAGE_SIZE_16M 24 76#define _PAGE_SIZE_64M 26 77#define _PAGE_SIZE_256M 28 78#define _PAGE_SIZE_1G 30 79#define _PAGE_SIZE_4G 32 80 81#define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB 82#define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB 83#define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED 84 85/* 86 * How many pointers will a page table level hold expressed in shift 87 */ 88#define PTRS_PER_PTD_SHIFT (PAGE_SHIFT-3) 89 90/* 91 * Definitions for fourth level: 92 */ 93#define PTRS_PER_PTE (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT)) 94 95/* 96 * Definitions for third level: 97 * 98 * PMD_SHIFT determines the size of the area a third-level page table 99 * can map. 100 */ 101#define PMD_SHIFT (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT)) 102#define PMD_SIZE (1UL << PMD_SHIFT) 103#define PMD_MASK (~(PMD_SIZE-1)) 104#define PTRS_PER_PMD (1UL << (PTRS_PER_PTD_SHIFT)) 105 106#ifdef CONFIG_PGTABLE_4 107/* 108 * Definitions for second level: 109 * 110 * PUD_SHIFT determines the size of the area a second-level page table 111 * can map. 112 */ 113#define PUD_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT)) 114#define PUD_SIZE (1UL << PUD_SHIFT) 115#define PUD_MASK (~(PUD_SIZE-1)) 116#define PTRS_PER_PUD (1UL << (PTRS_PER_PTD_SHIFT)) 117#endif 118 119/* 120 * Definitions for first level: 121 * 122 * PGDIR_SHIFT determines what a first-level page table entry can map. 123 */ 124#ifdef CONFIG_PGTABLE_4 125#define PGDIR_SHIFT (PUD_SHIFT + (PTRS_PER_PTD_SHIFT)) 126#else 127#define PGDIR_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT)) 128#endif 129#define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT) 130#define PGDIR_MASK (~(PGDIR_SIZE-1)) 131#define PTRS_PER_PGD_SHIFT PTRS_PER_PTD_SHIFT 132#define PTRS_PER_PGD (1UL << PTRS_PER_PGD_SHIFT) 133#define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */ 134#define FIRST_USER_ADDRESS 0 135 136/* 137 * All the normal masks have the "page accessed" bits on, as any time 138 * they are used, the page is accessed. They are cleared only by the 139 * page-out routines. 140 */ 141#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A) 142#define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW) 143#define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R) 144#define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R) 145#define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX) 146#define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX) 147#define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX) 148#define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX) 149 150# ifndef __ASSEMBLY__ 151 152#include <linux/sched.h> /* for mm_struct */ 153#include <asm/bitops.h> 154#include <asm/cacheflush.h> 155#include <asm/mmu_context.h> 156#include <asm/processor.h> 157 158/* 159 * Next come the mappings that determine how mmap() protection bits 160 * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The 161 * _P version gets used for a private shared memory segment, the _S 162 * version gets used for a shared memory segment with MAP_SHARED on. 163 * In a private shared memory segment, we do a copy-on-write if a task 164 * attempts to write to the page. 165 */ 166 /* xwr */ 167#define __P000 PAGE_NONE 168#define __P001 PAGE_READONLY 169#define __P010 PAGE_READONLY /* write to priv pg -> copy & make writable */ 170#define __P011 PAGE_READONLY /* ditto */ 171#define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX) 172#define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX) 173#define __P110 PAGE_COPY_EXEC 174#define __P111 PAGE_COPY_EXEC 175 176#define __S000 PAGE_NONE 177#define __S001 PAGE_READONLY 178#define __S010 PAGE_SHARED /* we don't have (and don't need) write-only */ 179#define __S011 PAGE_SHARED 180#define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX) 181#define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX) 182#define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX) 183#define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX) 184 185#define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 186#ifdef CONFIG_PGTABLE_4 187#define pud_ERROR(e) printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 188#endif 189#define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 190#define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 191 192 193/* 194 * Some definitions to translate between mem_map, PTEs, and page addresses: 195 */ 196 197 198/* Quick test to see if ADDR is a (potentially) valid physical address. */ 199static inline long 200ia64_phys_addr_valid (unsigned long addr) 201{ 202 return (addr & (local_cpu_data->unimpl_pa_mask)) == 0; 203} 204 205#define kern_addr_valid(addr) (1) 206 207 208/* 209 * Now come the defines and routines to manage and access the three-level 210 * page table. 211 */ 212 213/* 214 * On some architectures, special things need to be done when setting 215 * the PTE in a page table. Nothing special needs to be on IA-64. 216 */ 217#define set_pte(ptep, pteval) (*(ptep) = (pteval)) 218#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 219 220#define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL) 221#ifdef CONFIG_VIRTUAL_MEM_MAP 222# define VMALLOC_END_INIT (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9))) 223# define VMALLOC_END vmalloc_end 224 extern unsigned long vmalloc_end; 225#else 226# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9))) 227#endif 228 229/* fs/proc/kcore.c */ 230#define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE)) 231#define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE)) 232 233#define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3) 234#define RGN_MAP_LIMIT ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE) /* per region addr limit */ 235 236/* 237 * Conversion functions: convert page frame number (pfn) and a protection value to a page 238 * table entry (pte). 239 */ 240#define pfn_pte(pfn, pgprot) \ 241({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; }) 242 243/* Extract pfn from pte. */ 244#define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT) 245 246#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 247 248/* This takes a physical page address that is used by the remapping functions */ 249#define mk_pte_phys(physpage, pgprot) \ 250({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; }) 251 252#define pte_modify(_pte, newprot) \ 253 (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK))) 254 255#define pte_none(pte) (!pte_val(pte)) 256#define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE)) 257#define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL) 258/* pte_page() returns the "struct page *" corresponding to the PTE: */ 259#define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET)) 260 261#define pmd_none(pmd) (!pmd_val(pmd)) 262#define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd))) 263#define pmd_present(pmd) (pmd_val(pmd) != 0UL) 264#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) 265#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK)) 266#define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET)) 267 268#define pud_none(pud) (!pud_val(pud)) 269#define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud))) 270#define pud_present(pud) (pud_val(pud) != 0UL) 271#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) 272#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & _PFN_MASK)) 273#define pud_page(pud) virt_to_page((pud_val(pud) + PAGE_OFFSET)) 274 275#ifdef CONFIG_PGTABLE_4 276#define pgd_none(pgd) (!pgd_val(pgd)) 277#define pgd_bad(pgd) (!ia64_phys_addr_valid(pgd_val(pgd))) 278#define pgd_present(pgd) (pgd_val(pgd) != 0UL) 279#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL) 280#define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_val(pgd) & _PFN_MASK)) 281#define pgd_page(pgd) virt_to_page((pgd_val(pgd) + PAGE_OFFSET)) 282#endif 283 284/* 285 * The following have defined behavior only work if pte_present() is true. 286 */ 287#define pte_user(pte) ((pte_val(pte) & _PAGE_PL_MASK) == _PAGE_PL_3) 288#define pte_read(pte) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) < 6) 289#define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4) 290#define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0) 291#define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0) 292#define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0) 293#define pte_file(pte) ((pte_val(pte) & _PAGE_FILE) != 0) 294/* 295 * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the 296 * access rights: 297 */ 298#define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW)) 299#define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW)) 300#define pte_mkexec(pte) (__pte(pte_val(pte) | _PAGE_AR_RX)) 301#define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A)) 302#define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A)) 303#define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D)) 304#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D)) 305#define pte_mkhuge(pte) (__pte(pte_val(pte))) 306 307/* 308 * Make page protection values cacheable, uncacheable, or write- 309 * combining. Note that "protection" is really a misnomer here as the 310 * protection value contains the memory attribute bits, dirty bits, and 311 * various other bits as well. 312 */ 313#define pgprot_cacheable(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB) 314#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC) 315#define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC) 316 317struct file; 318extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 319 unsigned long size, pgprot_t vma_prot); 320#define __HAVE_PHYS_MEM_ACCESS_PROT 321 322static inline unsigned long 323pgd_index (unsigned long address) 324{ 325 unsigned long region = address >> 61; 326 unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1); 327 328 return (region << (PAGE_SHIFT - 6)) | l1index; 329} 330 331/* The offset in the 1-level directory is given by the 3 region bits 332 (61..63) and the level-1 bits. */ 333static inline pgd_t* 334pgd_offset (struct mm_struct *mm, unsigned long address) 335{ 336 return mm->pgd + pgd_index(address); 337} 338 339/* In the kernel's mapped region we completely ignore the region number 340 (since we know it's in region number 5). */ 341#define pgd_offset_k(addr) \ 342 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))) 343 344/* Look up a pgd entry in the gate area. On IA-64, the gate-area 345 resides in the kernel-mapped segment, hence we use pgd_offset_k() 346 here. */ 347#define pgd_offset_gate(mm, addr) pgd_offset_k(addr) 348 349#ifdef CONFIG_PGTABLE_4 350/* Find an entry in the second-level page table.. */ 351#define pud_offset(dir,addr) \ 352 ((pud_t *) pgd_page_vaddr(*(dir)) + (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))) 353#endif 354 355/* Find an entry in the third-level page table.. */ 356#define pmd_offset(dir,addr) \ 357 ((pmd_t *) pud_page_vaddr(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))) 358 359/* 360 * Find an entry in the third-level page table. This looks more complicated than it 361 * should be because some platforms place page tables in high memory. 362 */ 363#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 364#define pte_offset_kernel(dir,addr) ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr)) 365#define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr) 366#define pte_offset_map_nested(dir,addr) pte_offset_map(dir, addr) 367#define pte_unmap(pte) do { } while (0) 368#define pte_unmap_nested(pte) do { } while (0) 369 370/* atomic versions of the some PTE manipulations: */ 371 372static inline int 373ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) 374{ 375#ifdef CONFIG_SMP 376 if (!pte_young(*ptep)) 377 return 0; 378 return test_and_clear_bit(_PAGE_A_BIT, ptep); 379#else 380 pte_t pte = *ptep; 381 if (!pte_young(pte)) 382 return 0; 383 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte)); 384 return 1; 385#endif 386} 387 388static inline int 389ptep_test_and_clear_dirty (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) 390{ 391#ifdef CONFIG_SMP 392 if (!pte_dirty(*ptep)) 393 return 0; 394 return test_and_clear_bit(_PAGE_D_BIT, ptep); 395#else 396 pte_t pte = *ptep; 397 if (!pte_dirty(pte)) 398 return 0; 399 set_pte_at(vma->vm_mm, addr, ptep, pte_mkclean(pte)); 400 return 1; 401#endif 402} 403 404static inline pte_t 405ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 406{ 407#ifdef CONFIG_SMP 408 return __pte(xchg((long *) ptep, 0)); 409#else 410 pte_t pte = *ptep; 411 pte_clear(mm, addr, ptep); 412 return pte; 413#endif 414} 415 416static inline void 417ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 418{ 419#ifdef CONFIG_SMP 420 unsigned long new, old; 421 422 do { 423 old = pte_val(*ptep); 424 new = pte_val(pte_wrprotect(__pte (old))); 425 } while (cmpxchg((unsigned long *) ptep, old, new) != old); 426#else 427 pte_t old_pte = *ptep; 428 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte)); 429#endif 430} 431 432static inline int 433pte_same (pte_t a, pte_t b) 434{ 435 return pte_val(a) == pte_val(b); 436} 437 438#define update_mmu_cache(vma, address, pte) do { } while (0) 439 440extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 441extern void paging_init (void); 442 443/* 444 * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of 445 * bits in the swap-type field of the swap pte. It would be nice to 446 * enforce that, but we can't easily include <linux/swap.h> here. 447 * (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...). 448 * 449 * Format of swap pte: 450 * bit 0 : present bit (must be zero) 451 * bit 1 : _PAGE_FILE (must be zero) 452 * bits 2- 8: swap-type 453 * bits 9-62: swap offset 454 * bit 63 : _PAGE_PROTNONE bit 455 * 456 * Format of file pte: 457 * bit 0 : present bit (must be zero) 458 * bit 1 : _PAGE_FILE (must be one) 459 * bits 2-62: file_offset/PAGE_SIZE 460 * bit 63 : _PAGE_PROTNONE bit 461 */ 462#define __swp_type(entry) (((entry).val >> 2) & 0x7f) 463#define __swp_offset(entry) (((entry).val << 1) >> 10) 464#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((long) (offset) << 9) }) 465#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 466#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 467 468#define PTE_FILE_MAX_BITS 61 469#define pte_to_pgoff(pte) ((pte_val(pte) << 1) >> 3) 470#define pgoff_to_pte(off) ((pte_t) { ((off) << 2) | _PAGE_FILE }) 471 472#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ 473 remap_pfn_range(vma, vaddr, pfn, size, prot) 474 475/* 476 * ZERO_PAGE is a global shared page that is always zero: used 477 * for zero-mapped memory areas etc.. 478 */ 479extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)]; 480extern struct page *zero_page_memmap_ptr; 481#define ZERO_PAGE(vaddr) (zero_page_memmap_ptr) 482 483/* We provide our own get_unmapped_area to cope with VA holes for userland */ 484#define HAVE_ARCH_UNMAPPED_AREA 485 486#ifdef CONFIG_HUGETLB_PAGE 487#define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3)) 488#define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT) 489#define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1)) 490#endif 491 492/* 493 * IA-64 doesn't have any external MMU info: the page tables contain all the necessary 494 * information. However, we use this routine to take care of any (delayed) i-cache 495 * flushing that may be necessary. 496 */ 497extern void lazy_mmu_prot_update (pte_t pte); 498 499#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 500/* 501 * Update PTEP with ENTRY, which is guaranteed to be a less 502 * restrictive PTE. That is, ENTRY may have the ACCESSED, DIRTY, and 503 * WRITABLE bits turned on, when the value at PTEP did not. The 504 * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE. 505 * 506 * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without 507 * having to worry about races. On SMP machines, there are only two 508 * cases where this is true: 509 * 510 * (1) *PTEP has the PRESENT bit turned OFF 511 * (2) ENTRY has the DIRTY bit turned ON 512 * 513 * On ia64, we could implement this routine with a cmpxchg()-loop 514 * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY. 515 * However, like on x86, we can get a more streamlined version by 516 * observing that it is OK to drop ACCESSED bit updates when 517 * SAFELY_WRITABLE is FALSE. Besides being rare, all that would do is 518 * result in an extra Access-bit fault, which would then turn on the 519 * ACCESSED bit in the low-level fault handler (iaccess_bit or 520 * daccess_bit in ivt.S). 521 */ 522#ifdef CONFIG_SMP 523# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ 524({ \ 525 int __changed = !pte_same(*(__ptep), __entry); \ 526 if (__changed && __safely_writable) { \ 527 set_pte(__ptep, __entry); \ 528 flush_tlb_page(__vma, __addr); \ 529 } \ 530 __changed; \ 531}) 532#else 533# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ 534({ \ 535 int __changed = !pte_same(*(__ptep), __entry); \ 536 if (__changed) \ 537 ptep_establish(__vma, __addr, __ptep, __entry); \ 538 __changed; \ 539}) 540#endif 541 542# ifdef CONFIG_VIRTUAL_MEM_MAP 543 /* arch mem_map init routine is needed due to holes in a virtual mem_map */ 544# define __HAVE_ARCH_MEMMAP_INIT 545 extern void memmap_init (unsigned long size, int nid, unsigned long zone, 546 unsigned long start_pfn); 547# endif /* CONFIG_VIRTUAL_MEM_MAP */ 548# endif /* !__ASSEMBLY__ */ 549 550/* 551 * Identity-mapped regions use a large page size. We'll call such large pages 552 * "granules". If you can think of a better name that's unambiguous, let me 553 * know... 554 */ 555#if defined(CONFIG_IA64_GRANULE_64MB) 556# define IA64_GRANULE_SHIFT _PAGE_SIZE_64M 557#elif defined(CONFIG_IA64_GRANULE_16MB) 558# define IA64_GRANULE_SHIFT _PAGE_SIZE_16M 559#endif 560#define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT) 561/* 562 * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL): 563 */ 564#define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M 565#define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT) 566 567/* 568 * No page table caches to initialise 569 */ 570#define pgtable_cache_init() do { } while (0) 571 572/* These tell get_user_pages() that the first gate page is accessible from user-level. */ 573#define FIXADDR_USER_START GATE_ADDR 574#ifdef HAVE_BUGGY_SEGREL 575# define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE) 576#else 577# define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE) 578#endif 579 580#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 581#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY 582#define __HAVE_ARCH_PTEP_GET_AND_CLEAR 583#define __HAVE_ARCH_PTEP_SET_WRPROTECT 584#define __HAVE_ARCH_PTE_SAME 585#define __HAVE_ARCH_PGD_OFFSET_GATE 586#define __HAVE_ARCH_LAZY_MMU_PROT_UPDATE 587 588#ifndef CONFIG_PGTABLE_4 589#include <asm-generic/pgtable-nopud.h> 590#endif 591#include <asm-generic/pgtable.h> 592 593#endif /* _ASM_IA64_PGTABLE_H */ 594