1#ifndef __I386_SGI_PIIX_H 2#define __I386_SGI_PIIX_H 3 4/* 5 * PIIX4 as used on SGI Visual Workstations 6 */ 7 8#define PIIX_PM_START 0x0F80 9 10#define SIO_GPIO_START 0x0FC0 11 12#define SIO_PM_START 0x0FC8 13 14#define PMBASE PIIX_PM_START 15#define GPIREG0 (PMBASE+0x30) 16#define GPIREG(x) (GPIREG0+((x)/8)) 17#define GPIBIT(x) (1 << ((x)%8)) 18 19#define PIIX_GPI_BD_ID1 18 20#define PIIX_GPI_BD_ID2 19 21#define PIIX_GPI_BD_ID3 20 22#define PIIX_GPI_BD_ID4 21 23#define PIIX_GPI_BD_REG GPIREG(PIIX_GPI_BD_ID1) 24#define PIIX_GPI_BD_MASK (GPIBIT(PIIX_GPI_BD_ID1) | \ 25 GPIBIT(PIIX_GPI_BD_ID2) | \ 26 GPIBIT(PIIX_GPI_BD_ID3) | \ 27 GPIBIT(PIIX_GPI_BD_ID4) ) 28 29#define PIIX_GPI_BD_SHIFT (PIIX_GPI_BD_ID1 % 8) 30 31#define SIO_INDEX 0x2e 32#define SIO_DATA 0x2f 33 34#define SIO_DEV_SEL 0x7 35#define SIO_DEV_ENB 0x30 36#define SIO_DEV_MSB 0x60 37#define SIO_DEV_LSB 0x61 38 39#define SIO_GP_DEV 0x7 40 41#define SIO_GP_BASE SIO_GPIO_START 42#define SIO_GP_MSB (SIO_GP_BASE>>8) 43#define SIO_GP_LSB (SIO_GP_BASE&0xff) 44 45#define SIO_GP_DATA1 (SIO_GP_BASE+0) 46 47#define SIO_PM_DEV 0x8 48 49#define SIO_PM_BASE SIO_PM_START 50#define SIO_PM_MSB (SIO_PM_BASE>>8) 51#define SIO_PM_LSB (SIO_PM_BASE&0xff) 52#define SIO_PM_INDEX (SIO_PM_BASE+0) 53#define SIO_PM_DATA (SIO_PM_BASE+1) 54 55#define SIO_PM_FER2 0x1 56 57#define SIO_PM_GP_EN 0x80 58 59 60 61/* 62 * This is the dev/reg where generating a config cycle will 63 * result in a PCI special cycle. 64 */ 65#define SPECIAL_DEV 0xff 66#define SPECIAL_REG 0x00 67 68/* 69 * PIIX4 needs to see a special cycle with the following data 70 * to be convinced the processor has gone into the stop grant 71 * state. PIIX4 insists on seeing this before it will power 72 * down a system. 73 */ 74#define PIIX_SPECIAL_STOP 0x00120002 75 76#define PIIX4_RESET_PORT 0xcf9 77#define PIIX4_RESET_VAL 0x6 78 79#define PMSTS_PORT 0xf80 // 2 bytes PM Status 80#define PMEN_PORT 0xf82 // 2 bytes PM Enable 81#define PMCNTRL_PORT 0xf84 // 2 bytes PM Control 82 83#define PM_SUSPEND_ENABLE 0x2000 // start sequence to suspend state 84 85/* 86 * PMSTS and PMEN I/O bit definitions. 87 * (Bits are the same in both registers) 88 */ 89#define PM_STS_RSM (1<<15) // Resume Status 90#define PM_STS_PWRBTNOR (1<<11) // Power Button Override 91#define PM_STS_RTC (1<<10) // RTC status 92#define PM_STS_PWRBTN (1<<8) // Power Button Pressed? 93#define PM_STS_GBL (1<<5) // Global Status 94#define PM_STS_BM (1<<4) // Bus Master Status 95#define PM_STS_TMROF (1<<0) // Timer Overflow Status. 96 97/* 98 * Stop clock GPI register 99 */ 100#define PIIX_GPIREG0 (0xf80 + 0x30) 101 102/* 103 * Stop clock GPI bit in GPIREG0 104 */ 105#define PIIX_GPI_STPCLK 0x4 // STPCLK signal routed back in 106 107#endif 108