1/* dma.h: FRV DMA controller management
2 *
3 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef _ASM_DMA_H
13#define _ASM_DMA_H
14
15//#define DMA_DEBUG 1
16
17#include <linux/interrupt.h>
18
19#undef MAX_DMA_CHANNELS		/* don't use kernel/dma.c */
20
21/* under 2.4 this is actually needed by the new bootmem allocator */
22#define MAX_DMA_ADDRESS		PAGE_OFFSET
23
24/*
25 * FRV DMA controller management
26 */
27typedef irqreturn_t (*dma_irq_handler_t)(int dmachan, unsigned long cstr, void *data);
28
29extern void frv_dma_init(void);
30
31extern int frv_dma_open(const char *devname,
32			unsigned long dmamask,
33			int dmacap,
34			dma_irq_handler_t handler,
35			unsigned long irq_flags,
36			void *data);
37
38/* channels required */
39#define FRV_DMA_MASK_ANY	ULONG_MAX	/* any channel */
40
41/* capabilities required */
42#define FRV_DMA_CAP_DREQ	0x01		/* DMA request pin */
43#define FRV_DMA_CAP_DACK	0x02		/* DMA ACK pin */
44#define FRV_DMA_CAP_DONE	0x04		/* DMA done pin */
45
46extern void frv_dma_close(int dma);
47
48extern void frv_dma_config(int dma, unsigned long ccfr, unsigned long cctr, unsigned long apr);
49
50extern void frv_dma_start(int dma,
51			  unsigned long sba, unsigned long dba,
52			  unsigned long pix, unsigned long six, unsigned long bcl);
53
54extern void frv_dma_restart_circular(int dma, unsigned long six);
55
56extern void frv_dma_stop(int dma);
57
58extern int is_frv_dma_interrupting(int dma);
59
60extern void frv_dma_dump(int dma);
61
62extern void frv_dma_status_clear(int dma);
63
64#define FRV_DMA_NCHANS	8
65#define FRV_DMA_4CHANS	4
66#define FRV_DMA_8CHANS	8
67
68#define DMAC_CCFRx		0x00	/* channel configuration reg */
69#define DMAC_CCFRx_CM_SHIFT	16
70#define DMAC_CCFRx_CM_DA	0x00000000
71#define DMAC_CCFRx_CM_SCA	0x00010000
72#define DMAC_CCFRx_CM_DCA	0x00020000
73#define DMAC_CCFRx_CM_2D	0x00030000
74#define DMAC_CCFRx_ATS_SHIFT	8
75#define DMAC_CCFRx_RS_INTERN	0x00000000
76#define DMAC_CCFRx_RS_EXTERN	0x00000001
77#define DMAC_CCFRx_RS_SHIFT	0
78
79#define DMAC_CSTRx		0x08	/* channel status reg */
80#define DMAC_CSTRx_FS		0x0000003f
81#define DMAC_CSTRx_NE		0x00000100
82#define DMAC_CSTRx_FED		0x00000200
83#define DMAC_CSTRx_WER		0x00000800
84#define DMAC_CSTRx_RER		0x00001000
85#define DMAC_CSTRx_CE		0x00002000
86#define DMAC_CSTRx_INT		0x00800000
87#define DMAC_CSTRx_BUSY		0x80000000
88
89#define DMAC_CCTRx		0x10	/* channel control reg */
90#define DMAC_CCTRx_DSIZ_1	0x00000000
91#define DMAC_CCTRx_DSIZ_2	0x00000001
92#define DMAC_CCTRx_DSIZ_4	0x00000002
93#define DMAC_CCTRx_DSIZ_32	0x00000005
94#define DMAC_CCTRx_DAU_HOLD	0x00000000
95#define DMAC_CCTRx_DAU_INC	0x00000010
96#define DMAC_CCTRx_DAU_DEC	0x00000020
97#define DMAC_CCTRx_SSIZ_1	0x00000000
98#define DMAC_CCTRx_SSIZ_2	0x00000100
99#define DMAC_CCTRx_SSIZ_4	0x00000200
100#define DMAC_CCTRx_SSIZ_32	0x00000500
101#define DMAC_CCTRx_SAU_HOLD	0x00000000
102#define DMAC_CCTRx_SAU_INC	0x00001000
103#define DMAC_CCTRx_SAU_DEC	0x00002000
104#define DMAC_CCTRx_FC		0x08000000
105#define DMAC_CCTRx_ICE		0x10000000
106#define DMAC_CCTRx_IE		0x40000000
107#define DMAC_CCTRx_ACT		0x80000000
108
109#define DMAC_SBAx		0x18	/* source base address reg */
110#define DMAC_DBAx		0x20	/* data base address reg */
111#define DMAC_PIXx		0x28	/* primary index reg */
112#define DMAC_SIXx		0x30	/* secondary index reg */
113#define DMAC_BCLx		0x38	/* byte count limit reg */
114#define DMAC_APRx		0x40	/* alternate pointer reg */
115
116/*
117 * required for PCI + MODULES
118 */
119#ifdef CONFIG_PCI
120extern int isa_dma_bridge_buggy;
121#else
122#define isa_dma_bridge_buggy 	(0)
123#endif
124
125#endif /* _ASM_DMA_H */
126