1#ifndef __iop_timer_grp_defs_h 2#define __iop_timer_grp_defs_h 3 4/* 5 * This file is autogenerated from 6 * file: ../../inst/io_proc/rtl/iop_timer_grp.r 7 * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp 8 * last modfied: Mon Apr 11 16:08:46 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r 11 * id: $Id: iop_timer_grp_defs.h,v 1.1.1.1 2007/08/03 18:53:23 Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16/* Main access macros */ 17#ifndef REG_RD 18#define REG_RD( scope, inst, reg ) \ 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 21#endif 22 23#ifndef REG_WR 24#define REG_WR( scope, inst, reg, val ) \ 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27#endif 28 29#ifndef REG_RD_VECT 30#define REG_RD_VECT( scope, inst, reg, index ) \ 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) 34#endif 35 36#ifndef REG_WR_VECT 37#define REG_WR_VECT( scope, inst, reg, index, val ) \ 38 REG_WRITE( reg_##scope##_##reg, \ 39 (inst) + REG_WR_ADDR_##scope##_##reg + \ 40 (index) * STRIDE_##scope##_##reg, (val) ) 41#endif 42 43#ifndef REG_RD_INT 44#define REG_RD_INT( scope, inst, reg ) \ 45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 46#endif 47 48#ifndef REG_WR_INT 49#define REG_WR_INT( scope, inst, reg, val ) \ 50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 51#endif 52 53#ifndef REG_RD_INT_VECT 54#define REG_RD_INT_VECT( scope, inst, reg, index ) \ 55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 56 (index) * STRIDE_##scope##_##reg ) 57#endif 58 59#ifndef REG_WR_INT_VECT 60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 62 (index) * STRIDE_##scope##_##reg, (val) ) 63#endif 64 65#ifndef REG_TYPE_CONV 66#define REG_TYPE_CONV( type, orgtype, val ) \ 67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 68#endif 69 70#ifndef reg_page_size 71#define reg_page_size 8192 72#endif 73 74#ifndef REG_ADDR 75#define REG_ADDR( scope, inst, reg ) \ 76 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 77#endif 78 79#ifndef REG_ADDR_VECT 80#define REG_ADDR_VECT( scope, inst, reg, index ) \ 81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 82 (index) * STRIDE_##scope##_##reg ) 83#endif 84 85/* C-code for register scope iop_timer_grp */ 86 87/* Register rw_cfg, scope iop_timer_grp, type rw */ 88typedef struct { 89 unsigned int clk_src : 1; 90 unsigned int trig : 2; 91 unsigned int clk_gen_div : 8; 92 unsigned int clk_div : 8; 93 unsigned int dummy1 : 13; 94} reg_iop_timer_grp_rw_cfg; 95#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0 96#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0 97 98/* Register rw_half_period, scope iop_timer_grp, type rw */ 99typedef struct { 100 unsigned int quota_lo : 15; 101 unsigned int quota_hi : 15; 102 unsigned int quota_hi_sel : 1; 103 unsigned int dummy1 : 1; 104} reg_iop_timer_grp_rw_half_period; 105#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4 106#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4 107 108/* Register rw_half_period_len, scope iop_timer_grp, type rw */ 109typedef unsigned int reg_iop_timer_grp_rw_half_period_len; 110#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8 111#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8 112 113#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 114/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ 115typedef struct { 116 unsigned int clk_src : 3; 117 unsigned int strb : 2; 118 unsigned int run_mode : 2; 119 unsigned int out_mode : 1; 120 unsigned int active_on_tmr : 2; 121 unsigned int inv : 1; 122 unsigned int en_by_tmr : 2; 123 unsigned int dis_by_tmr : 2; 124 unsigned int en_only_by_reg : 1; 125 unsigned int dis_only_by_reg : 1; 126 unsigned int rst_at_en_strb : 1; 127 unsigned int dummy1 : 14; 128} reg_iop_timer_grp_rw_tmr_cfg; 129#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12 130#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12 131 132#define STRIDE_iop_timer_grp_rw_tmr_len 4 133/* Register rw_tmr_len, scope iop_timer_grp, type rw */ 134typedef struct { 135 unsigned int val : 16; 136 unsigned int dummy1 : 16; 137} reg_iop_timer_grp_rw_tmr_len; 138#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44 139#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44 140 141/* Register rw_cmd, scope iop_timer_grp, type rw */ 142typedef struct { 143 unsigned int rst : 4; 144 unsigned int en : 4; 145 unsigned int dis : 4; 146 unsigned int strb : 4; 147 unsigned int dummy1 : 16; 148} reg_iop_timer_grp_rw_cmd; 149#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60 150#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60 151 152/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ 153typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt; 154#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64 155 156#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 157/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ 158typedef struct { 159 unsigned int val : 16; 160 unsigned int dummy1 : 16; 161} reg_iop_timer_grp_rs_tmr_cnt; 162#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68 163 164#define STRIDE_iop_timer_grp_r_tmr_cnt 8 165/* Register r_tmr_cnt, scope iop_timer_grp, type r */ 166typedef struct { 167 unsigned int val : 16; 168 unsigned int dummy1 : 16; 169} reg_iop_timer_grp_r_tmr_cnt; 170#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72 171 172/* Register rw_intr_mask, scope iop_timer_grp, type rw */ 173typedef struct { 174 unsigned int tmr0 : 1; 175 unsigned int tmr1 : 1; 176 unsigned int tmr2 : 1; 177 unsigned int tmr3 : 1; 178 unsigned int dummy1 : 28; 179} reg_iop_timer_grp_rw_intr_mask; 180#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100 181#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100 182 183/* Register rw_ack_intr, scope iop_timer_grp, type rw */ 184typedef struct { 185 unsigned int tmr0 : 1; 186 unsigned int tmr1 : 1; 187 unsigned int tmr2 : 1; 188 unsigned int tmr3 : 1; 189 unsigned int dummy1 : 28; 190} reg_iop_timer_grp_rw_ack_intr; 191#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104 192#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104 193 194/* Register r_intr, scope iop_timer_grp, type r */ 195typedef struct { 196 unsigned int tmr0 : 1; 197 unsigned int tmr1 : 1; 198 unsigned int tmr2 : 1; 199 unsigned int tmr3 : 1; 200 unsigned int dummy1 : 28; 201} reg_iop_timer_grp_r_intr; 202#define REG_RD_ADDR_iop_timer_grp_r_intr 108 203 204/* Register r_masked_intr, scope iop_timer_grp, type r */ 205typedef struct { 206 unsigned int tmr0 : 1; 207 unsigned int tmr1 : 1; 208 unsigned int tmr2 : 1; 209 unsigned int tmr3 : 1; 210 unsigned int dummy1 : 28; 211} reg_iop_timer_grp_r_masked_intr; 212#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112 213 214 215/* Constants */ 216enum { 217 regk_iop_timer_grp_clk200 = 0x00000000, 218 regk_iop_timer_grp_clk_gen = 0x00000002, 219 regk_iop_timer_grp_complete = 0x00000002, 220 regk_iop_timer_grp_div_clk200 = 0x00000001, 221 regk_iop_timer_grp_div_clk_gen = 0x00000003, 222 regk_iop_timer_grp_ext = 0x00000001, 223 regk_iop_timer_grp_hi = 0x00000000, 224 regk_iop_timer_grp_long_period = 0x00000001, 225 regk_iop_timer_grp_neg = 0x00000002, 226 regk_iop_timer_grp_no = 0x00000000, 227 regk_iop_timer_grp_once = 0x00000003, 228 regk_iop_timer_grp_pause = 0x00000001, 229 regk_iop_timer_grp_pos = 0x00000001, 230 regk_iop_timer_grp_pos_neg = 0x00000003, 231 regk_iop_timer_grp_pulse = 0x00000000, 232 regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004, 233 regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004, 234 regk_iop_timer_grp_rw_cfg_default = 0x00000002, 235 regk_iop_timer_grp_rw_intr_mask_default = 0x00000000, 236 regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000, 237 regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900, 238 regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200, 239 regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00, 240 regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004, 241 regk_iop_timer_grp_rw_tmr_len_default = 0x00000000, 242 regk_iop_timer_grp_rw_tmr_len_size = 0x00000004, 243 regk_iop_timer_grp_short_period = 0x00000000, 244 regk_iop_timer_grp_stop = 0x00000000, 245 regk_iop_timer_grp_tmr = 0x00000004, 246 regk_iop_timer_grp_toggle = 0x00000001, 247 regk_iop_timer_grp_yes = 0x00000001 248}; 249#endif /* __iop_timer_grp_defs_h */ 250