1#ifndef __ser_defs_asm_h 2#define __ser_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: ../../inst/ser/rtl/ser_regs.r 7 * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp 8 * last modfied: Mon Apr 11 16:09:21 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r 11 * id: $Id: ser_defs_asm.h,v 1.1.1.1 2007/08/03 18:53:23 Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17#ifndef REG_FIELD 18#define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20#define REG_FIELD_X_( value, shift ) ((value) << shift) 21#endif 22 23#ifndef REG_STATE 24#define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26#define REG_STATE_X_( k, shift ) (k << shift) 27#endif 28 29#ifndef REG_MASK 30#define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33#endif 34 35#ifndef REG_LSB 36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37#endif 38 39#ifndef REG_BIT 40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41#endif 42 43#ifndef REG_ADDR 44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46#endif 47 48#ifndef REG_ADDR_VECT 49#define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54#endif 55 56/* Register rw_tr_ctrl, scope ser, type rw */ 57#define reg_ser_rw_tr_ctrl___base_freq___lsb 0 58#define reg_ser_rw_tr_ctrl___base_freq___width 3 59#define reg_ser_rw_tr_ctrl___en___lsb 3 60#define reg_ser_rw_tr_ctrl___en___width 1 61#define reg_ser_rw_tr_ctrl___en___bit 3 62#define reg_ser_rw_tr_ctrl___par___lsb 4 63#define reg_ser_rw_tr_ctrl___par___width 2 64#define reg_ser_rw_tr_ctrl___par_en___lsb 6 65#define reg_ser_rw_tr_ctrl___par_en___width 1 66#define reg_ser_rw_tr_ctrl___par_en___bit 6 67#define reg_ser_rw_tr_ctrl___data_bits___lsb 7 68#define reg_ser_rw_tr_ctrl___data_bits___width 1 69#define reg_ser_rw_tr_ctrl___data_bits___bit 7 70#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8 71#define reg_ser_rw_tr_ctrl___stop_bits___width 1 72#define reg_ser_rw_tr_ctrl___stop_bits___bit 8 73#define reg_ser_rw_tr_ctrl___stop___lsb 9 74#define reg_ser_rw_tr_ctrl___stop___width 1 75#define reg_ser_rw_tr_ctrl___stop___bit 9 76#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10 77#define reg_ser_rw_tr_ctrl___rts_delay___width 3 78#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13 79#define reg_ser_rw_tr_ctrl___rts_setup___width 1 80#define reg_ser_rw_tr_ctrl___rts_setup___bit 13 81#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14 82#define reg_ser_rw_tr_ctrl___auto_rts___width 1 83#define reg_ser_rw_tr_ctrl___auto_rts___bit 14 84#define reg_ser_rw_tr_ctrl___txd___lsb 15 85#define reg_ser_rw_tr_ctrl___txd___width 1 86#define reg_ser_rw_tr_ctrl___txd___bit 15 87#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16 88#define reg_ser_rw_tr_ctrl___auto_cts___width 1 89#define reg_ser_rw_tr_ctrl___auto_cts___bit 16 90#define reg_ser_rw_tr_ctrl_offset 0 91 92/* Register rw_tr_dma_en, scope ser, type rw */ 93#define reg_ser_rw_tr_dma_en___en___lsb 0 94#define reg_ser_rw_tr_dma_en___en___width 1 95#define reg_ser_rw_tr_dma_en___en___bit 0 96#define reg_ser_rw_tr_dma_en_offset 4 97 98/* Register rw_rec_ctrl, scope ser, type rw */ 99#define reg_ser_rw_rec_ctrl___base_freq___lsb 0 100#define reg_ser_rw_rec_ctrl___base_freq___width 3 101#define reg_ser_rw_rec_ctrl___en___lsb 3 102#define reg_ser_rw_rec_ctrl___en___width 1 103#define reg_ser_rw_rec_ctrl___en___bit 3 104#define reg_ser_rw_rec_ctrl___par___lsb 4 105#define reg_ser_rw_rec_ctrl___par___width 2 106#define reg_ser_rw_rec_ctrl___par_en___lsb 6 107#define reg_ser_rw_rec_ctrl___par_en___width 1 108#define reg_ser_rw_rec_ctrl___par_en___bit 6 109#define reg_ser_rw_rec_ctrl___data_bits___lsb 7 110#define reg_ser_rw_rec_ctrl___data_bits___width 1 111#define reg_ser_rw_rec_ctrl___data_bits___bit 7 112#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8 113#define reg_ser_rw_rec_ctrl___dma_mode___width 1 114#define reg_ser_rw_rec_ctrl___dma_mode___bit 8 115#define reg_ser_rw_rec_ctrl___dma_err___lsb 9 116#define reg_ser_rw_rec_ctrl___dma_err___width 1 117#define reg_ser_rw_rec_ctrl___dma_err___bit 9 118#define reg_ser_rw_rec_ctrl___sampling___lsb 10 119#define reg_ser_rw_rec_ctrl___sampling___width 1 120#define reg_ser_rw_rec_ctrl___sampling___bit 10 121#define reg_ser_rw_rec_ctrl___timeout___lsb 11 122#define reg_ser_rw_rec_ctrl___timeout___width 3 123#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14 124#define reg_ser_rw_rec_ctrl___auto_eop___width 1 125#define reg_ser_rw_rec_ctrl___auto_eop___bit 14 126#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15 127#define reg_ser_rw_rec_ctrl___half_duplex___width 1 128#define reg_ser_rw_rec_ctrl___half_duplex___bit 15 129#define reg_ser_rw_rec_ctrl___rts_n___lsb 16 130#define reg_ser_rw_rec_ctrl___rts_n___width 1 131#define reg_ser_rw_rec_ctrl___rts_n___bit 16 132#define reg_ser_rw_rec_ctrl___loopback___lsb 17 133#define reg_ser_rw_rec_ctrl___loopback___width 1 134#define reg_ser_rw_rec_ctrl___loopback___bit 17 135#define reg_ser_rw_rec_ctrl_offset 8 136 137/* Register rw_tr_baud_div, scope ser, type rw */ 138#define reg_ser_rw_tr_baud_div___div___lsb 0 139#define reg_ser_rw_tr_baud_div___div___width 16 140#define reg_ser_rw_tr_baud_div_offset 12 141 142/* Register rw_rec_baud_div, scope ser, type rw */ 143#define reg_ser_rw_rec_baud_div___div___lsb 0 144#define reg_ser_rw_rec_baud_div___div___width 16 145#define reg_ser_rw_rec_baud_div_offset 16 146 147/* Register rw_xoff, scope ser, type rw */ 148#define reg_ser_rw_xoff___chr___lsb 0 149#define reg_ser_rw_xoff___chr___width 8 150#define reg_ser_rw_xoff___automatic___lsb 8 151#define reg_ser_rw_xoff___automatic___width 1 152#define reg_ser_rw_xoff___automatic___bit 8 153#define reg_ser_rw_xoff_offset 20 154 155/* Register rw_xoff_clr, scope ser, type rw */ 156#define reg_ser_rw_xoff_clr___clr___lsb 0 157#define reg_ser_rw_xoff_clr___clr___width 1 158#define reg_ser_rw_xoff_clr___clr___bit 0 159#define reg_ser_rw_xoff_clr_offset 24 160 161/* Register rw_dout, scope ser, type rw */ 162#define reg_ser_rw_dout___data___lsb 0 163#define reg_ser_rw_dout___data___width 8 164#define reg_ser_rw_dout_offset 28 165 166/* Register rs_stat_din, scope ser, type rs */ 167#define reg_ser_rs_stat_din___data___lsb 0 168#define reg_ser_rs_stat_din___data___width 8 169#define reg_ser_rs_stat_din___dav___lsb 16 170#define reg_ser_rs_stat_din___dav___width 1 171#define reg_ser_rs_stat_din___dav___bit 16 172#define reg_ser_rs_stat_din___framing_err___lsb 17 173#define reg_ser_rs_stat_din___framing_err___width 1 174#define reg_ser_rs_stat_din___framing_err___bit 17 175#define reg_ser_rs_stat_din___par_err___lsb 18 176#define reg_ser_rs_stat_din___par_err___width 1 177#define reg_ser_rs_stat_din___par_err___bit 18 178#define reg_ser_rs_stat_din___orun___lsb 19 179#define reg_ser_rs_stat_din___orun___width 1 180#define reg_ser_rs_stat_din___orun___bit 19 181#define reg_ser_rs_stat_din___rec_err___lsb 20 182#define reg_ser_rs_stat_din___rec_err___width 1 183#define reg_ser_rs_stat_din___rec_err___bit 20 184#define reg_ser_rs_stat_din___rxd___lsb 21 185#define reg_ser_rs_stat_din___rxd___width 1 186#define reg_ser_rs_stat_din___rxd___bit 21 187#define reg_ser_rs_stat_din___tr_idle___lsb 22 188#define reg_ser_rs_stat_din___tr_idle___width 1 189#define reg_ser_rs_stat_din___tr_idle___bit 22 190#define reg_ser_rs_stat_din___tr_empty___lsb 23 191#define reg_ser_rs_stat_din___tr_empty___width 1 192#define reg_ser_rs_stat_din___tr_empty___bit 23 193#define reg_ser_rs_stat_din___tr_rdy___lsb 24 194#define reg_ser_rs_stat_din___tr_rdy___width 1 195#define reg_ser_rs_stat_din___tr_rdy___bit 24 196#define reg_ser_rs_stat_din___cts_n___lsb 25 197#define reg_ser_rs_stat_din___cts_n___width 1 198#define reg_ser_rs_stat_din___cts_n___bit 25 199#define reg_ser_rs_stat_din___xoff_detect___lsb 26 200#define reg_ser_rs_stat_din___xoff_detect___width 1 201#define reg_ser_rs_stat_din___xoff_detect___bit 26 202#define reg_ser_rs_stat_din___rts_n___lsb 27 203#define reg_ser_rs_stat_din___rts_n___width 1 204#define reg_ser_rs_stat_din___rts_n___bit 27 205#define reg_ser_rs_stat_din___txd___lsb 28 206#define reg_ser_rs_stat_din___txd___width 1 207#define reg_ser_rs_stat_din___txd___bit 28 208#define reg_ser_rs_stat_din_offset 32 209 210/* Register r_stat_din, scope ser, type r */ 211#define reg_ser_r_stat_din___data___lsb 0 212#define reg_ser_r_stat_din___data___width 8 213#define reg_ser_r_stat_din___dav___lsb 16 214#define reg_ser_r_stat_din___dav___width 1 215#define reg_ser_r_stat_din___dav___bit 16 216#define reg_ser_r_stat_din___framing_err___lsb 17 217#define reg_ser_r_stat_din___framing_err___width 1 218#define reg_ser_r_stat_din___framing_err___bit 17 219#define reg_ser_r_stat_din___par_err___lsb 18 220#define reg_ser_r_stat_din___par_err___width 1 221#define reg_ser_r_stat_din___par_err___bit 18 222#define reg_ser_r_stat_din___orun___lsb 19 223#define reg_ser_r_stat_din___orun___width 1 224#define reg_ser_r_stat_din___orun___bit 19 225#define reg_ser_r_stat_din___rec_err___lsb 20 226#define reg_ser_r_stat_din___rec_err___width 1 227#define reg_ser_r_stat_din___rec_err___bit 20 228#define reg_ser_r_stat_din___rxd___lsb 21 229#define reg_ser_r_stat_din___rxd___width 1 230#define reg_ser_r_stat_din___rxd___bit 21 231#define reg_ser_r_stat_din___tr_idle___lsb 22 232#define reg_ser_r_stat_din___tr_idle___width 1 233#define reg_ser_r_stat_din___tr_idle___bit 22 234#define reg_ser_r_stat_din___tr_empty___lsb 23 235#define reg_ser_r_stat_din___tr_empty___width 1 236#define reg_ser_r_stat_din___tr_empty___bit 23 237#define reg_ser_r_stat_din___tr_rdy___lsb 24 238#define reg_ser_r_stat_din___tr_rdy___width 1 239#define reg_ser_r_stat_din___tr_rdy___bit 24 240#define reg_ser_r_stat_din___cts_n___lsb 25 241#define reg_ser_r_stat_din___cts_n___width 1 242#define reg_ser_r_stat_din___cts_n___bit 25 243#define reg_ser_r_stat_din___xoff_detect___lsb 26 244#define reg_ser_r_stat_din___xoff_detect___width 1 245#define reg_ser_r_stat_din___xoff_detect___bit 26 246#define reg_ser_r_stat_din___rts_n___lsb 27 247#define reg_ser_r_stat_din___rts_n___width 1 248#define reg_ser_r_stat_din___rts_n___bit 27 249#define reg_ser_r_stat_din___txd___lsb 28 250#define reg_ser_r_stat_din___txd___width 1 251#define reg_ser_r_stat_din___txd___bit 28 252#define reg_ser_r_stat_din_offset 36 253 254/* Register rw_rec_eop, scope ser, type rw */ 255#define reg_ser_rw_rec_eop___set___lsb 0 256#define reg_ser_rw_rec_eop___set___width 1 257#define reg_ser_rw_rec_eop___set___bit 0 258#define reg_ser_rw_rec_eop_offset 40 259 260/* Register rw_intr_mask, scope ser, type rw */ 261#define reg_ser_rw_intr_mask___tr_rdy___lsb 0 262#define reg_ser_rw_intr_mask___tr_rdy___width 1 263#define reg_ser_rw_intr_mask___tr_rdy___bit 0 264#define reg_ser_rw_intr_mask___tr_empty___lsb 1 265#define reg_ser_rw_intr_mask___tr_empty___width 1 266#define reg_ser_rw_intr_mask___tr_empty___bit 1 267#define reg_ser_rw_intr_mask___tr_idle___lsb 2 268#define reg_ser_rw_intr_mask___tr_idle___width 1 269#define reg_ser_rw_intr_mask___tr_idle___bit 2 270#define reg_ser_rw_intr_mask___dav___lsb 3 271#define reg_ser_rw_intr_mask___dav___width 1 272#define reg_ser_rw_intr_mask___dav___bit 3 273#define reg_ser_rw_intr_mask_offset 44 274 275/* Register rw_ack_intr, scope ser, type rw */ 276#define reg_ser_rw_ack_intr___tr_rdy___lsb 0 277#define reg_ser_rw_ack_intr___tr_rdy___width 1 278#define reg_ser_rw_ack_intr___tr_rdy___bit 0 279#define reg_ser_rw_ack_intr___tr_empty___lsb 1 280#define reg_ser_rw_ack_intr___tr_empty___width 1 281#define reg_ser_rw_ack_intr___tr_empty___bit 1 282#define reg_ser_rw_ack_intr___tr_idle___lsb 2 283#define reg_ser_rw_ack_intr___tr_idle___width 1 284#define reg_ser_rw_ack_intr___tr_idle___bit 2 285#define reg_ser_rw_ack_intr___dav___lsb 3 286#define reg_ser_rw_ack_intr___dav___width 1 287#define reg_ser_rw_ack_intr___dav___bit 3 288#define reg_ser_rw_ack_intr_offset 48 289 290/* Register r_intr, scope ser, type r */ 291#define reg_ser_r_intr___tr_rdy___lsb 0 292#define reg_ser_r_intr___tr_rdy___width 1 293#define reg_ser_r_intr___tr_rdy___bit 0 294#define reg_ser_r_intr___tr_empty___lsb 1 295#define reg_ser_r_intr___tr_empty___width 1 296#define reg_ser_r_intr___tr_empty___bit 1 297#define reg_ser_r_intr___tr_idle___lsb 2 298#define reg_ser_r_intr___tr_idle___width 1 299#define reg_ser_r_intr___tr_idle___bit 2 300#define reg_ser_r_intr___dav___lsb 3 301#define reg_ser_r_intr___dav___width 1 302#define reg_ser_r_intr___dav___bit 3 303#define reg_ser_r_intr_offset 52 304 305/* Register r_masked_intr, scope ser, type r */ 306#define reg_ser_r_masked_intr___tr_rdy___lsb 0 307#define reg_ser_r_masked_intr___tr_rdy___width 1 308#define reg_ser_r_masked_intr___tr_rdy___bit 0 309#define reg_ser_r_masked_intr___tr_empty___lsb 1 310#define reg_ser_r_masked_intr___tr_empty___width 1 311#define reg_ser_r_masked_intr___tr_empty___bit 1 312#define reg_ser_r_masked_intr___tr_idle___lsb 2 313#define reg_ser_r_masked_intr___tr_idle___width 1 314#define reg_ser_r_masked_intr___tr_idle___bit 2 315#define reg_ser_r_masked_intr___dav___lsb 3 316#define reg_ser_r_masked_intr___dav___width 1 317#define reg_ser_r_masked_intr___dav___bit 3 318#define reg_ser_r_masked_intr_offset 56 319 320 321/* Constants */ 322#define regk_ser_active 0x00000000 323#define regk_ser_bits1 0x00000000 324#define regk_ser_bits2 0x00000001 325#define regk_ser_bits7 0x00000001 326#define regk_ser_bits8 0x00000000 327#define regk_ser_del0_5 0x00000000 328#define regk_ser_del1 0x00000001 329#define regk_ser_del1_5 0x00000002 330#define regk_ser_del2 0x00000003 331#define regk_ser_del2_5 0x00000004 332#define regk_ser_del3 0x00000005 333#define regk_ser_del3_5 0x00000006 334#define regk_ser_del4 0x00000007 335#define regk_ser_even 0x00000000 336#define regk_ser_ext 0x00000001 337#define regk_ser_f100 0x00000007 338#define regk_ser_f29_493 0x00000004 339#define regk_ser_f32 0x00000005 340#define regk_ser_f32_768 0x00000006 341#define regk_ser_ignore 0x00000001 342#define regk_ser_inactive 0x00000001 343#define regk_ser_majority 0x00000001 344#define regk_ser_mark 0x00000002 345#define regk_ser_middle 0x00000000 346#define regk_ser_no 0x00000000 347#define regk_ser_odd 0x00000001 348#define regk_ser_off 0x00000000 349#define regk_ser_rw_intr_mask_default 0x00000000 350#define regk_ser_rw_rec_baud_div_default 0x00000000 351#define regk_ser_rw_rec_ctrl_default 0x00010000 352#define regk_ser_rw_tr_baud_div_default 0x00000000 353#define regk_ser_rw_tr_ctrl_default 0x00008000 354#define regk_ser_rw_tr_dma_en_default 0x00000000 355#define regk_ser_rw_xoff_default 0x00000000 356#define regk_ser_space 0x00000003 357#define regk_ser_stop 0x00000000 358#define regk_ser_yes 0x00000001 359#endif /* __ser_defs_asm_h */ 360