1#ifndef __bif_core_defs_asm_h 2#define __bif_core_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: ../../inst/bif/rtl/bif_core_regs.r 7 * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp 8 * last modfied: Mon Apr 11 16:06:33 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r 11 * id: $Id: bif_core_defs_asm.h,v 1.1.1.1 2007/08/03 18:53:23 Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17#ifndef REG_FIELD 18#define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20#define REG_FIELD_X_( value, shift ) ((value) << shift) 21#endif 22 23#ifndef REG_STATE 24#define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26#define REG_STATE_X_( k, shift ) (k << shift) 27#endif 28 29#ifndef REG_MASK 30#define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33#endif 34 35#ifndef REG_LSB 36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37#endif 38 39#ifndef REG_BIT 40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41#endif 42 43#ifndef REG_ADDR 44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46#endif 47 48#ifndef REG_ADDR_VECT 49#define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54#endif 55 56/* Register rw_grp1_cfg, scope bif_core, type rw */ 57#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 58#define reg_bif_core_rw_grp1_cfg___lw___width 6 59#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 60#define reg_bif_core_rw_grp1_cfg___ew___width 3 61#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 62#define reg_bif_core_rw_grp1_cfg___zw___width 3 63#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 64#define reg_bif_core_rw_grp1_cfg___aw___width 2 65#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 66#define reg_bif_core_rw_grp1_cfg___dw___width 2 67#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 68#define reg_bif_core_rw_grp1_cfg___ewb___width 2 69#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 70#define reg_bif_core_rw_grp1_cfg___bw___width 1 71#define reg_bif_core_rw_grp1_cfg___bw___bit 18 72#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 73#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 74#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 75#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 76#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 77#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 78#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 79#define reg_bif_core_rw_grp1_cfg___mode___width 1 80#define reg_bif_core_rw_grp1_cfg___mode___bit 21 81#define reg_bif_core_rw_grp1_cfg_offset 0 82 83/* Register rw_grp2_cfg, scope bif_core, type rw */ 84#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 85#define reg_bif_core_rw_grp2_cfg___lw___width 6 86#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 87#define reg_bif_core_rw_grp2_cfg___ew___width 3 88#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 89#define reg_bif_core_rw_grp2_cfg___zw___width 3 90#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 91#define reg_bif_core_rw_grp2_cfg___aw___width 2 92#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 93#define reg_bif_core_rw_grp2_cfg___dw___width 2 94#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 95#define reg_bif_core_rw_grp2_cfg___ewb___width 2 96#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 97#define reg_bif_core_rw_grp2_cfg___bw___width 1 98#define reg_bif_core_rw_grp2_cfg___bw___bit 18 99#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 100#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 101#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 102#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 103#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 104#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 105#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 106#define reg_bif_core_rw_grp2_cfg___mode___width 1 107#define reg_bif_core_rw_grp2_cfg___mode___bit 21 108#define reg_bif_core_rw_grp2_cfg_offset 4 109 110/* Register rw_grp3_cfg, scope bif_core, type rw */ 111#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 112#define reg_bif_core_rw_grp3_cfg___lw___width 6 113#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 114#define reg_bif_core_rw_grp3_cfg___ew___width 3 115#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 116#define reg_bif_core_rw_grp3_cfg___zw___width 3 117#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 118#define reg_bif_core_rw_grp3_cfg___aw___width 2 119#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 120#define reg_bif_core_rw_grp3_cfg___dw___width 2 121#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 122#define reg_bif_core_rw_grp3_cfg___ewb___width 2 123#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 124#define reg_bif_core_rw_grp3_cfg___bw___width 1 125#define reg_bif_core_rw_grp3_cfg___bw___bit 18 126#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 127#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 128#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 129#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 130#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 131#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 132#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 133#define reg_bif_core_rw_grp3_cfg___mode___width 1 134#define reg_bif_core_rw_grp3_cfg___mode___bit 21 135#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 136#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 137#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 138#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 139#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 140#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 141#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 142#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 143#define reg_bif_core_rw_grp3_cfg_offset 8 144 145/* Register rw_grp4_cfg, scope bif_core, type rw */ 146#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 147#define reg_bif_core_rw_grp4_cfg___lw___width 6 148#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 149#define reg_bif_core_rw_grp4_cfg___ew___width 3 150#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 151#define reg_bif_core_rw_grp4_cfg___zw___width 3 152#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 153#define reg_bif_core_rw_grp4_cfg___aw___width 2 154#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 155#define reg_bif_core_rw_grp4_cfg___dw___width 2 156#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 157#define reg_bif_core_rw_grp4_cfg___ewb___width 2 158#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 159#define reg_bif_core_rw_grp4_cfg___bw___width 1 160#define reg_bif_core_rw_grp4_cfg___bw___bit 18 161#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 162#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 163#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 164#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 165#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 166#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 167#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 168#define reg_bif_core_rw_grp4_cfg___mode___width 1 169#define reg_bif_core_rw_grp4_cfg___mode___bit 21 170#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 171#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 172#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 173#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 174#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 175#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 176#define reg_bif_core_rw_grp4_cfg_offset 12 177 178/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ 179#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 180#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 181#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 182#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 183#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 184#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 185#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 186#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 187#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 188#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 189#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 190#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 191#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 192#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 193#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 194#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 195#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 196#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 197#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 198#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 199#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 200 201/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ 202#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 203#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 204#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 205#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 206#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 207#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 208#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 209#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 210#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 211#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 212#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 213#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 214#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 215#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 216#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 217#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 218#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 219#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 220#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 221 222/* Register rw_sdram_timing, scope bif_core, type rw */ 223#define reg_bif_core_rw_sdram_timing___cl___lsb 0 224#define reg_bif_core_rw_sdram_timing___cl___width 3 225#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 226#define reg_bif_core_rw_sdram_timing___rcd___width 3 227#define reg_bif_core_rw_sdram_timing___rp___lsb 6 228#define reg_bif_core_rw_sdram_timing___rp___width 3 229#define reg_bif_core_rw_sdram_timing___rc___lsb 9 230#define reg_bif_core_rw_sdram_timing___rc___width 2 231#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 232#define reg_bif_core_rw_sdram_timing___dpl___width 2 233#define reg_bif_core_rw_sdram_timing___pde___lsb 13 234#define reg_bif_core_rw_sdram_timing___pde___width 1 235#define reg_bif_core_rw_sdram_timing___pde___bit 13 236#define reg_bif_core_rw_sdram_timing___ref___lsb 14 237#define reg_bif_core_rw_sdram_timing___ref___width 2 238#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 239#define reg_bif_core_rw_sdram_timing___cpd___width 1 240#define reg_bif_core_rw_sdram_timing___cpd___bit 16 241#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 242#define reg_bif_core_rw_sdram_timing___sdcke___width 1 243#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 244#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 245#define reg_bif_core_rw_sdram_timing___sdclk___width 1 246#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 247#define reg_bif_core_rw_sdram_timing_offset 24 248 249/* Register rw_sdram_cmd, scope bif_core, type rw */ 250#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 251#define reg_bif_core_rw_sdram_cmd___cmd___width 3 252#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 253#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 254#define reg_bif_core_rw_sdram_cmd_offset 28 255 256/* Register rs_sdram_ref_stat, scope bif_core, type rs */ 257#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 258#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 259#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 260#define reg_bif_core_rs_sdram_ref_stat_offset 32 261 262/* Register r_sdram_ref_stat, scope bif_core, type r */ 263#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 264#define reg_bif_core_r_sdram_ref_stat___ok___width 1 265#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 266#define reg_bif_core_r_sdram_ref_stat_offset 36 267 268 269/* Constants */ 270#define regk_bif_core_bank2 0x00000000 271#define regk_bif_core_bank4 0x00000001 272#define regk_bif_core_bit10 0x0000000a 273#define regk_bif_core_bit11 0x0000000b 274#define regk_bif_core_bit12 0x0000000c 275#define regk_bif_core_bit13 0x0000000d 276#define regk_bif_core_bit14 0x0000000e 277#define regk_bif_core_bit15 0x0000000f 278#define regk_bif_core_bit16 0x00000010 279#define regk_bif_core_bit17 0x00000011 280#define regk_bif_core_bit18 0x00000012 281#define regk_bif_core_bit19 0x00000013 282#define regk_bif_core_bit20 0x00000014 283#define regk_bif_core_bit21 0x00000015 284#define regk_bif_core_bit22 0x00000016 285#define regk_bif_core_bit23 0x00000017 286#define regk_bif_core_bit24 0x00000018 287#define regk_bif_core_bit25 0x00000019 288#define regk_bif_core_bit26 0x0000001a 289#define regk_bif_core_bit27 0x0000001b 290#define regk_bif_core_bit28 0x0000001c 291#define regk_bif_core_bit29 0x0000001d 292#define regk_bif_core_bit9 0x00000009 293#define regk_bif_core_bw16 0x00000001 294#define regk_bif_core_bw32 0x00000000 295#define regk_bif_core_bwe 0x00000000 296#define regk_bif_core_cwe 0x00000001 297#define regk_bif_core_e15us 0x00000001 298#define regk_bif_core_e7800ns 0x00000002 299#define regk_bif_core_grp0 0x00000000 300#define regk_bif_core_grp1 0x00000001 301#define regk_bif_core_mrs 0x00000003 302#define regk_bif_core_no 0x00000000 303#define regk_bif_core_none 0x00000000 304#define regk_bif_core_nop 0x00000000 305#define regk_bif_core_off 0x00000000 306#define regk_bif_core_pre 0x00000002 307#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 308#define regk_bif_core_rd 0x00000002 309#define regk_bif_core_ref 0x00000001 310#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 311#define regk_bif_core_rw_grp1_cfg_default 0x000006cf 312#define regk_bif_core_rw_grp2_cfg_default 0x000006cf 313#define regk_bif_core_rw_grp3_cfg_default 0x000006cf 314#define regk_bif_core_rw_grp4_cfg_default 0x000006cf 315#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 316#define regk_bif_core_slf 0x00000004 317#define regk_bif_core_wr 0x00000001 318#define regk_bif_core_yes 0x00000001 319#endif /* __bif_core_defs_asm_h */ 320