1/* 2 * linux/include/asm-arm/arch-versatile/platform.h 3 * 4 * Copyright (c) ARM Limited 2003. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 21#ifndef __address_h 22#define __address_h 1 23 24/* 25 * Memory definitions 26 */ 27#define VERSATILE_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/ 28#define VERSATILE_BOOT_ROM_HI 0x30000000 29#define VERSATILE_BOOT_ROM_BASE VERSATILE_BOOT_ROM_HI /* Normal position */ 30#define VERSATILE_BOOT_ROM_SIZE SZ_64M 31 32#define VERSATILE_SSRAM_BASE /* VERSATILE_SSMC_BASE ? */ 33#define VERSATILE_SSRAM_SIZE SZ_2M 34 35#define VERSATILE_FLASH_BASE 0x34000000 36#define VERSATILE_FLASH_SIZE SZ_64M 37 38/* 39 * SDRAM 40 */ 41#define VERSATILE_SDRAM_BASE 0x00000000 42 43/* 44 * Logic expansion modules 45 * 46 */ 47 48 49/* ------------------------------------------------------------------------ 50 * Versatile Registers 51 * ------------------------------------------------------------------------ 52 * 53 */ 54#define VERSATILE_SYS_ID_OFFSET 0x00 55#define VERSATILE_SYS_SW_OFFSET 0x04 56#define VERSATILE_SYS_LED_OFFSET 0x08 57#define VERSATILE_SYS_OSC0_OFFSET 0x0C 58 59#if defined(CONFIG_ARCH_VERSATILE_PB) 60#define VERSATILE_SYS_OSC1_OFFSET 0x10 61#define VERSATILE_SYS_OSC2_OFFSET 0x14 62#define VERSATILE_SYS_OSC3_OFFSET 0x18 63#define VERSATILE_SYS_OSC4_OFFSET 0x1C 64#elif defined(CONFIG_MACH_VERSATILE_AB) 65#define VERSATILE_SYS_OSC1_OFFSET 0x1C 66#endif 67 68#define VERSATILE_SYS_OSCCLCD_OFFSET 0x1c 69 70#define VERSATILE_SYS_LOCK_OFFSET 0x20 71#define VERSATILE_SYS_100HZ_OFFSET 0x24 72#define VERSATILE_SYS_CFGDATA1_OFFSET 0x28 73#define VERSATILE_SYS_CFGDATA2_OFFSET 0x2C 74#define VERSATILE_SYS_FLAGS_OFFSET 0x30 75#define VERSATILE_SYS_FLAGSSET_OFFSET 0x30 76#define VERSATILE_SYS_FLAGSCLR_OFFSET 0x34 77#define VERSATILE_SYS_NVFLAGS_OFFSET 0x38 78#define VERSATILE_SYS_NVFLAGSSET_OFFSET 0x38 79#define VERSATILE_SYS_NVFLAGSCLR_OFFSET 0x3C 80#define VERSATILE_SYS_RESETCTL_OFFSET 0x40 81#define VERSATILE_SYS_PCICTL_OFFSET 0x44 82#define VERSATILE_SYS_MCI_OFFSET 0x48 83#define VERSATILE_SYS_FLASH_OFFSET 0x4C 84#define VERSATILE_SYS_CLCD_OFFSET 0x50 85#define VERSATILE_SYS_CLCDSER_OFFSET 0x54 86#define VERSATILE_SYS_BOOTCS_OFFSET 0x58 87#define VERSATILE_SYS_24MHz_OFFSET 0x5C 88#define VERSATILE_SYS_MISC_OFFSET 0x60 89#define VERSATILE_SYS_TEST_OSC0_OFFSET 0x80 90#define VERSATILE_SYS_TEST_OSC1_OFFSET 0x84 91#define VERSATILE_SYS_TEST_OSC2_OFFSET 0x88 92#define VERSATILE_SYS_TEST_OSC3_OFFSET 0x8C 93#define VERSATILE_SYS_TEST_OSC4_OFFSET 0x90 94 95#define VERSATILE_SYS_BASE 0x10000000 96#define VERSATILE_SYS_ID (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET) 97#define VERSATILE_SYS_SW (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET) 98#define VERSATILE_SYS_LED (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET) 99#define VERSATILE_SYS_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET) 100#define VERSATILE_SYS_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET) 101 102#if defined(CONFIG_ARCH_VERSATILE_PB) 103#define VERSATILE_SYS_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET) 104#define VERSATILE_SYS_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET) 105#define VERSATILE_SYS_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET) 106#endif 107 108#define VERSATILE_SYS_LOCK (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET) 109#define VERSATILE_SYS_100HZ (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET) 110#define VERSATILE_SYS_CFGDATA1 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET) 111#define VERSATILE_SYS_CFGDATA2 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET) 112#define VERSATILE_SYS_FLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET) 113#define VERSATILE_SYS_FLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET) 114#define VERSATILE_SYS_FLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET) 115#define VERSATILE_SYS_NVFLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET) 116#define VERSATILE_SYS_NVFLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET) 117#define VERSATILE_SYS_NVFLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET) 118#define VERSATILE_SYS_RESETCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET) 119#define VERSATILE_SYS_PCICTL (VERSATILE_SYS_BASE + VERSATILE_SYS_PCICTL_OFFSET) 120#define VERSATILE_SYS_MCI (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET) 121#define VERSATILE_SYS_FLASH (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET) 122#define VERSATILE_SYS_CLCD (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET) 123#define VERSATILE_SYS_CLCDSER (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET) 124#define VERSATILE_SYS_BOOTCS (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET) 125#define VERSATILE_SYS_24MHz (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET) 126#define VERSATILE_SYS_MISC (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET) 127#define VERSATILE_SYS_TEST_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET) 128#define VERSATILE_SYS_TEST_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET) 129#define VERSATILE_SYS_TEST_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET) 130#define VERSATILE_SYS_TEST_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET) 131#define VERSATILE_SYS_TEST_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET) 132 133/* 134 * Values for VERSATILE_SYS_RESET_CTRL 135 */ 136#define VERSATILE_SYS_CTRL_RESET_CONFIGCLR 0x01 137#define VERSATILE_SYS_CTRL_RESET_CONFIGINIT 0x02 138#define VERSATILE_SYS_CTRL_RESET_DLLRESET 0x03 139#define VERSATILE_SYS_CTRL_RESET_PLLRESET 0x04 140#define VERSATILE_SYS_CTRL_RESET_POR 0x05 141#define VERSATILE_SYS_CTRL_RESET_DoC 0x06 142 143#define VERSATILE_SYS_CTRL_LED (1 << 0) 144 145 146/* ------------------------------------------------------------------------ 147 * Versatile control registers 148 * ------------------------------------------------------------------------ 149 */ 150 151/* 152 * VERSATILE_IDFIELD 153 * 154 * 31:24 = manufacturer (0x41 = ARM) 155 * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus) 156 * 15:12 = FPGA (0x3 = XVC600 or XVC600E) 157 * 11:4 = build value 158 * 3:0 = revision number (0x1 = rev B (AHB)) 159 */ 160 161/* 162 * VERSATILE_SYS_LOCK 163 * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, 164 * SYS_CLD, SYS_BOOTCS 165 */ 166#define VERSATILE_SYS_LOCK_LOCKED (1 << 16) 167#define VERSATILE_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */ 168 169/* 170 * VERSATILE_SYS_FLASH 171 */ 172#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ 173 174/* 175 * VERSATILE_INTREG 176 * - used to acknowledge and control MMCI and UART interrupts 177 */ 178#define VERSATILE_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */ 179#define VERSATILE_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */ 180#define VERSATILE_INTREG_CARDIN 0x08 /* MMCI card in detect */ 181 /* write 1 to acknowledge and clear */ 182#define VERSATILE_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */ 183#define VERSATILE_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ 184 185/* 186 * VERSATILE peripheral addresses 187 */ 188#define VERSATILE_PCI_CORE_BASE 0x10001000 /* PCI core control */ 189#define VERSATILE_I2C_BASE 0x10002000 /* I2C control */ 190#define VERSATILE_SIC_BASE 0x10003000 /* Secondary interrupt controller */ 191#define VERSATILE_AACI_BASE 0x10004000 /* Audio */ 192#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */ 193#define VERSATILE_KMI0_BASE 0x10006000 /* KMI interface */ 194#define VERSATILE_KMI1_BASE 0x10007000 /* KMI 2nd interface */ 195#define VERSATILE_CHAR_LCD_BASE 0x10008000 /* Character LCD */ 196#define VERSATILE_UART3_BASE 0x10009000 /* UART 3 */ 197#define VERSATILE_SCI1_BASE 0x1000A000 198#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */ 199 /* 0x1000C000 - 0x1000CFFF = reserved */ 200#define VERSATILE_ETH_BASE 0x10010000 /* Ethernet */ 201#define VERSATILE_USB_BASE 0x10020000 /* USB */ 202 /* 0x10030000 - 0x100FFFFF = reserved */ 203#define VERSATILE_SMC_BASE 0x10100000 /* SMC */ 204#define VERSATILE_MPMC_BASE 0x10110000 /* MPMC */ 205#define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */ 206#define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */ 207#define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */ 208#define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */ 209 /* 0x10000000 - 0x100FFFFF */ 210#define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */ 211#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ 212#define VERSATILE_WATCHDOG_BASE 0x101E1000 /* Watchdog */ 213#define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */ 214#define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */ 215#define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */ 216#define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */ 217#define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */ 218#define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */ 219#define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */ 220 /* 0x101E9000 - reserved */ 221#define VERSATILE_SCI_BASE 0x101F0000 /* Smart card controller */ 222#define VERSATILE_UART0_BASE 0x101F1000 /* Uart 0 */ 223#define VERSATILE_UART1_BASE 0x101F2000 /* Uart 1 */ 224#define VERSATILE_UART2_BASE 0x101F3000 /* Uart 2 */ 225#define VERSATILE_SSP_BASE 0x101F4000 /* Synchronous Serial Port */ 226 227#define VERSATILE_SSMC_BASE 0x20000000 /* SSMC */ 228#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */ 229#define VERSATILE_MBX_BASE 0x40000000 /* MBX */ 230 231/* PCI space */ 232#define VERSATILE_PCI_BASE 0x41000000 /* PCI Interface */ 233#define VERSATILE_PCI_CFG_BASE 0x42000000 234#define VERSATILE_PCI_MEM_BASE0 0x44000000 235#define VERSATILE_PCI_MEM_BASE1 0x50000000 236#define VERSATILE_PCI_MEM_BASE2 0x60000000 237/* Sizes of above maps */ 238#define VERSATILE_PCI_BASE_SIZE 0x01000000 239#define VERSATILE_PCI_CFG_BASE_SIZE 0x02000000 240#define VERSATILE_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */ 241#define VERSATILE_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */ 242#define VERSATILE_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */ 243 244#define VERSATILE_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */ 245#define VERSATILE_LT_BASE 0x80000000 /* Logic Tile expansion */ 246 247/* 248 * Disk on Chip 249 */ 250#define VERSATILE_DOC_BASE 0x2C000000 251#define VERSATILE_DOC_SIZE (16 << 20) 252#define VERSATILE_DOC_PAGE_SIZE 512 253#define VERSATILE_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE) 254 255#define ERASE_UNIT_PAGES 32 256#define START_PAGE 0x80 257 258/* 259 * LED settings, bits [7:0] 260 */ 261#define VERSATILE_SYS_LED0 (1 << 0) 262#define VERSATILE_SYS_LED1 (1 << 1) 263#define VERSATILE_SYS_LED2 (1 << 2) 264#define VERSATILE_SYS_LED3 (1 << 3) 265#define VERSATILE_SYS_LED4 (1 << 4) 266#define VERSATILE_SYS_LED5 (1 << 5) 267#define VERSATILE_SYS_LED6 (1 << 6) 268#define VERSATILE_SYS_LED7 (1 << 7) 269 270#define ALL_LEDS 0xFF 271 272#define LED_BANK VERSATILE_SYS_LED 273 274/* 275 * Control registers 276 */ 277#define VERSATILE_IDFIELD_OFFSET 0x0 /* Versatile build information */ 278#define VERSATILE_FLASHPROG_OFFSET 0x4 /* Flash devices */ 279#define VERSATILE_INTREG_OFFSET 0x8 /* Interrupt control */ 280#define VERSATILE_DECODE_OFFSET 0xC /* Fitted logic modules */ 281 282 283/* ------------------------------------------------------------------------ 284 * Versatile Interrupt Controller - control registers 285 * ------------------------------------------------------------------------ 286 * 287 * Offsets from interrupt controller base 288 * 289 * System Controller interrupt controller base is 290 * 291 * VERSATILE_IC_BASE 292 * 293 * Core Module interrupt controller base is 294 * 295 * VERSATILE_SYS_IC 296 * 297 */ 298/* VIC definitions in include/asm-arm/hardware/vic.h */ 299 300#define SIC_IRQ_STATUS 0 301#define SIC_IRQ_RAW_STATUS 0x04 302#define SIC_IRQ_ENABLE 0x08 303#define SIC_IRQ_ENABLE_SET 0x08 304#define SIC_IRQ_ENABLE_CLEAR 0x0C 305#define SIC_INT_SOFT_SET 0x10 306#define SIC_INT_SOFT_CLEAR 0x14 307#define SIC_INT_PIC_ENABLE 0x20 /* read status of pass through mask */ 308#define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */ 309#define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */ 310 311/* ------------------------------------------------------------------------ 312 * Interrupts - bit assignment (primary) 313 * ------------------------------------------------------------------------ 314 */ 315 316#define INT_WDOGINT 0 /* Watchdog timer */ 317#define INT_SOFTINT 1 /* Software interrupt */ 318#define INT_COMMRx 2 /* Debug Comm Rx interrupt */ 319#define INT_COMMTx 3 /* Debug Comm Tx interrupt */ 320#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */ 321#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */ 322#define INT_GPIOINT0 6 /* GPIO 0 */ 323#define INT_GPIOINT1 7 /* GPIO 1 */ 324#define INT_GPIOINT2 8 /* GPIO 2 */ 325#define INT_GPIOINT3 9 /* GPIO 3 */ 326#define INT_RTCINT 10 /* Real Time Clock */ 327#define INT_SSPINT 11 /* Synchronous Serial Port */ 328#define INT_UARTINT0 12 /* UART 0 on development chip */ 329#define INT_UARTINT1 13 /* UART 1 on development chip */ 330#define INT_UARTINT2 14 /* UART 2 on development chip */ 331#define INT_SCIINT 15 /* Smart Card Interface */ 332#define INT_CLCDINT 16 /* CLCD controller */ 333#define INT_DMAINT 17 /* DMA controller */ 334#define INT_PWRFAILINT 18 /* Power failure */ 335#define INT_MBXINT 19 /* Graphics processor */ 336#define INT_GNDINT 20 /* Reserved */ 337 /* External interrupt signals from logic tiles or secondary controller */ 338#define INT_VICSOURCE21 21 /* Disk on Chip */ 339#define INT_VICSOURCE22 22 /* MCI0A */ 340#define INT_VICSOURCE23 23 /* MCI1A */ 341#define INT_VICSOURCE24 24 /* AACI */ 342#define INT_VICSOURCE25 25 /* Ethernet */ 343#define INT_VICSOURCE26 26 /* USB */ 344#define INT_VICSOURCE27 27 /* PCI 0 */ 345#define INT_VICSOURCE28 28 /* PCI 1 */ 346#define INT_VICSOURCE29 29 /* PCI 2 */ 347#define INT_VICSOURCE30 30 /* PCI 3 */ 348#define INT_VICSOURCE31 31 /* SIC source */ 349 350/* 351 * Interrupt bit positions 352 * 353 */ 354#define INTMASK_WDOGINT (1 << INT_WDOGINT) 355#define INTMASK_SOFTINT (1 << INT_SOFTINT) 356#define INTMASK_COMMRx (1 << INT_COMMRx) 357#define INTMASK_COMMTx (1 << INT_COMMTx) 358#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1) 359#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3) 360#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0) 361#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1) 362#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2) 363#define INTMASK_GPIOINT3 (1 << INT_GPIOINT3) 364#define INTMASK_RTCINT (1 << INT_RTCINT) 365#define INTMASK_SSPINT (1 << INT_SSPINT) 366#define INTMASK_UARTINT0 (1 << INT_UARTINT0) 367#define INTMASK_UARTINT1 (1 << INT_UARTINT1) 368#define INTMASK_UARTINT2 (1 << INT_UARTINT2) 369#define INTMASK_SCIINT (1 << INT_SCIINT) 370#define INTMASK_CLCDINT (1 << INT_CLCDINT) 371#define INTMASK_DMAINT (1 << INT_DMAINT) 372#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT) 373#define INTMASK_MBXINT (1 << INT_MBXINT) 374#define INTMASK_GNDINT (1 << INT_GNDINT) 375#define INTMASK_VICSOURCE21 (1 << INT_VICSOURCE21) 376#define INTMASK_VICSOURCE22 (1 << INT_VICSOURCE22) 377#define INTMASK_VICSOURCE23 (1 << INT_VICSOURCE23) 378#define INTMASK_VICSOURCE24 (1 << INT_VICSOURCE24) 379#define INTMASK_VICSOURCE25 (1 << INT_VICSOURCE25) 380#define INTMASK_VICSOURCE26 (1 << INT_VICSOURCE26) 381#define INTMASK_VICSOURCE27 (1 << INT_VICSOURCE27) 382#define INTMASK_VICSOURCE28 (1 << INT_VICSOURCE28) 383#define INTMASK_VICSOURCE29 (1 << INT_VICSOURCE29) 384#define INTMASK_VICSOURCE30 (1 << INT_VICSOURCE30) 385#define INTMASK_VICSOURCE31 (1 << INT_VICSOURCE31) 386 387 388#define VERSATILE_SC_VALID_INT 0x003FFFFF 389 390#define MAXIRQNUM 31 391#define MAXFIQNUM 31 392#define MAXSWINUM 31 393 394/* ------------------------------------------------------------------------ 395 * Interrupts - bit assignment (secondary) 396 * ------------------------------------------------------------------------ 397 */ 398#define SIC_INT_MMCI0B 1 /* Multimedia Card 0B */ 399#define SIC_INT_MMCI1B 2 /* Multimedia Card 1B */ 400#define SIC_INT_KMI0 3 /* Keyboard/Mouse port 0 */ 401#define SIC_INT_KMI1 4 /* Keyboard/Mouse port 1 */ 402#define SIC_INT_SCI3 5 /* Smart Card interface */ 403#define SIC_INT_UART3 6 /* UART 3 empty or data available */ 404#define SIC_INT_CLCD 7 /* Character LCD */ 405#define SIC_INT_TOUCH 8 /* Touchscreen */ 406#define SIC_INT_KEYPAD 9 /* Key pressed on display keypad */ 407 /* 10:20 - reserved */ 408#define SIC_INT_DoC 21 /* Disk on Chip memory controller */ 409#define SIC_INT_MMCI0A 22 /* MMC 0A */ 410#define SIC_INT_MMCI1A 23 /* MMC 1A */ 411#define SIC_INT_AACI 24 /* Audio Codec */ 412#define SIC_INT_ETH 25 /* Ethernet controller */ 413#define SIC_INT_USB 26 /* USB controller */ 414#define SIC_INT_PCI0 27 415#define SIC_INT_PCI1 28 416#define SIC_INT_PCI2 29 417#define SIC_INT_PCI3 30 418 419 420#define SIC_INTMASK_MMCI0B (1 << SIC_INT_MMCI0B) 421#define SIC_INTMASK_MMCI1B (1 << SIC_INT_MMCI1B) 422#define SIC_INTMASK_KMI0 (1 << SIC_INT_KMI0) 423#define SIC_INTMASK_KMI1 (1 << SIC_INT_KMI1) 424#define SIC_INTMASK_SCI3 (1 << SIC_INT_SCI3) 425#define SIC_INTMASK_UART3 (1 << SIC_INT_UART3) 426#define SIC_INTMASK_CLCD (1 << SIC_INT_CLCD) 427#define SIC_INTMASK_TOUCH (1 << SIC_INT_TOUCH) 428#define SIC_INTMASK_KEYPAD (1 << SIC_INT_KEYPAD) 429#define SIC_INTMASK_DoC (1 << SIC_INT_DoC) 430#define SIC_INTMASK_MMCI0A (1 << SIC_INT_MMCI0A) 431#define SIC_INTMASK_MMCI1A (1 << SIC_INT_MMCI1A) 432#define SIC_INTMASK_AACI (1 << SIC_INT_AACI) 433#define SIC_INTMASK_ETH (1 << SIC_INT_ETH) 434#define SIC_INTMASK_USB (1 << SIC_INT_USB) 435#define SIC_INTMASK_PCI0 (1 << SIC_INT_PCI0) 436#define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1) 437#define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2) 438#define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3) 439/* 440 * Application Flash 441 * 442 */ 443#define FLASH_BASE VERSATILE_FLASH_BASE 444#define FLASH_SIZE VERSATILE_FLASH_SIZE 445#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) 446#define FLASH_BLOCK_SIZE SZ_128K 447 448/* 449 * Boot Flash 450 * 451 */ 452#define EPROM_BASE VERSATILE_BOOT_ROM_HI 453#define EPROM_SIZE VERSATILE_BOOT_ROM_SIZE 454#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) 455 456/* 457 * Clean base - dummy 458 * 459 */ 460#define CLEAN_BASE EPROM_BASE 461 462/* 463 * System controller bit assignment 464 */ 465#define VERSATILE_REFCLK 0 466#define VERSATILE_TIMCLK 1 467 468#define VERSATILE_TIMER1_EnSel 15 469#define VERSATILE_TIMER2_EnSel 17 470#define VERSATILE_TIMER3_EnSel 19 471#define VERSATILE_TIMER4_EnSel 21 472 473 474#define MAX_TIMER 2 475#define MAX_PERIOD 699050 476#define TICKS_PER_uSEC 1 477 478/* 479 * These are useconds NOT ticks. 480 * 481 */ 482#define mSEC_1 1000 483#define mSEC_5 (mSEC_1 * 5) 484#define mSEC_10 (mSEC_1 * 10) 485#define mSEC_25 (mSEC_1 * 25) 486#define SEC_1 (mSEC_1 * 1000) 487 488#define VERSATILE_CSR_BASE 0x10000000 489#define VERSATILE_CSR_SIZE 0x10000000 490 491#ifdef CONFIG_MACH_VERSATILE_AB 492/* 493 * IB2 Versatile/AB expansion board definitions 494 */ 495#define VERSATILE_IB2_CAMERA_BANK VERSATILE_IB2_BASE 496#define VERSATILE_IB2_KBD_DATAREG (VERSATILE_IB2_BASE + 0x01000000) 497 498/* VICINTSOURCE27 */ 499#define VERSATILE_IB2_INT_BASE (VERSATILE_IB2_BASE + 0x02000000) 500#define VERSATILE_IB2_IER (VERSATILE_IB2_INT_BASE + 0) 501#define VERSATILE_IB2_ISR (VERSATILE_IB2_INT_BASE + 4) 502 503#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000) 504#define VERSATILE_IB2_CTRL (VERSATILE_IB2_CTL_BASE + 0) 505#define VERSATILE_IB2_STAT (VERSATILE_IB2_CTL_BASE + 4) 506#endif 507 508#endif 509 510/* END */ 511