1/* linux/include/asm-arm/arch-s3c2410/dma.h 2 * 3 * Copyright (C) 2003,2004,2006 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * Samsung S3C241XX DMA support 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11*/ 12 13#ifndef __ASM_ARCH_DMA_H 14#define __ASM_ARCH_DMA_H __FILE__ 15 16#include <linux/sysdev.h> 17#include <asm/hardware.h> 18 19/* 20 * This is the maximum DMA address(physical address) that can be DMAd to. 21 * 22 */ 23#define MAX_DMA_ADDRESS 0x40000000 24#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ 25 26/* We use `virtual` dma channels to hide the fact we have only a limited 27 * number of DMA channels, and not of all of them (dependant on the device) 28 * can be attached to any DMA source. We therefore let the DMA core handle 29 * the allocation of hardware channels to clients. 30*/ 31 32enum dma_ch { 33 DMACH_XD0, 34 DMACH_XD1, 35 DMACH_SDI, 36 DMACH_SPI0, 37 DMACH_SPI1, 38 DMACH_UART0, 39 DMACH_UART1, 40 DMACH_UART2, 41 DMACH_TIMER, 42 DMACH_I2S_IN, 43 DMACH_I2S_OUT, 44 DMACH_PCM_IN, 45 DMACH_PCM_OUT, 46 DMACH_MIC_IN, 47 DMACH_USB_EP1, 48 DMACH_USB_EP2, 49 DMACH_USB_EP3, 50 DMACH_USB_EP4, 51 DMACH_UART0_SRC2, /* s3c2412 second uart sources */ 52 DMACH_UART1_SRC2, 53 DMACH_UART2_SRC2, 54 DMACH_UART3, /* s3c2443 has extra uart */ 55 DMACH_UART3_SRC2, 56 DMACH_MAX, /* the end entry */ 57}; 58 59#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ 60 61/* we have 4 dma channels */ 62#ifndef CONFIG_CPU_S3C2443 63#define S3C2410_DMA_CHANNELS (4) 64#else 65#define S3C2410_DMA_CHANNELS (6) 66#endif 67 68/* types */ 69 70enum s3c2410_dma_state { 71 S3C2410_DMA_IDLE, 72 S3C2410_DMA_RUNNING, 73 S3C2410_DMA_PAUSED 74}; 75 76 77/* enum s3c2410_dma_loadst 78 * 79 * This represents the state of the DMA engine, wrt to the loaded / running 80 * transfers. Since we don't have any way of knowing exactly the state of 81 * the DMA transfers, we need to know the state to make decisions on wether 82 * we can 83 * 84 * S3C2410_DMA_NONE 85 * 86 * There are no buffers loaded (the channel should be inactive) 87 * 88 * S3C2410_DMA_1LOADED 89 * 90 * There is one buffer loaded, however it has not been confirmed to be 91 * loaded by the DMA engine. This may be because the channel is not 92 * yet running, or the DMA driver decided that it was too costly to 93 * sit and wait for it to happen. 94 * 95 * S3C2410_DMA_1RUNNING 96 * 97 * The buffer has been confirmed running, and not finisged 98 * 99 * S3C2410_DMA_1LOADED_1RUNNING 100 * 101 * There is a buffer waiting to be loaded by the DMA engine, and one 102 * currently running. 103*/ 104 105enum s3c2410_dma_loadst { 106 S3C2410_DMALOAD_NONE, 107 S3C2410_DMALOAD_1LOADED, 108 S3C2410_DMALOAD_1RUNNING, 109 S3C2410_DMALOAD_1LOADED_1RUNNING, 110}; 111 112enum s3c2410_dma_buffresult { 113 S3C2410_RES_OK, 114 S3C2410_RES_ERR, 115 S3C2410_RES_ABORT 116}; 117 118enum s3c2410_dmasrc { 119 S3C2410_DMASRC_HW, /* source is memory */ 120 S3C2410_DMASRC_MEM /* source is hardware */ 121}; 122 123/* enum s3c2410_chan_op 124 * 125 * operation codes passed to the DMA code by the user, and also used 126 * to inform the current channel owner of any changes to the system state 127*/ 128 129enum s3c2410_chan_op { 130 S3C2410_DMAOP_START, 131 S3C2410_DMAOP_STOP, 132 S3C2410_DMAOP_PAUSE, 133 S3C2410_DMAOP_RESUME, 134 S3C2410_DMAOP_FLUSH, 135 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ 136 S3C2410_DMAOP_STARTED, /* indicate channel started */ 137}; 138 139/* flags */ 140 141#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about 142 * waiting for reloads */ 143#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */ 144 145/* dma buffer */ 146 147struct s3c2410_dma_client { 148 char *name; 149}; 150 151/* s3c2410_dma_buf_s 152 * 153 * internally used buffer structure to describe a queued or running 154 * buffer. 155*/ 156 157struct s3c2410_dma_buf; 158struct s3c2410_dma_buf { 159 struct s3c2410_dma_buf *next; 160 int magic; /* magic */ 161 int size; /* buffer size in bytes */ 162 dma_addr_t data; /* start of DMA data */ 163 dma_addr_t ptr; /* where the DMA got to [1] */ 164 void *id; /* client's id */ 165}; 166 167/* [1] is this updated for both recv/send modes? */ 168 169struct s3c2410_dma_chan; 170 171/* s3c2410_dma_cbfn_t 172 * 173 * buffer callback routine type 174*/ 175 176typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *, 177 void *buf, int size, 178 enum s3c2410_dma_buffresult result); 179 180typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *, 181 enum s3c2410_chan_op ); 182 183struct s3c2410_dma_stats { 184 unsigned long loads; 185 unsigned long timeout_longest; 186 unsigned long timeout_shortest; 187 unsigned long timeout_avg; 188 unsigned long timeout_failed; 189}; 190 191struct s3c2410_dma_map; 192 193/* struct s3c2410_dma_chan 194 * 195 * full state information for each DMA channel 196*/ 197 198struct s3c2410_dma_chan { 199 /* channel state flags and information */ 200 unsigned char number; /* number of this dma channel */ 201 unsigned char in_use; /* channel allocated */ 202 unsigned char irq_claimed; /* irq claimed for channel */ 203 unsigned char irq_enabled; /* irq enabled for channel */ 204 unsigned char xfer_unit; /* size of an transfer */ 205 206 /* channel state */ 207 208 enum s3c2410_dma_state state; 209 enum s3c2410_dma_loadst load_state; 210 struct s3c2410_dma_client *client; 211 212 /* channel configuration */ 213 enum s3c2410_dmasrc source; 214 unsigned long dev_addr; 215 unsigned long load_timeout; 216 unsigned int flags; /* channel flags */ 217 218 struct s3c24xx_dma_map *map; /* channel hw maps */ 219 220 /* channel's hardware position and configuration */ 221 void __iomem *regs; /* channels registers */ 222 void __iomem *addr_reg; /* data address register */ 223 unsigned int irq; /* channel irq */ 224 unsigned long dcon; /* default value of DCON */ 225 226 /* driver handles */ 227 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ 228 s3c2410_dma_opfn_t op_fn; /* channel op callback */ 229 230 /* stats gathering */ 231 struct s3c2410_dma_stats *stats; 232 struct s3c2410_dma_stats stats_store; 233 234 /* buffer list and information */ 235 struct s3c2410_dma_buf *curr; /* current dma buffer */ 236 struct s3c2410_dma_buf *next; /* next buffer to load */ 237 struct s3c2410_dma_buf *end; /* end of queue */ 238 239 /* system device */ 240 struct sys_device dev; 241}; 242 243/* the currently allocated channel information */ 244extern struct s3c2410_dma_chan s3c2410_chans[]; 245 246/* note, we don't really use dma_device_t at the moment */ 247typedef unsigned long dma_device_t; 248 249/* functions --------------------------------------------------------------- */ 250 251/* s3c2410_dma_request 252 * 253 * request a dma channel exclusivley 254*/ 255 256extern int s3c2410_dma_request(dmach_t channel, 257 struct s3c2410_dma_client *, void *dev); 258 259 260/* s3c2410_dma_ctrl 261 * 262 * change the state of the dma channel 263*/ 264 265extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op); 266 267/* s3c2410_dma_setflags 268 * 269 * set the channel's flags to a given state 270*/ 271 272extern int s3c2410_dma_setflags(dmach_t channel, 273 unsigned int flags); 274 275/* s3c2410_dma_free 276 * 277 * free the dma channel (will also abort any outstanding operations) 278*/ 279 280extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *); 281 282/* s3c2410_dma_enqueue 283 * 284 * place the given buffer onto the queue of operations for the channel. 285 * The buffer must be allocated from dma coherent memory, or the Dcache/WB 286 * drained before the buffer is given to the DMA system. 287*/ 288 289extern int s3c2410_dma_enqueue(dmach_t channel, void *id, 290 dma_addr_t data, int size); 291 292/* s3c2410_dma_config 293 * 294 * configure the dma channel 295*/ 296 297extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon); 298 299/* s3c2410_dma_devconfig 300 * 301 * configure the device we're talking to 302*/ 303 304extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, 305 int hwcfg, unsigned long devaddr); 306 307/* s3c2410_dma_getposition 308 * 309 * get the position that the dma transfer is currently at 310*/ 311 312extern int s3c2410_dma_getposition(dmach_t channel, 313 dma_addr_t *src, dma_addr_t *dest); 314 315extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn); 316extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); 317 318/* DMA Register definitions */ 319 320#define S3C2410_DMA_DISRC (0x00) 321#define S3C2410_DMA_DISRCC (0x04) 322#define S3C2410_DMA_DIDST (0x08) 323#define S3C2410_DMA_DIDSTC (0x0C) 324#define S3C2410_DMA_DCON (0x10) 325#define S3C2410_DMA_DSTAT (0x14) 326#define S3C2410_DMA_DCSRC (0x18) 327#define S3C2410_DMA_DCDST (0x1C) 328#define S3C2410_DMA_DMASKTRIG (0x20) 329#define S3C2412_DMA_DMAREQSEL (0x24) 330#define S3C2443_DMA_DMAREQSEL (0x24) 331 332#define S3C2410_DISRCC_INC (1<<0) 333#define S3C2410_DISRCC_APB (1<<1) 334 335#define S3C2410_DMASKTRIG_STOP (1<<2) 336#define S3C2410_DMASKTRIG_ON (1<<1) 337#define S3C2410_DMASKTRIG_SWTRIG (1<<0) 338 339#define S3C2410_DCON_DEMAND (0<<31) 340#define S3C2410_DCON_HANDSHAKE (1<<31) 341#define S3C2410_DCON_SYNC_PCLK (0<<30) 342#define S3C2410_DCON_SYNC_HCLK (1<<30) 343 344#define S3C2410_DCON_INTREQ (1<<29) 345 346#define S3C2410_DCON_CH0_XDREQ0 (0<<24) 347#define S3C2410_DCON_CH0_UART0 (1<<24) 348#define S3C2410_DCON_CH0_SDI (2<<24) 349#define S3C2410_DCON_CH0_TIMER (3<<24) 350#define S3C2410_DCON_CH0_USBEP1 (4<<24) 351 352#define S3C2410_DCON_CH1_XDREQ1 (0<<24) 353#define S3C2410_DCON_CH1_UART1 (1<<24) 354#define S3C2410_DCON_CH1_I2SSDI (2<<24) 355#define S3C2410_DCON_CH1_SPI (3<<24) 356#define S3C2410_DCON_CH1_USBEP2 (4<<24) 357 358#define S3C2410_DCON_CH2_I2SSDO (0<<24) 359#define S3C2410_DCON_CH2_I2SSDI (1<<24) 360#define S3C2410_DCON_CH2_SDI (2<<24) 361#define S3C2410_DCON_CH2_TIMER (3<<24) 362#define S3C2410_DCON_CH2_USBEP3 (4<<24) 363 364#define S3C2410_DCON_CH3_UART2 (0<<24) 365#define S3C2410_DCON_CH3_SDI (1<<24) 366#define S3C2410_DCON_CH3_SPI (2<<24) 367#define S3C2410_DCON_CH3_TIMER (3<<24) 368#define S3C2410_DCON_CH3_USBEP4 (4<<24) 369 370#define S3C2410_DCON_SRCSHIFT (24) 371#define S3C2410_DCON_SRCMASK (7<<24) 372 373#define S3C2410_DCON_BYTE (0<<20) 374#define S3C2410_DCON_HALFWORD (1<<20) 375#define S3C2410_DCON_WORD (2<<20) 376 377#define S3C2410_DCON_AUTORELOAD (0<<22) 378#define S3C2410_DCON_NORELOAD (1<<22) 379#define S3C2410_DCON_HWTRIG (1<<23) 380 381#ifdef CONFIG_CPU_S3C2440 382#define S3C2440_DIDSTC_CHKINT (1<<2) 383 384#define S3C2440_DCON_CH0_I2SSDO (5<<24) 385#define S3C2440_DCON_CH0_PCMIN (6<<24) 386 387#define S3C2440_DCON_CH1_PCMOUT (5<<24) 388#define S3C2440_DCON_CH1_SDI (6<<24) 389 390#define S3C2440_DCON_CH2_PCMIN (5<<24) 391#define S3C2440_DCON_CH2_MICIN (6<<24) 392 393#define S3C2440_DCON_CH3_MICIN (5<<24) 394#define S3C2440_DCON_CH3_PCMOUT (6<<24) 395#endif 396 397#ifdef CONFIG_CPU_S3C2412 398 399#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1) 400 401#define S3C2412_DMAREQSEL_HW (1) 402 403#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0) 404#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1) 405#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2) 406#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3) 407#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4) 408#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5) 409#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9) 410#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10) 411#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13) 412#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14) 413#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15) 414#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16) 415#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17) 416#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18) 417#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19) 418#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20) 419#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21) 420#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22) 421#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23) 422#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) 423 424#endif 425 426#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1) 427 428#define S3C2443_DMAREQSEL_HW (1) 429 430#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0) 431#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1) 432#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2) 433#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3) 434#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4) 435#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5) 436#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9) 437#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10) 438#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17) 439#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18) 440#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19) 441#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20) 442#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21) 443#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22) 444#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23) 445#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24) 446#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25) 447#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26) 448#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27) 449#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28) 450#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29) 451 452#endif /* __ASM_ARCH_DMA_H */ 453