1/* 2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge 3 * 4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file COPYING in the main directory of this archive for 8 * more details. 9 * 10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/) 11 * which is based on the code of neofb. 12 */ 13 14#include <linux/version.h> 15#include <linux/module.h> 16#include <linux/kernel.h> 17#include <linux/errno.h> 18#include <linux/string.h> 19#include <linux/mm.h> 20#include <linux/tty.h> 21#include <linux/slab.h> 22#include <linux/delay.h> 23#include <linux/fb.h> 24#include <linux/svga.h> 25#include <linux/init.h> 26#include <linux/pci.h> 27#include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */ 28#include <video/vga.h> 29 30#ifdef CONFIG_MTRR 31#include <asm/mtrr.h> 32#endif 33 34struct s3fb_info { 35 int chip, rev, mclk_freq; 36 int mtrr_reg; 37 struct vgastate state; 38 struct mutex open_lock; 39 unsigned int ref_count; 40 u32 pseudo_palette[16]; 41}; 42 43 44/* ------------------------------------------------------------------------- */ 45 46static const struct svga_fb_format s3fb_formats[] = { 47 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 48 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16}, 49 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 50 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16}, 51 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1, 52 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16}, 53 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 54 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8}, 55 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, 56 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, 57 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, 58 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, 59 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, 60 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, 61 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, 62 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, 63 SVGA_FORMAT_END 64}; 65 66 67static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3, 68 35000, 240000, 14318}; 69 70static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512}; 71 72static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+", 73 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX", 74 "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge", 75 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX", 76 "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P"}; 77 78#define CHIP_UNKNOWN 0x00 79#define CHIP_732_TRIO32 0x01 80#define CHIP_764_TRIO64 0x02 81#define CHIP_765_TRIO64VP 0x03 82#define CHIP_767_TRIO64UVP 0x04 83#define CHIP_775_TRIO64V2_DX 0x05 84#define CHIP_785_TRIO64V2_GX 0x06 85#define CHIP_551_PLATO_PX 0x07 86#define CHIP_M65_AURORA64VP 0x08 87#define CHIP_325_VIRGE 0x09 88#define CHIP_988_VIRGE_VX 0x0A 89#define CHIP_375_VIRGE_DX 0x0B 90#define CHIP_385_VIRGE_GX 0x0C 91#define CHIP_356_VIRGE_GX2 0x0D 92#define CHIP_357_VIRGE_GX2P 0x0E 93#define CHIP_359_VIRGE_GX2P 0x0F 94 95#define CHIP_XXX_TRIO 0x80 96#define CHIP_XXX_TRIO64V2_DXGX 0x81 97#define CHIP_XXX_VIRGE_DXGX 0x82 98 99#define CHIP_UNDECIDED_FLAG 0x80 100#define CHIP_MASK 0xFF 101 102/* CRT timing register sets */ 103 104static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END}; 105static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END}; 106static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END}; 107static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END}; 108static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END}; 109static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; 110 111static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END}; 112static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END}; 113static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END}; 114static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END}; 115static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END}; 116static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; 117 118static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END}; 119static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END}; 120static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */ 121 122static const struct svga_timing_regs s3_timing_regs = { 123 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs, 124 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs, 125 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs, 126 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs, 127}; 128 129 130/* ------------------------------------------------------------------------- */ 131 132/* Module parameters */ 133 134 135static char *mode = "640x480-8@60"; 136 137#ifdef CONFIG_MTRR 138static int mtrr = 1; 139#endif 140 141static int fasttext = 1; 142 143 144MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>"); 145MODULE_LICENSE("GPL"); 146MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge"); 147 148module_param(mode, charp, 0444); 149MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc)"); 150 151#ifdef CONFIG_MTRR 152module_param(mtrr, int, 0444); 153MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)"); 154#endif 155 156module_param(fasttext, int, 0644); 157MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)"); 158 159 160/* ------------------------------------------------------------------------- */ 161 162/* Set font in S3 fast text mode */ 163 164static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) 165{ 166 const u8 *font = map->data; 167 u8 __iomem *fb = (u8 __iomem *) info->screen_base; 168 int i, c; 169 170 if ((map->width != 8) || (map->height != 16) || 171 (map->depth != 1) || (map->length != 256)) { 172 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n", 173 info->node, map->width, map->height, map->depth, map->length); 174 return; 175 } 176 177 fb += 2; 178 for (i = 0; i < map->height; i++) { 179 for (c = 0; c < map->length; c++) { 180 fb_writeb(font[c * map->height + i], fb + c * 4); 181 } 182 fb += 1024; 183 } 184} 185 186static struct fb_tile_ops s3fb_tile_ops = { 187 .fb_settile = svga_settile, 188 .fb_tilecopy = svga_tilecopy, 189 .fb_tilefill = svga_tilefill, 190 .fb_tileblit = svga_tileblit, 191 .fb_tilecursor = svga_tilecursor, 192 .fb_get_tilemax = svga_get_tilemax, 193}; 194 195static struct fb_tile_ops s3fb_fast_tile_ops = { 196 .fb_settile = s3fb_settile_fast, 197 .fb_tilecopy = svga_tilecopy, 198 .fb_tilefill = svga_tilefill, 199 .fb_tileblit = svga_tileblit, 200 .fb_tilecursor = svga_tilecursor, 201 .fb_get_tilemax = svga_get_tilemax, 202}; 203 204 205/* ------------------------------------------------------------------------- */ 206 207/* image data is MSB-first, fb structure is MSB-first too */ 208static inline u32 expand_color(u32 c) 209{ 210 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; 211} 212 213/* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */ 214static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image) 215{ 216 u32 fg = expand_color(image->fg_color); 217 u32 bg = expand_color(image->bg_color); 218 const u8 *src1, *src; 219 u8 __iomem *dst1; 220 u32 __iomem *dst; 221 u32 val; 222 int x, y; 223 224 src1 = image->data; 225 dst1 = info->screen_base + (image->dy * info->fix.line_length) 226 + ((image->dx / 8) * 4); 227 228 for (y = 0; y < image->height; y++) { 229 src = src1; 230 dst = (u32 __iomem *) dst1; 231 for (x = 0; x < image->width; x += 8) { 232 val = *(src++) * 0x01010101; 233 val = (val & fg) | (~val & bg); 234 fb_writel(val, dst++); 235 } 236 src1 += image->width / 8; 237 dst1 += info->fix.line_length; 238 } 239 240} 241 242/* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */ 243static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 244{ 245 u32 fg = expand_color(rect->color); 246 u8 __iomem *dst1; 247 u32 __iomem *dst; 248 int x, y; 249 250 dst1 = info->screen_base + (rect->dy * info->fix.line_length) 251 + ((rect->dx / 8) * 4); 252 253 for (y = 0; y < rect->height; y++) { 254 dst = (u32 __iomem *) dst1; 255 for (x = 0; x < rect->width; x += 8) { 256 fb_writel(fg, dst++); 257 } 258 dst1 += info->fix.line_length; 259 } 260} 261 262 263/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */ 264static inline u32 expand_pixel(u32 c) 265{ 266 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | 267 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; 268} 269 270/* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */ 271static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image) 272{ 273 u32 fg = image->fg_color * 0x11111111; 274 u32 bg = image->bg_color * 0x11111111; 275 const u8 *src1, *src; 276 u8 __iomem *dst1; 277 u32 __iomem *dst; 278 u32 val; 279 int x, y; 280 281 src1 = image->data; 282 dst1 = info->screen_base + (image->dy * info->fix.line_length) 283 + ((image->dx / 8) * 4); 284 285 for (y = 0; y < image->height; y++) { 286 src = src1; 287 dst = (u32 __iomem *) dst1; 288 for (x = 0; x < image->width; x += 8) { 289 val = expand_pixel(*(src++)); 290 val = (val & fg) | (~val & bg); 291 fb_writel(val, dst++); 292 } 293 src1 += image->width / 8; 294 dst1 += info->fix.line_length; 295 } 296} 297 298static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image) 299{ 300 if ((info->var.bits_per_pixel == 4) && (image->depth == 1) 301 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { 302 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) 303 s3fb_iplan_imageblit(info, image); 304 else 305 s3fb_cfb4_imageblit(info, image); 306 } else 307 cfb_imageblit(info, image); 308} 309 310static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 311{ 312 if ((info->var.bits_per_pixel == 4) 313 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) 314 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) 315 s3fb_iplan_fillrect(info, rect); 316 else 317 cfb_fillrect(info, rect); 318} 319 320 321 322/* ------------------------------------------------------------------------- */ 323 324 325static void s3_set_pixclock(struct fb_info *info, u32 pixclock) 326{ 327 u16 m, n, r; 328 u8 regval; 329 int rv; 330 331 rv = svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node); 332 if (rv < 0) { 333 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); 334 return; 335 } 336 337 /* Set VGA misc register */ 338 regval = vga_r(NULL, VGA_MIS_R); 339 vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); 340 341 /* Set S3 clock registers */ 342 vga_wseq(NULL, 0x12, ((n - 2) | (r << 5))); 343 vga_wseq(NULL, 0x13, m - 2); 344 345 udelay(1000); 346 347 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ 348 regval = vga_rseq (NULL, 0x15); /* | 0x80; */ 349 vga_wseq(NULL, 0x15, regval & ~(1<<5)); 350 vga_wseq(NULL, 0x15, regval | (1<<5)); 351 vga_wseq(NULL, 0x15, regval & ~(1<<5)); 352} 353 354 355/* Open framebuffer */ 356 357static int s3fb_open(struct fb_info *info, int user) 358{ 359 struct s3fb_info *par = info->par; 360 361 mutex_lock(&(par->open_lock)); 362 if (par->ref_count == 0) { 363 memset(&(par->state), 0, sizeof(struct vgastate)); 364 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; 365 par->state.num_crtc = 0x70; 366 par->state.num_seq = 0x20; 367 save_vga(&(par->state)); 368 } 369 370 par->ref_count++; 371 mutex_unlock(&(par->open_lock)); 372 373 return 0; 374} 375 376/* Close framebuffer */ 377 378static int s3fb_release(struct fb_info *info, int user) 379{ 380 struct s3fb_info *par = info->par; 381 382 mutex_lock(&(par->open_lock)); 383 if (par->ref_count == 0) { 384 mutex_unlock(&(par->open_lock)); 385 return -EINVAL; 386 } 387 388 if (par->ref_count == 1) 389 restore_vga(&(par->state)); 390 391 par->ref_count--; 392 mutex_unlock(&(par->open_lock)); 393 394 return 0; 395} 396 397/* Validate passed in var */ 398 399static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 400{ 401 struct s3fb_info *par = info->par; 402 int rv, mem, step; 403 404 /* Find appropriate format */ 405 rv = svga_match_format (s3fb_formats, var, NULL); 406 if ((rv < 0) || ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))) 407 { /* 24bpp on VIRGE VX, 32bpp on others */ 408 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node); 409 return rv; 410 } 411 412 /* Do not allow to have real resoulution larger than virtual */ 413 if (var->xres > var->xres_virtual) 414 var->xres_virtual = var->xres; 415 416 if (var->yres > var->yres_virtual) 417 var->yres_virtual = var->yres; 418 419 /* Round up xres_virtual to have proper alignment of lines */ 420 step = s3fb_formats[rv].xresstep - 1; 421 var->xres_virtual = (var->xres_virtual+step) & ~step; 422 423 /* Check whether have enough memory */ 424 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; 425 if (mem > info->screen_size) 426 { 427 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", 428 info->node, mem >> 10, (unsigned int) (info->screen_size >> 10)); 429 return -EINVAL; 430 } 431 432 rv = svga_check_timings (&s3_timing_regs, var, info->node); 433 if (rv < 0) 434 { 435 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node); 436 return rv; 437 } 438 439 return 0; 440} 441 442/* Set video mode from par */ 443 444static int s3fb_set_par(struct fb_info *info) 445{ 446 struct s3fb_info *par = info->par; 447 u32 value, mode, hmul, offset_value, screen_size, multiplex; 448 u32 bpp = info->var.bits_per_pixel; 449 450 if (bpp != 0) { 451 info->fix.ypanstep = 1; 452 info->fix.line_length = (info->var.xres_virtual * bpp) / 8; 453 454 info->flags &= ~FBINFO_MISC_TILEBLITTING; 455 info->tileops = NULL; 456 457 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ 458 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); 459 info->pixmap.blit_y = ~(u32)0; 460 461 offset_value = (info->var.xres_virtual * bpp) / 64; 462 screen_size = info->var.yres_virtual * info->fix.line_length; 463 } else { 464 info->fix.ypanstep = 16; 465 info->fix.line_length = 0; 466 467 info->flags |= FBINFO_MISC_TILEBLITTING; 468 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops; 469 470 /* supports 8x16 tiles only */ 471 info->pixmap.blit_x = 1 << (8 - 1); 472 info->pixmap.blit_y = 1 << (16 - 1); 473 474 offset_value = info->var.xres_virtual / 16; 475 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; 476 } 477 478 info->var.xoffset = 0; 479 info->var.yoffset = 0; 480 info->var.activate = FB_ACTIVATE_NOW; 481 482 /* Unlock registers */ 483 vga_wcrt(NULL, 0x38, 0x48); 484 vga_wcrt(NULL, 0x39, 0xA5); 485 vga_wseq(NULL, 0x08, 0x06); 486 svga_wcrt_mask(0x11, 0x00, 0x80); 487 488 /* Blank screen and turn off sync */ 489 svga_wseq_mask(0x01, 0x20, 0x20); 490 svga_wcrt_mask(0x17, 0x00, 0x80); 491 492 /* Set default values */ 493 svga_set_default_gfx_regs(); 494 svga_set_default_atc_regs(); 495 svga_set_default_seq_regs(); 496 svga_set_default_crt_regs(); 497 svga_wcrt_multi(s3_line_compare_regs, 0xFFFFFFFF); 498 svga_wcrt_multi(s3_start_address_regs, 0); 499 500 /* S3 specific initialization */ 501 svga_wcrt_mask(0x58, 0x10, 0x10); /* enable linear framebuffer */ 502 svga_wcrt_mask(0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */ 503 504/* svga_wcrt_mask(0x33, 0x08, 0x08); */ /* DDR ? */ 505/* svga_wcrt_mask(0x43, 0x01, 0x01); */ /* DDR ? */ 506 svga_wcrt_mask(0x33, 0x00, 0x08); /* no DDR ? */ 507 svga_wcrt_mask(0x43, 0x00, 0x01); /* no DDR ? */ 508 509 svga_wcrt_mask(0x5D, 0x00, 0x28); // Clear strange HSlen bits 510 511/* svga_wcrt_mask(0x58, 0x03, 0x03); */ 512 513/* svga_wcrt_mask(0x53, 0x12, 0x13); */ /* enable MMIO */ 514/* svga_wcrt_mask(0x40, 0x08, 0x08); */ /* enable write buffer */ 515 516 517 /* Set the offset register */ 518 pr_debug("fb%d: offset register : %d\n", info->node, offset_value); 519 svga_wcrt_multi(s3_offset_regs, offset_value); 520 521 vga_wcrt(NULL, 0x54, 0x18); /* M parameter */ 522 vga_wcrt(NULL, 0x60, 0xff); /* N parameter */ 523 vga_wcrt(NULL, 0x61, 0xff); /* L parameter */ 524 vga_wcrt(NULL, 0x62, 0xff); /* L parameter */ 525 526 vga_wcrt(NULL, 0x3A, 0x35); 527 svga_wattr(0x33, 0x00); 528 529 if (info->var.vmode & FB_VMODE_DOUBLE) 530 svga_wcrt_mask(0x09, 0x80, 0x80); 531 else 532 svga_wcrt_mask(0x09, 0x00, 0x80); 533 534 if (info->var.vmode & FB_VMODE_INTERLACED) 535 svga_wcrt_mask(0x42, 0x20, 0x20); 536 else 537 svga_wcrt_mask(0x42, 0x00, 0x20); 538 539 /* Disable hardware graphics cursor */ 540 svga_wcrt_mask(0x45, 0x00, 0x01); 541 /* Disable Streams engine */ 542 svga_wcrt_mask(0x67, 0x00, 0x0C); 543 544 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix)); 545 546 /* S3 virge DX hack */ 547 if (par->chip == CHIP_375_VIRGE_DX) { 548 vga_wcrt(NULL, 0x86, 0x80); 549 vga_wcrt(NULL, 0x90, 0x00); 550 } 551 552 /* S3 virge VX hack */ 553 if (par->chip == CHIP_988_VIRGE_VX) { 554 vga_wcrt(NULL, 0x50, 0x00); 555 vga_wcrt(NULL, 0x67, 0x50); 556 557 vga_wcrt(NULL, 0x63, (mode <= 2) ? 0x90 : 0x09); 558 vga_wcrt(NULL, 0x66, 0x90); 559 } 560 561 svga_wcrt_mask(0x31, 0x00, 0x40); 562 multiplex = 0; 563 hmul = 1; 564 565 /* Set mode-specific register values */ 566 switch (mode) { 567 case 0: 568 pr_debug("fb%d: text mode\n", info->node); 569 svga_set_textmode_vga_regs(); 570 571 /* Set additional registers like in 8-bit mode */ 572 svga_wcrt_mask(0x50, 0x00, 0x30); 573 svga_wcrt_mask(0x67, 0x00, 0xF0); 574 575 /* Disable enhanced mode */ 576 svga_wcrt_mask(0x3A, 0x00, 0x30); 577 578 if (fasttext) { 579 pr_debug("fb%d: high speed text mode set\n", info->node); 580 svga_wcrt_mask(0x31, 0x40, 0x40); 581 } 582 break; 583 case 1: 584 pr_debug("fb%d: 4 bit pseudocolor\n", info->node); 585 vga_wgfx(NULL, VGA_GFX_MODE, 0x40); 586 587 /* Set additional registers like in 8-bit mode */ 588 svga_wcrt_mask(0x50, 0x00, 0x30); 589 svga_wcrt_mask(0x67, 0x00, 0xF0); 590 591 /* disable enhanced mode */ 592 svga_wcrt_mask(0x3A, 0x00, 0x30); 593 break; 594 case 2: 595 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); 596 597 /* Set additional registers like in 8-bit mode */ 598 svga_wcrt_mask(0x50, 0x00, 0x30); 599 svga_wcrt_mask(0x67, 0x00, 0xF0); 600 601 /* disable enhanced mode */ 602 svga_wcrt_mask(0x3A, 0x00, 0x30); 603 break; 604 case 3: 605 pr_debug("fb%d: 8 bit pseudocolor\n", info->node); 606 if (info->var.pixclock > 20000) { 607 svga_wcrt_mask(0x50, 0x00, 0x30); 608 svga_wcrt_mask(0x67, 0x00, 0xF0); 609 } else { 610 svga_wcrt_mask(0x50, 0x00, 0x30); 611 svga_wcrt_mask(0x67, 0x10, 0xF0); 612 multiplex = 1; 613 } 614 break; 615 case 4: 616 pr_debug("fb%d: 5/5/5 truecolor\n", info->node); 617 if (par->chip == CHIP_988_VIRGE_VX) { 618 if (info->var.pixclock > 20000) 619 svga_wcrt_mask(0x67, 0x20, 0xF0); 620 else 621 svga_wcrt_mask(0x67, 0x30, 0xF0); 622 } else { 623 svga_wcrt_mask(0x50, 0x10, 0x30); 624 svga_wcrt_mask(0x67, 0x30, 0xF0); 625 hmul = 2; 626 } 627 break; 628 case 5: 629 pr_debug("fb%d: 5/6/5 truecolor\n", info->node); 630 if (par->chip == CHIP_988_VIRGE_VX) { 631 if (info->var.pixclock > 20000) 632 svga_wcrt_mask(0x67, 0x40, 0xF0); 633 else 634 svga_wcrt_mask(0x67, 0x50, 0xF0); 635 } else { 636 svga_wcrt_mask(0x50, 0x10, 0x30); 637 svga_wcrt_mask(0x67, 0x50, 0xF0); 638 hmul = 2; 639 } 640 break; 641 case 6: 642 /* VIRGE VX case */ 643 pr_debug("fb%d: 8/8/8 truecolor\n", info->node); 644 svga_wcrt_mask(0x67, 0xD0, 0xF0); 645 break; 646 case 7: 647 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); 648 svga_wcrt_mask(0x50, 0x30, 0x30); 649 svga_wcrt_mask(0x67, 0xD0, 0xF0); 650 break; 651 default: 652 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node); 653 return -EINVAL; 654 } 655 656 if (par->chip != CHIP_988_VIRGE_VX) { 657 svga_wseq_mask(0x15, multiplex ? 0x10 : 0x00, 0x10); 658 svga_wseq_mask(0x18, multiplex ? 0x80 : 0x00, 0x80); 659 } 660 661 s3_set_pixclock(info, info->var.pixclock); 662 svga_set_timings(&s3_timing_regs, &(info->var), hmul, 1, 663 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 664 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, 665 hmul, info->node); 666 667 /* Set interlaced mode start/end register */ 668 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; 669 value = ((value * hmul) / 8) - 5; 670 vga_wcrt(NULL, 0x3C, (value + 1) / 2); 671 672 memset_io(info->screen_base, 0x00, screen_size); 673 /* Device and screen back on */ 674 svga_wcrt_mask(0x17, 0x80, 0x80); 675 svga_wseq_mask(0x01, 0x00, 0x20); 676 677 return 0; 678} 679 680/* Set a colour register */ 681 682static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 683 u_int transp, struct fb_info *fb) 684{ 685 switch (fb->var.bits_per_pixel) { 686 case 0: 687 case 4: 688 if (regno >= 16) 689 return -EINVAL; 690 691 if ((fb->var.bits_per_pixel == 4) && 692 (fb->var.nonstd == 0)) { 693 outb(0xF0, VGA_PEL_MSK); 694 outb(regno*16, VGA_PEL_IW); 695 } else { 696 outb(0x0F, VGA_PEL_MSK); 697 outb(regno, VGA_PEL_IW); 698 } 699 outb(red >> 10, VGA_PEL_D); 700 outb(green >> 10, VGA_PEL_D); 701 outb(blue >> 10, VGA_PEL_D); 702 break; 703 case 8: 704 if (regno >= 256) 705 return -EINVAL; 706 707 outb(0xFF, VGA_PEL_MSK); 708 outb(regno, VGA_PEL_IW); 709 outb(red >> 10, VGA_PEL_D); 710 outb(green >> 10, VGA_PEL_D); 711 outb(blue >> 10, VGA_PEL_D); 712 break; 713 case 16: 714 if (regno >= 16) 715 return 0; 716 717 if (fb->var.green.length == 5) 718 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | 719 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11); 720 else if (fb->var.green.length == 6) 721 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | 722 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); 723 else return -EINVAL; 724 break; 725 case 24: 726 case 32: 727 if (regno >= 16) 728 return 0; 729 730 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | 731 (green & 0xFF00) | ((blue & 0xFF00) >> 8); 732 break; 733 default: 734 return -EINVAL; 735 } 736 737 return 0; 738} 739 740 741/* Set the display blanking state */ 742 743static int s3fb_blank(int blank_mode, struct fb_info *info) 744{ 745 switch (blank_mode) { 746 case FB_BLANK_UNBLANK: 747 pr_debug("fb%d: unblank\n", info->node); 748 svga_wcrt_mask(0x56, 0x00, 0x06); 749 svga_wseq_mask(0x01, 0x00, 0x20); 750 break; 751 case FB_BLANK_NORMAL: 752 pr_debug("fb%d: blank\n", info->node); 753 svga_wcrt_mask(0x56, 0x00, 0x06); 754 svga_wseq_mask(0x01, 0x20, 0x20); 755 break; 756 case FB_BLANK_HSYNC_SUSPEND: 757 pr_debug("fb%d: hsync\n", info->node); 758 svga_wcrt_mask(0x56, 0x02, 0x06); 759 svga_wseq_mask(0x01, 0x20, 0x20); 760 break; 761 case FB_BLANK_VSYNC_SUSPEND: 762 pr_debug("fb%d: vsync\n", info->node); 763 svga_wcrt_mask(0x56, 0x04, 0x06); 764 svga_wseq_mask(0x01, 0x20, 0x20); 765 break; 766 case FB_BLANK_POWERDOWN: 767 pr_debug("fb%d: sync down\n", info->node); 768 svga_wcrt_mask(0x56, 0x06, 0x06); 769 svga_wseq_mask(0x01, 0x20, 0x20); 770 break; 771 } 772 773 return 0; 774} 775 776 777/* Pan the display */ 778 779static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) { 780 781 unsigned int offset; 782 783 /* Calculate the offset */ 784 if (var->bits_per_pixel == 0) { 785 offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2); 786 offset = offset >> 2; 787 } else { 788 offset = (var->yoffset * info->fix.line_length) + 789 (var->xoffset * var->bits_per_pixel / 8); 790 offset = offset >> 2; 791 } 792 793 /* Set the offset */ 794 svga_wcrt_multi(s3_start_address_regs, offset); 795 796 return 0; 797} 798 799/* ------------------------------------------------------------------------- */ 800 801/* Frame buffer operations */ 802 803static struct fb_ops s3fb_ops = { 804 .owner = THIS_MODULE, 805 .fb_open = s3fb_open, 806 .fb_release = s3fb_release, 807 .fb_check_var = s3fb_check_var, 808 .fb_set_par = s3fb_set_par, 809 .fb_setcolreg = s3fb_setcolreg, 810 .fb_blank = s3fb_blank, 811 .fb_pan_display = s3fb_pan_display, 812 .fb_fillrect = s3fb_fillrect, 813 .fb_copyarea = cfb_copyarea, 814 .fb_imageblit = s3fb_imageblit, 815 .fb_get_caps = svga_get_caps, 816}; 817 818/* ------------------------------------------------------------------------- */ 819 820static int __devinit s3_identification(int chip) 821{ 822 if (chip == CHIP_XXX_TRIO) { 823 u8 cr30 = vga_rcrt(NULL, 0x30); 824 u8 cr2e = vga_rcrt(NULL, 0x2e); 825 u8 cr2f = vga_rcrt(NULL, 0x2f); 826 827 if ((cr30 == 0xE0) || (cr30 == 0xE1)) { 828 if (cr2e == 0x10) 829 return CHIP_732_TRIO32; 830 if (cr2e == 0x11) { 831 if (! (cr2f & 0x40)) 832 return CHIP_764_TRIO64; 833 else 834 return CHIP_765_TRIO64VP; 835 } 836 } 837 } 838 839 if (chip == CHIP_XXX_TRIO64V2_DXGX) { 840 u8 cr6f = vga_rcrt(NULL, 0x6f); 841 842 if (! (cr6f & 0x01)) 843 return CHIP_775_TRIO64V2_DX; 844 else 845 return CHIP_785_TRIO64V2_GX; 846 } 847 848 if (chip == CHIP_XXX_VIRGE_DXGX) { 849 u8 cr6f = vga_rcrt(NULL, 0x6f); 850 851 if (! (cr6f & 0x01)) 852 return CHIP_375_VIRGE_DX; 853 else 854 return CHIP_385_VIRGE_GX; 855 } 856 857 return CHIP_UNKNOWN; 858} 859 860 861/* PCI probe */ 862 863static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 864{ 865 struct fb_info *info; 866 struct s3fb_info *par; 867 int rc; 868 u8 regval, cr38, cr39; 869 870 /* Ignore secondary VGA device because there is no VGA arbitration */ 871 if (! svga_primary_device(dev)) { 872 dev_info(&(dev->dev), "ignoring secondary device\n"); 873 return -ENODEV; 874 } 875 876 /* Allocate and fill driver data structure */ 877 info = framebuffer_alloc(sizeof(struct s3fb_info), NULL); 878 if (!info) { 879 dev_err(&(dev->dev), "cannot allocate memory\n"); 880 return -ENOMEM; 881 } 882 883 par = info->par; 884 mutex_init(&par->open_lock); 885 886 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; 887 info->fbops = &s3fb_ops; 888 889 /* Prepare PCI device */ 890 rc = pci_enable_device(dev); 891 if (rc < 0) { 892 dev_err(&(dev->dev), "cannot enable PCI device\n"); 893 goto err_enable_device; 894 } 895 896 rc = pci_request_regions(dev, "s3fb"); 897 if (rc < 0) { 898 dev_err(&(dev->dev), "cannot reserve framebuffer region\n"); 899 goto err_request_regions; 900 } 901 902 903 info->fix.smem_start = pci_resource_start(dev, 0); 904 info->fix.smem_len = pci_resource_len(dev, 0); 905 906 /* Map physical IO memory address into kernel space */ 907 info->screen_base = pci_iomap(dev, 0, 0); 908 if (! info->screen_base) { 909 rc = -ENOMEM; 910 dev_err(&(dev->dev), "iomap for framebuffer failed\n"); 911 goto err_iomap; 912 } 913 914 /* Unlock regs */ 915 cr38 = vga_rcrt(NULL, 0x38); 916 cr39 = vga_rcrt(NULL, 0x39); 917 vga_wseq(NULL, 0x08, 0x06); 918 vga_wcrt(NULL, 0x38, 0x48); 919 vga_wcrt(NULL, 0x39, 0xA5); 920 921 /* Find how many physical memory there is on card */ 922 /* 0x36 register is accessible even if other registers are locked */ 923 regval = vga_rcrt(NULL, 0x36); 924 info->screen_size = s3_memsizes[regval >> 5] << 10; 925 info->fix.smem_len = info->screen_size; 926 927 par->chip = id->driver_data & CHIP_MASK; 928 par->rev = vga_rcrt(NULL, 0x2f); 929 if (par->chip & CHIP_UNDECIDED_FLAG) 930 par->chip = s3_identification(par->chip); 931 932 /* Find MCLK frequency */ 933 regval = vga_rseq(NULL, 0x10); 934 par->mclk_freq = ((vga_rseq(NULL, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); 935 par->mclk_freq = par->mclk_freq >> (regval >> 5); 936 937 /* Restore locks */ 938 vga_wcrt(NULL, 0x38, cr38); 939 vga_wcrt(NULL, 0x39, cr39); 940 941 strcpy(info->fix.id, s3_names [par->chip]); 942 info->fix.mmio_start = 0; 943 info->fix.mmio_len = 0; 944 info->fix.type = FB_TYPE_PACKED_PIXELS; 945 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 946 info->fix.ypanstep = 0; 947 info->fix.accel = FB_ACCEL_NONE; 948 info->pseudo_palette = (void*) (par->pseudo_palette); 949 950 /* Prepare startup mode */ 951 rc = fb_find_mode(&(info->var), info, mode, NULL, 0, NULL, 8); 952 if (! ((rc == 1) || (rc == 2))) { 953 rc = -EINVAL; 954 dev_err(&(dev->dev), "mode %s not found\n", mode); 955 goto err_find_mode; 956 } 957 958 rc = fb_alloc_cmap(&info->cmap, 256, 0); 959 if (rc < 0) { 960 dev_err(&(dev->dev), "cannot allocate colormap\n"); 961 goto err_alloc_cmap; 962 } 963 964 rc = register_framebuffer(info); 965 if (rc < 0) { 966 dev_err(&(dev->dev), "cannot register framebuffer\n"); 967 goto err_reg_fb; 968 } 969 970 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id, 971 pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); 972 973 if (par->chip == CHIP_UNKNOWN) 974 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", 975 info->node, vga_rcrt(NULL, 0x2d), vga_rcrt(NULL, 0x2e), 976 vga_rcrt(NULL, 0x2f), vga_rcrt(NULL, 0x30)); 977 978 /* Record a reference to the driver data */ 979 pci_set_drvdata(dev, info); 980 981#ifdef CONFIG_MTRR 982 if (mtrr) { 983 par->mtrr_reg = -1; 984 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1); 985 } 986#endif 987 988 return 0; 989 990 /* Error handling */ 991err_reg_fb: 992 fb_dealloc_cmap(&info->cmap); 993err_alloc_cmap: 994err_find_mode: 995 pci_iounmap(dev, info->screen_base); 996err_iomap: 997 pci_release_regions(dev); 998err_request_regions: 999/* pci_disable_device(dev); */ 1000err_enable_device: 1001 framebuffer_release(info); 1002 return rc; 1003} 1004 1005 1006/* PCI remove */ 1007 1008static void __devexit s3_pci_remove(struct pci_dev *dev) 1009{ 1010 struct fb_info *info = pci_get_drvdata(dev); 1011 1012 if (info) { 1013 1014#ifdef CONFIG_MTRR 1015 struct s3fb_info *par = info->par; 1016 1017 if (par->mtrr_reg >= 0) { 1018 mtrr_del(par->mtrr_reg, 0, 0); 1019 par->mtrr_reg = -1; 1020 } 1021#endif 1022 1023 unregister_framebuffer(info); 1024 fb_dealloc_cmap(&info->cmap); 1025 1026 pci_iounmap(dev, info->screen_base); 1027 pci_release_regions(dev); 1028/* pci_disable_device(dev); */ 1029 1030 pci_set_drvdata(dev, NULL); 1031 framebuffer_release(info); 1032 } 1033} 1034 1035/* PCI suspend */ 1036 1037static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state) 1038{ 1039 struct fb_info *info = pci_get_drvdata(dev); 1040 struct s3fb_info *par = info->par; 1041 1042 dev_info(&(dev->dev), "suspend\n"); 1043 1044 acquire_console_sem(); 1045 mutex_lock(&(par->open_lock)); 1046 1047 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) { 1048 mutex_unlock(&(par->open_lock)); 1049 release_console_sem(); 1050 return 0; 1051 } 1052 1053 fb_set_suspend(info, 1); 1054 1055 pci_save_state(dev); 1056 pci_disable_device(dev); 1057 pci_set_power_state(dev, pci_choose_state(dev, state)); 1058 1059 mutex_unlock(&(par->open_lock)); 1060 release_console_sem(); 1061 1062 return 0; 1063} 1064 1065 1066/* PCI resume */ 1067 1068static int s3_pci_resume(struct pci_dev* dev) 1069{ 1070 struct fb_info *info = pci_get_drvdata(dev); 1071 struct s3fb_info *par = info->par; 1072 int err; 1073 1074 dev_info(&(dev->dev), "resume\n"); 1075 1076 acquire_console_sem(); 1077 mutex_lock(&(par->open_lock)); 1078 1079 if (par->ref_count == 0) { 1080 mutex_unlock(&(par->open_lock)); 1081 release_console_sem(); 1082 return 0; 1083 } 1084 1085 pci_set_power_state(dev, PCI_D0); 1086 pci_restore_state(dev); 1087 err = pci_enable_device(dev); 1088 if (err) { 1089 mutex_unlock(&(par->open_lock)); 1090 release_console_sem(); 1091 dev_err(&(dev->dev), "error %d enabling device for resume\n", err); 1092 return err; 1093 } 1094 pci_set_master(dev); 1095 1096 s3fb_set_par(info); 1097 fb_set_suspend(info, 0); 1098 1099 mutex_unlock(&(par->open_lock)); 1100 release_console_sem(); 1101 1102 return 0; 1103} 1104 1105 1106/* List of boards that we are trying to support */ 1107 1108static struct pci_device_id s3_devices[] __devinitdata = { 1109 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO}, 1110 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO}, 1111 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP}, 1112 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP}, 1113 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX}, 1114 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX}, 1115 1116 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE}, 1117 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX}, 1118 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX}, 1119 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2}, 1120 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P}, 1121 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P}, 1122 1123 {0, 0, 0, 0, 0, 0, 0} 1124}; 1125 1126 1127MODULE_DEVICE_TABLE(pci, s3_devices); 1128 1129static struct pci_driver s3fb_pci_driver = { 1130 .name = "s3fb", 1131 .id_table = s3_devices, 1132 .probe = s3_pci_probe, 1133 .remove = __devexit_p(s3_pci_remove), 1134 .suspend = s3_pci_suspend, 1135 .resume = s3_pci_resume, 1136}; 1137 1138/* Parse user speficied options */ 1139 1140#ifndef MODULE 1141static int __init s3fb_setup(char *options) 1142{ 1143 char *opt; 1144 1145 if (!options || !*options) 1146 return 0; 1147 1148 while ((opt = strsep(&options, ",")) != NULL) { 1149 1150 if (!*opt) 1151 continue; 1152#ifdef CONFIG_MTRR 1153 else if (!strncmp(opt, "mtrr:", 5)) 1154 mtrr = simple_strtoul(opt + 5, NULL, 0); 1155#endif 1156 else if (!strncmp(opt, "fasttext:", 9)) 1157 fasttext = simple_strtoul(opt + 9, NULL, 0); 1158 else 1159 mode = opt; 1160 } 1161 1162 return 0; 1163} 1164#endif 1165 1166/* Cleanup */ 1167 1168static void __exit s3fb_cleanup(void) 1169{ 1170 pr_debug("s3fb: cleaning up\n"); 1171 pci_unregister_driver(&s3fb_pci_driver); 1172} 1173 1174/* Driver Initialisation */ 1175 1176static int __init s3fb_init(void) 1177{ 1178 1179#ifndef MODULE 1180 char *option = NULL; 1181 1182 if (fb_get_options("s3fb", &option)) 1183 return -ENODEV; 1184 s3fb_setup(option); 1185#endif 1186 1187 pr_debug("s3fb: initializing\n"); 1188 return pci_register_driver(&s3fb_pci_driver); 1189} 1190 1191/* ------------------------------------------------------------------------- */ 1192 1193/* Modularization */ 1194 1195module_init(s3fb_init); 1196module_exit(s3fb_cleanup); 1197