1/* 2 * linux/drivers/video/pxafb.c 3 * 4 * Copyright (C) 1999 Eric A. Thomas. 5 * Copyright (C) 2004 Jean-Frederic Clere. 6 * Copyright (C) 2004 Ian Campbell. 7 * Copyright (C) 2004 Jeff Lackey. 8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas 9 * which in turn is 10 * Based on acornfb.c Copyright (C) Russell King. 11 * 12 * This file is subject to the terms and conditions of the GNU General Public 13 * License. See the file COPYING in the main directory of this archive for 14 * more details. 15 * 16 * Intel PXA250/210 LCD Controller Frame Buffer Driver 17 * 18 * Please direct your questions and comments on this driver to the following 19 * email address: 20 * 21 * linux-arm-kernel@lists.arm.linux.org.uk 22 * 23 */ 24 25#include <linux/module.h> 26#include <linux/moduleparam.h> 27#include <linux/kernel.h> 28#include <linux/sched.h> 29#include <linux/errno.h> 30#include <linux/string.h> 31#include <linux/interrupt.h> 32#include <linux/slab.h> 33#include <linux/fb.h> 34#include <linux/delay.h> 35#include <linux/init.h> 36#include <linux/ioport.h> 37#include <linux/cpufreq.h> 38#include <linux/platform_device.h> 39#include <linux/dma-mapping.h> 40 41#include <asm/hardware.h> 42#include <asm/io.h> 43#include <asm/irq.h> 44#include <asm/uaccess.h> 45#include <asm/div64.h> 46#include <asm/arch/pxa-regs.h> 47#include <asm/arch/bitfield.h> 48#include <asm/arch/pxafb.h> 49 50/* 51 * Complain if VAR is out of range. 52 */ 53#define DEBUG_VAR 1 54 55#include "pxafb.h" 56 57/* Bits which should not be set in machine configuration structures */ 58#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB) 59#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP) 60 61static void (*pxafb_backlight_power)(int); 62static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); 63 64static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *); 65static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); 66 67#ifdef CONFIG_FB_PXA_PARAMETERS 68#define PXAFB_OPTIONS_SIZE 256 69static char g_options[PXAFB_OPTIONS_SIZE] __initdata = ""; 70#endif 71 72static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state) 73{ 74 unsigned long flags; 75 76 local_irq_save(flags); 77 /* 78 * We need to handle two requests being made at the same time. 79 * There are two important cases: 80 * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE) 81 * We must perform the unblanking, which will do our REENABLE for us. 82 * 2. When we are blanking, but immediately unblank before we have 83 * blanked. We do the "REENABLE" thing here as well, just to be sure. 84 */ 85 if (fbi->task_state == C_ENABLE && state == C_REENABLE) 86 state = (u_int) -1; 87 if (fbi->task_state == C_DISABLE && state == C_ENABLE) 88 state = C_REENABLE; 89 90 if (state != (u_int)-1) { 91 fbi->task_state = state; 92 schedule_work(&fbi->task); 93 } 94 local_irq_restore(flags); 95} 96 97static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) 98{ 99 chan &= 0xffff; 100 chan >>= 16 - bf->length; 101 return chan << bf->offset; 102} 103 104static int 105pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, 106 u_int trans, struct fb_info *info) 107{ 108 struct pxafb_info *fbi = (struct pxafb_info *)info; 109 u_int val, ret = 1; 110 111 if (regno < fbi->palette_size) { 112 if (fbi->fb.var.grayscale) { 113 val = ((blue >> 8) & 0x00ff); 114 } else { 115 val = ((red >> 0) & 0xf800); 116 val |= ((green >> 5) & 0x07e0); 117 val |= ((blue >> 11) & 0x001f); 118 } 119 fbi->palette_cpu[regno] = val; 120 ret = 0; 121 } 122 return ret; 123} 124 125static int 126pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 127 u_int trans, struct fb_info *info) 128{ 129 struct pxafb_info *fbi = (struct pxafb_info *)info; 130 unsigned int val; 131 int ret = 1; 132 133 /* 134 * If inverse mode was selected, invert all the colours 135 * rather than the register number. The register number 136 * is what you poke into the framebuffer to produce the 137 * colour you requested. 138 */ 139 if (fbi->cmap_inverse) { 140 red = 0xffff - red; 141 green = 0xffff - green; 142 blue = 0xffff - blue; 143 } 144 145 /* 146 * If greyscale is true, then we convert the RGB value 147 * to greyscale no matter what visual we are using. 148 */ 149 if (fbi->fb.var.grayscale) 150 red = green = blue = (19595 * red + 38470 * green + 151 7471 * blue) >> 16; 152 153 switch (fbi->fb.fix.visual) { 154 case FB_VISUAL_TRUECOLOR: 155 /* 156 * 16-bit True Colour. We encode the RGB value 157 * according to the RGB bitfield information. 158 */ 159 if (regno < 16) { 160 u32 *pal = fbi->fb.pseudo_palette; 161 162 val = chan_to_field(red, &fbi->fb.var.red); 163 val |= chan_to_field(green, &fbi->fb.var.green); 164 val |= chan_to_field(blue, &fbi->fb.var.blue); 165 166 pal[regno] = val; 167 ret = 0; 168 } 169 break; 170 171 case FB_VISUAL_STATIC_PSEUDOCOLOR: 172 case FB_VISUAL_PSEUDOCOLOR: 173 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info); 174 break; 175 } 176 177 return ret; 178} 179 180/* 181 * pxafb_bpp_to_lccr3(): 182 * Convert a bits per pixel value to the correct bit pattern for LCCR3 183 */ 184static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var) 185{ 186 int ret = 0; 187 switch (var->bits_per_pixel) { 188 case 1: ret = LCCR3_1BPP; break; 189 case 2: ret = LCCR3_2BPP; break; 190 case 4: ret = LCCR3_4BPP; break; 191 case 8: ret = LCCR3_8BPP; break; 192 case 16: ret = LCCR3_16BPP; break; 193 } 194 return ret; 195} 196 197#ifdef CONFIG_CPU_FREQ 198/* 199 * pxafb_display_dma_period() 200 * Calculate the minimum period (in picoseconds) between two DMA 201 * requests for the LCD controller. If we hit this, it means we're 202 * doing nothing but LCD DMA. 203 */ 204static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var) 205{ 206 /* 207 * Period = pixclock * bits_per_byte * bytes_per_transfer 208 * / memory_bits_per_pixel; 209 */ 210 return var->pixclock * 8 * 16 / var->bits_per_pixel; 211} 212 213extern unsigned int get_clk_frequency_khz(int info); 214#endif 215 216/* 217 * Select the smallest mode that allows the desired resolution to be 218 * displayed. If desired parameters can be rounded up. 219 */ 220static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach, struct fb_var_screeninfo *var) 221{ 222 struct pxafb_mode_info *mode = NULL; 223 struct pxafb_mode_info *modelist = mach->modes; 224 unsigned int best_x = 0xffffffff, best_y = 0xffffffff; 225 unsigned int i; 226 227 for (i = 0 ; i < mach->num_modes ; i++) { 228 if (modelist[i].xres >= var->xres && modelist[i].yres >= var->yres && 229 modelist[i].xres < best_x && modelist[i].yres < best_y && 230 modelist[i].bpp >= var->bits_per_pixel ) { 231 best_x = modelist[i].xres; 232 best_y = modelist[i].yres; 233 mode = &modelist[i]; 234 } 235 } 236 237 return mode; 238} 239 240static void pxafb_setmode(struct fb_var_screeninfo *var, struct pxafb_mode_info *mode) 241{ 242 var->xres = mode->xres; 243 var->yres = mode->yres; 244 var->bits_per_pixel = mode->bpp; 245 var->pixclock = mode->pixclock; 246 var->hsync_len = mode->hsync_len; 247 var->left_margin = mode->left_margin; 248 var->right_margin = mode->right_margin; 249 var->vsync_len = mode->vsync_len; 250 var->upper_margin = mode->upper_margin; 251 var->lower_margin = mode->lower_margin; 252 var->sync = mode->sync; 253 var->grayscale = mode->cmap_greyscale; 254 var->xres_virtual = var->xres; 255 var->yres_virtual = var->yres; 256} 257 258/* 259 * pxafb_check_var(): 260 * Get the video params out of 'var'. If a value doesn't fit, round it up, 261 * if it's too big, return -EINVAL. 262 * 263 * Round up in the following order: bits_per_pixel, xres, 264 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, 265 * bitfields, horizontal timing, vertical timing. 266 */ 267static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 268{ 269 struct pxafb_info *fbi = (struct pxafb_info *)info; 270 struct pxafb_mach_info *inf = fbi->dev->platform_data; 271 272 if (var->xres < MIN_XRES) 273 var->xres = MIN_XRES; 274 if (var->yres < MIN_YRES) 275 var->yres = MIN_YRES; 276 277 if (inf->fixed_modes) { 278 struct pxafb_mode_info *mode; 279 280 mode = pxafb_getmode(inf, var); 281 if (!mode) 282 return -EINVAL; 283 pxafb_setmode(var, mode); 284 } else { 285 if (var->xres > inf->modes->xres) 286 return -EINVAL; 287 if (var->yres > inf->modes->yres) 288 return -EINVAL; 289 if (var->bits_per_pixel > inf->modes->bpp) 290 return -EINVAL; 291 } 292 293 var->xres_virtual = 294 max(var->xres_virtual, var->xres); 295 var->yres_virtual = 296 max(var->yres_virtual, var->yres); 297 298 /* 299 * Setup the RGB parameters for this display. 300 * 301 * The pixel packing format is described on page 7-11 of the 302 * PXA2XX Developer's Manual. 303 */ 304 if (var->bits_per_pixel == 16) { 305 var->red.offset = 11; var->red.length = 5; 306 var->green.offset = 5; var->green.length = 6; 307 var->blue.offset = 0; var->blue.length = 5; 308 var->transp.offset = var->transp.length = 0; 309 } else { 310 var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0; 311 var->red.length = 8; 312 var->green.length = 8; 313 var->blue.length = 8; 314 var->transp.length = 0; 315 } 316 317#ifdef CONFIG_CPU_FREQ 318 pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n", 319 pxafb_display_dma_period(var), 320 get_clk_frequency_khz(0)); 321#endif 322 323 return 0; 324} 325 326static inline void pxafb_set_truecolor(u_int is_true_color) 327{ 328 pr_debug("pxafb: true_color = %d\n", is_true_color); 329 // do your machine-specific setup if needed 330} 331 332/* 333 * pxafb_set_par(): 334 * Set the user defined part of the display for the specified console 335 */ 336static int pxafb_set_par(struct fb_info *info) 337{ 338 struct pxafb_info *fbi = (struct pxafb_info *)info; 339 struct fb_var_screeninfo *var = &info->var; 340 unsigned long palette_mem_size; 341 342 pr_debug("pxafb: set_par\n"); 343 344 if (var->bits_per_pixel == 16) 345 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR; 346 else if (!fbi->cmap_static) 347 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; 348 else { 349 /* 350 * Some people have weird ideas about wanting static 351 * pseudocolor maps. I suspect their user space 352 * applications are broken. 353 */ 354 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; 355 } 356 357 fbi->fb.fix.line_length = var->xres_virtual * 358 var->bits_per_pixel / 8; 359 if (var->bits_per_pixel == 16) 360 fbi->palette_size = 0; 361 else 362 fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel; 363 364 palette_mem_size = fbi->palette_size * sizeof(u16); 365 366 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size); 367 368 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size); 369 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size; 370 371 /* 372 * Set (any) board control register to handle new color depth 373 */ 374 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR); 375 376 if (fbi->fb.var.bits_per_pixel == 16) 377 fb_dealloc_cmap(&fbi->fb.cmap); 378 else 379 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0); 380 381 pxafb_activate_var(var, fbi); 382 383 return 0; 384} 385 386/* 387 * Formal definition of the VESA spec: 388 * On 389 * This refers to the state of the display when it is in full operation 390 * Stand-By 391 * This defines an optional operating state of minimal power reduction with 392 * the shortest recovery time 393 * Suspend 394 * This refers to a level of power management in which substantial power 395 * reduction is achieved by the display. The display can have a longer 396 * recovery time from this state than from the Stand-by state 397 * Off 398 * This indicates that the display is consuming the lowest level of power 399 * and is non-operational. Recovery from this state may optionally require 400 * the user to manually power on the monitor 401 * 402 * Now, the fbdev driver adds an additional state, (blank), where they 403 * turn off the video (maybe by colormap tricks), but don't mess with the 404 * video itself: think of it semantically between on and Stand-By. 405 * 406 * So here's what we should do in our fbdev blank routine: 407 * 408 * VESA_NO_BLANKING (mode 0) Video on, front/back light on 409 * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off 410 * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off 411 * VESA_POWERDOWN (mode 3) Video off, front/back light off 412 * 413 * This will match the matrox implementation. 414 */ 415 416/* 417 * pxafb_blank(): 418 * Blank the display by setting all palette values to zero. Note, the 419 * 16 bpp mode does not really use the palette, so this will not 420 * blank the display in all modes. 421 */ 422static int pxafb_blank(int blank, struct fb_info *info) 423{ 424 struct pxafb_info *fbi = (struct pxafb_info *)info; 425 int i; 426 427 pr_debug("pxafb: blank=%d\n", blank); 428 429 switch (blank) { 430 case FB_BLANK_POWERDOWN: 431 case FB_BLANK_VSYNC_SUSPEND: 432 case FB_BLANK_HSYNC_SUSPEND: 433 case FB_BLANK_NORMAL: 434 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || 435 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) 436 for (i = 0; i < fbi->palette_size; i++) 437 pxafb_setpalettereg(i, 0, 0, 0, 0, info); 438 439 pxafb_schedule_work(fbi, C_DISABLE); 440 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); 441 break; 442 443 case FB_BLANK_UNBLANK: 444 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); 445 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || 446 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) 447 fb_set_cmap(&fbi->fb.cmap, info); 448 pxafb_schedule_work(fbi, C_ENABLE); 449 } 450 return 0; 451} 452 453static int pxafb_mmap(struct fb_info *info, 454 struct vm_area_struct *vma) 455{ 456 struct pxafb_info *fbi = (struct pxafb_info *)info; 457 unsigned long off = vma->vm_pgoff << PAGE_SHIFT; 458 459 if (off < info->fix.smem_len) { 460 vma->vm_pgoff += 1; 461 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu, 462 fbi->map_dma, fbi->map_size); 463 } 464 return -EINVAL; 465} 466 467static struct fb_ops pxafb_ops = { 468 .owner = THIS_MODULE, 469 .fb_check_var = pxafb_check_var, 470 .fb_set_par = pxafb_set_par, 471 .fb_setcolreg = pxafb_setcolreg, 472 .fb_fillrect = cfb_fillrect, 473 .fb_copyarea = cfb_copyarea, 474 .fb_imageblit = cfb_imageblit, 475 .fb_blank = pxafb_blank, 476 .fb_mmap = pxafb_mmap, 477}; 478 479/* 480 * Calculate the PCD value from the clock rate (in picoseconds). 481 * We take account of the PPCR clock setting. 482 * From PXA Developer's Manual: 483 * 484 * PixelClock = LCLK 485 * ------------- 486 * 2 ( PCD + 1 ) 487 * 488 * PCD = LCLK 489 * ------------- - 1 490 * 2(PixelClock) 491 * 492 * Where: 493 * LCLK = LCD/Memory Clock 494 * PCD = LCCR3[7:0] 495 * 496 * PixelClock here is in Hz while the pixclock argument given is the 497 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 ) 498 * 499 * The function get_lclk_frequency_10khz returns LCLK in units of 500 * 10khz. Calling the result of this function lclk gives us the 501 * following 502 * 503 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 ) 504 * -------------------------------------- - 1 505 * 2 506 * 507 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below. 508 */ 509static inline unsigned int get_pcd(unsigned int pixclock) 510{ 511 unsigned long long pcd; 512 513 514 pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock; 515 do_div(pcd, 100000000 * 2); 516 /* no need for this, since we should subtract 1 anyway. they cancel */ 517 /* pcd += 1; */ /* make up for integer math truncations */ 518 return (unsigned int)pcd; 519} 520 521/* 522 * Some touchscreens need hsync information from the video driver to 523 * function correctly. We export it here. 524 */ 525static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd) 526{ 527 unsigned long long htime; 528 529 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) { 530 fbi->hsync_time=0; 531 return; 532 } 533 534 htime = (unsigned long long)get_lcdclk_frequency_10khz() * 10000; 535 do_div(htime, pcd * fbi->fb.var.hsync_len); 536 fbi->hsync_time = htime; 537} 538 539unsigned long pxafb_get_hsync_time(struct device *dev) 540{ 541 struct pxafb_info *fbi = dev_get_drvdata(dev); 542 543 /* If display is blanked/suspended, hsync isn't active */ 544 if (!fbi || (fbi->state != C_ENABLE)) 545 return 0; 546 547 return fbi->hsync_time; 548} 549EXPORT_SYMBOL(pxafb_get_hsync_time); 550 551/* 552 * pxafb_activate_var(): 553 * Configures LCD Controller based on entries in var parameter. Settings are 554 * only written to the controller if changes were made. 555 */ 556static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi) 557{ 558 struct pxafb_lcd_reg new_regs; 559 u_long flags; 560 u_int lines_per_panel, pcd = get_pcd(var->pixclock); 561 562 pr_debug("pxafb: Configuring PXA LCD\n"); 563 564 pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n", 565 var->xres, var->hsync_len, 566 var->left_margin, var->right_margin); 567 pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n", 568 var->yres, var->vsync_len, 569 var->upper_margin, var->lower_margin); 570 pr_debug("var: pixclock=%d pcd=%d\n", var->pixclock, pcd); 571 572#if DEBUG_VAR 573 if (var->xres < 16 || var->xres > 1024) 574 printk(KERN_ERR "%s: invalid xres %d\n", 575 fbi->fb.fix.id, var->xres); 576 switch(var->bits_per_pixel) { 577 case 1: 578 case 2: 579 case 4: 580 case 8: 581 case 16: 582 break; 583 default: 584 printk(KERN_ERR "%s: invalid bit depth %d\n", 585 fbi->fb.fix.id, var->bits_per_pixel); 586 break; 587 } 588 if (var->hsync_len < 1 || var->hsync_len > 64) 589 printk(KERN_ERR "%s: invalid hsync_len %d\n", 590 fbi->fb.fix.id, var->hsync_len); 591 if (var->left_margin < 1 || var->left_margin > 255) 592 printk(KERN_ERR "%s: invalid left_margin %d\n", 593 fbi->fb.fix.id, var->left_margin); 594 if (var->right_margin < 1 || var->right_margin > 255) 595 printk(KERN_ERR "%s: invalid right_margin %d\n", 596 fbi->fb.fix.id, var->right_margin); 597 if (var->yres < 1 || var->yres > 1024) 598 printk(KERN_ERR "%s: invalid yres %d\n", 599 fbi->fb.fix.id, var->yres); 600 if (var->vsync_len < 1 || var->vsync_len > 64) 601 printk(KERN_ERR "%s: invalid vsync_len %d\n", 602 fbi->fb.fix.id, var->vsync_len); 603 if (var->upper_margin < 0 || var->upper_margin > 255) 604 printk(KERN_ERR "%s: invalid upper_margin %d\n", 605 fbi->fb.fix.id, var->upper_margin); 606 if (var->lower_margin < 0 || var->lower_margin > 255) 607 printk(KERN_ERR "%s: invalid lower_margin %d\n", 608 fbi->fb.fix.id, var->lower_margin); 609#endif 610 611 new_regs.lccr0 = fbi->lccr0 | 612 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | 613 LCCR0_QDM | LCCR0_BM | LCCR0_OUM); 614 615 new_regs.lccr1 = 616 LCCR1_DisWdth(var->xres) + 617 LCCR1_HorSnchWdth(var->hsync_len) + 618 LCCR1_BegLnDel(var->left_margin) + 619 LCCR1_EndLnDel(var->right_margin); 620 621 /* 622 * If we have a dual scan LCD, we need to halve 623 * the YRES parameter. 624 */ 625 lines_per_panel = var->yres; 626 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) 627 lines_per_panel /= 2; 628 629 new_regs.lccr2 = 630 LCCR2_DisHght(lines_per_panel) + 631 LCCR2_VrtSnchWdth(var->vsync_len) + 632 LCCR2_BegFrmDel(var->upper_margin) + 633 LCCR2_EndFrmDel(var->lower_margin); 634 635 new_regs.lccr3 = fbi->lccr3 | 636 pxafb_bpp_to_lccr3(var) | 637 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) | 638 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL); 639 640 if (pcd) 641 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd); 642 643 pr_debug("nlccr0 = 0x%08x\n", new_regs.lccr0); 644 pr_debug("nlccr1 = 0x%08x\n", new_regs.lccr1); 645 pr_debug("nlccr2 = 0x%08x\n", new_regs.lccr2); 646 pr_debug("nlccr3 = 0x%08x\n", new_regs.lccr3); 647 648 /* Update shadow copy atomically */ 649 local_irq_save(flags); 650 651 /* setup dma descriptors */ 652 fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16); 653 fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16); 654 fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16); 655 656 fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16; 657 fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16; 658 fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16; 659 660#define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length) 661 662 /* populate descriptors */ 663 fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma; 664 fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL; 665 fbi->dmadesc_fblow_cpu->fidr = 0; 666 fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL; 667 668 fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */ 669 670 fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma; 671 fbi->dmadesc_fbhigh_cpu->fidr = 0; 672 fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL; 673 674 fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma; 675 fbi->dmadesc_palette_cpu->fidr = 0; 676 fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL; 677 678 if (var->bits_per_pixel == 16) { 679 /* palette shouldn't be loaded in true-color mode */ 680 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma; 681 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */ 682 /* init it to something, even though we won't be using it */ 683 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma; 684 } else { 685 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma; 686 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma; 687 fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */ 688 } 689 690 691 fbi->reg_lccr0 = new_regs.lccr0; 692 fbi->reg_lccr1 = new_regs.lccr1; 693 fbi->reg_lccr2 = new_regs.lccr2; 694 fbi->reg_lccr3 = new_regs.lccr3; 695 set_hsync_time(fbi, pcd); 696 local_irq_restore(flags); 697 698 /* 699 * Only update the registers if the controller is enabled 700 * and something has changed. 701 */ 702 if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) || 703 (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) || 704 (FDADR0 != fbi->fdadr0) || (FDADR1 != fbi->fdadr1)) 705 pxafb_schedule_work(fbi, C_REENABLE); 706 707 return 0; 708} 709 710/* 711 * NOTE! The following functions are purely helpers for set_ctrlr_state. 712 * Do not call them directly; set_ctrlr_state does the correct serialisation 713 * to ensure that things happen in the right way 100% of time time. 714 * -- rmk 715 */ 716static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on) 717{ 718 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff"); 719 720 if (pxafb_backlight_power) 721 pxafb_backlight_power(on); 722} 723 724static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) 725{ 726 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff"); 727 728 if (pxafb_lcd_power) 729 pxafb_lcd_power(on, &fbi->fb.var); 730} 731 732static void pxafb_setup_gpio(struct pxafb_info *fbi) 733{ 734 int gpio, ldd_bits; 735 unsigned int lccr0 = fbi->lccr0; 736 737 /* 738 * setup is based on type of panel supported 739 */ 740 741 /* 4 bit interface */ 742 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono && 743 (lccr0 & LCCR0_SDS) == LCCR0_Sngl && 744 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono) 745 ldd_bits = 4; 746 747 /* 8 bit interface */ 748 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono && 749 ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) || 750 ((lccr0 & LCCR0_CMS) == LCCR0_Color && 751 (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl)) 752 ldd_bits = 8; 753 754 /* 16 bit interface */ 755 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color && 756 ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act)) 757 ldd_bits = 16; 758 759 else { 760 printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n"); 761 return; 762 } 763 764 for (gpio = 58; ldd_bits; gpio++, ldd_bits--) 765 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT); 766 pxa_gpio_mode(GPIO74_LCD_FCLK_MD); 767 pxa_gpio_mode(GPIO75_LCD_LCLK_MD); 768 pxa_gpio_mode(GPIO76_LCD_PCLK_MD); 769 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD); 770} 771 772static void pxafb_enable_controller(struct pxafb_info *fbi) 773{ 774 pr_debug("pxafb: Enabling LCD controller\n"); 775 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0); 776 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1); 777 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0); 778 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1); 779 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2); 780 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); 781 782 /* enable LCD controller clock */ 783 pxa_set_cken(CKEN_LCD, 1); 784 785 /* Sequence from 11.7.10 */ 786 LCCR3 = fbi->reg_lccr3; 787 LCCR2 = fbi->reg_lccr2; 788 LCCR1 = fbi->reg_lccr1; 789 LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB; 790 791 FDADR0 = fbi->fdadr0; 792 FDADR1 = fbi->fdadr1; 793 LCCR0 |= LCCR0_ENB; 794 795 pr_debug("FDADR0 0x%08x\n", (unsigned int) FDADR0); 796 pr_debug("FDADR1 0x%08x\n", (unsigned int) FDADR1); 797 pr_debug("LCCR0 0x%08x\n", (unsigned int) LCCR0); 798 pr_debug("LCCR1 0x%08x\n", (unsigned int) LCCR1); 799 pr_debug("LCCR2 0x%08x\n", (unsigned int) LCCR2); 800 pr_debug("LCCR3 0x%08x\n", (unsigned int) LCCR3); 801} 802 803static void pxafb_disable_controller(struct pxafb_info *fbi) 804{ 805 DECLARE_WAITQUEUE(wait, current); 806 807 pr_debug("pxafb: disabling LCD controller\n"); 808 809 set_current_state(TASK_UNINTERRUPTIBLE); 810 add_wait_queue(&fbi->ctrlr_wait, &wait); 811 812 LCSR = 0xffffffff; /* Clear LCD Status Register */ 813 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */ 814 LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */ 815 816 schedule_timeout(200 * HZ / 1000); 817 remove_wait_queue(&fbi->ctrlr_wait, &wait); 818 819 /* disable LCD controller clock */ 820 pxa_set_cken(CKEN_LCD, 0); 821} 822 823/* 824 * pxafb_handle_irq: Handle 'LCD DONE' interrupts. 825 */ 826static irqreturn_t pxafb_handle_irq(int irq, void *dev_id) 827{ 828 struct pxafb_info *fbi = dev_id; 829 unsigned int lcsr = LCSR; 830 831 if (lcsr & LCSR_LDD) { 832 LCCR0 |= LCCR0_LDM; 833 wake_up(&fbi->ctrlr_wait); 834 } 835 836 LCSR = lcsr; 837 return IRQ_HANDLED; 838} 839 840/* 841 * This function must be called from task context only, since it will 842 * sleep when disabling the LCD controller, or if we get two contending 843 * processes trying to alter state. 844 */ 845static void set_ctrlr_state(struct pxafb_info *fbi, u_int state) 846{ 847 u_int old_state; 848 849 down(&fbi->ctrlr_sem); 850 851 old_state = fbi->state; 852 853 /* 854 * Hack around fbcon initialisation. 855 */ 856 if (old_state == C_STARTUP && state == C_REENABLE) 857 state = C_ENABLE; 858 859 switch (state) { 860 case C_DISABLE_CLKCHANGE: 861 /* 862 * Disable controller for clock change. If the 863 * controller is already disabled, then do nothing. 864 */ 865 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) { 866 fbi->state = state; 867 //TODO __pxafb_lcd_power(fbi, 0); 868 pxafb_disable_controller(fbi); 869 } 870 break; 871 872 case C_DISABLE_PM: 873 case C_DISABLE: 874 /* 875 * Disable controller 876 */ 877 if (old_state != C_DISABLE) { 878 fbi->state = state; 879 __pxafb_backlight_power(fbi, 0); 880 __pxafb_lcd_power(fbi, 0); 881 if (old_state != C_DISABLE_CLKCHANGE) 882 pxafb_disable_controller(fbi); 883 } 884 break; 885 886 case C_ENABLE_CLKCHANGE: 887 /* 888 * Enable the controller after clock change. Only 889 * do this if we were disabled for the clock change. 890 */ 891 if (old_state == C_DISABLE_CLKCHANGE) { 892 fbi->state = C_ENABLE; 893 pxafb_enable_controller(fbi); 894 //TODO __pxafb_lcd_power(fbi, 1); 895 } 896 break; 897 898 case C_REENABLE: 899 /* 900 * Re-enable the controller only if it was already 901 * enabled. This is so we reprogram the control 902 * registers. 903 */ 904 if (old_state == C_ENABLE) { 905 __pxafb_lcd_power(fbi, 0); 906 pxafb_disable_controller(fbi); 907 pxafb_setup_gpio(fbi); 908 pxafb_enable_controller(fbi); 909 __pxafb_lcd_power(fbi, 1); 910 } 911 break; 912 913 case C_ENABLE_PM: 914 /* 915 * Re-enable the controller after PM. This is not 916 * perfect - think about the case where we were doing 917 * a clock change, and we suspended half-way through. 918 */ 919 if (old_state != C_DISABLE_PM) 920 break; 921 /* fall through */ 922 923 case C_ENABLE: 924 /* 925 * Power up the LCD screen, enable controller, and 926 * turn on the backlight. 927 */ 928 if (old_state != C_ENABLE) { 929 fbi->state = C_ENABLE; 930 pxafb_setup_gpio(fbi); 931 pxafb_enable_controller(fbi); 932 __pxafb_lcd_power(fbi, 1); 933 __pxafb_backlight_power(fbi, 1); 934 } 935 break; 936 } 937 up(&fbi->ctrlr_sem); 938} 939 940/* 941 * Our LCD controller task (which is called when we blank or unblank) 942 * via keventd. 943 */ 944static void pxafb_task(struct work_struct *work) 945{ 946 struct pxafb_info *fbi = 947 container_of(work, struct pxafb_info, task); 948 u_int state = xchg(&fbi->task_state, -1); 949 950 set_ctrlr_state(fbi, state); 951} 952 953#ifdef CONFIG_CPU_FREQ 954/* 955 * CPU clock speed change handler. We need to adjust the LCD timing 956 * parameters when the CPU clock is adjusted by the power management 957 * subsystem. 958 * 959 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz() 960 */ 961static int 962pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data) 963{ 964 struct pxafb_info *fbi = TO_INF(nb, freq_transition); 965 //TODO struct cpufreq_freqs *f = data; 966 u_int pcd; 967 968 switch (val) { 969 case CPUFREQ_PRECHANGE: 970 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE); 971 break; 972 973 case CPUFREQ_POSTCHANGE: 974 pcd = get_pcd(fbi->fb.var.pixclock); 975 set_hsync_time(fbi, pcd); 976 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd); 977 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); 978 break; 979 } 980 return 0; 981} 982 983static int 984pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data) 985{ 986 struct pxafb_info *fbi = TO_INF(nb, freq_policy); 987 struct fb_var_screeninfo *var = &fbi->fb.var; 988 struct cpufreq_policy *policy = data; 989 990 switch (val) { 991 case CPUFREQ_ADJUST: 992 case CPUFREQ_INCOMPATIBLE: 993 printk(KERN_DEBUG "min dma period: %d ps, " 994 "new clock %d kHz\n", pxafb_display_dma_period(var), 995 policy->max); 996 // TODO: fill in min/max values 997 break; 998 } 999 return 0; 1000} 1001#endif 1002 1003#ifdef CONFIG_PM 1004/* 1005 * Power management hooks. Note that we won't be called from IRQ context, 1006 * unlike the blank functions above, so we may sleep. 1007 */ 1008static int pxafb_suspend(struct platform_device *dev, pm_message_t state) 1009{ 1010 struct pxafb_info *fbi = platform_get_drvdata(dev); 1011 1012 set_ctrlr_state(fbi, C_DISABLE_PM); 1013 return 0; 1014} 1015 1016static int pxafb_resume(struct platform_device *dev) 1017{ 1018 struct pxafb_info *fbi = platform_get_drvdata(dev); 1019 1020 set_ctrlr_state(fbi, C_ENABLE_PM); 1021 return 0; 1022} 1023#else 1024#define pxafb_suspend NULL 1025#define pxafb_resume NULL 1026#endif 1027 1028/* 1029 * pxafb_map_video_memory(): 1030 * Allocates the DRAM memory for the frame buffer. This buffer is 1031 * remapped into a non-cached, non-buffered, memory region to 1032 * allow palette and pixel writes to occur without flushing the 1033 * cache. Once this area is remapped, all virtual memory 1034 * access to the video memory should occur at the new region. 1035 */ 1036static int __init pxafb_map_video_memory(struct pxafb_info *fbi) 1037{ 1038 u_long palette_mem_size; 1039 1040 /* 1041 * We reserve one page for the palette, plus the size 1042 * of the framebuffer. 1043 */ 1044 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE); 1045 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size, 1046 &fbi->map_dma, GFP_KERNEL); 1047 1048 if (fbi->map_cpu) { 1049 /* prevent initial garbage on screen */ 1050 memset(fbi->map_cpu, 0, fbi->map_size); 1051 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE; 1052 fbi->screen_dma = fbi->map_dma + PAGE_SIZE; 1053 fbi->fb.fix.smem_start = fbi->screen_dma; 1054 1055 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16; 1056 1057 palette_mem_size = fbi->palette_size * sizeof(u16); 1058 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size); 1059 1060 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size); 1061 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size; 1062 } 1063 1064 return fbi->map_cpu ? 0 : -ENOMEM; 1065} 1066 1067static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev) 1068{ 1069 struct pxafb_info *fbi; 1070 void *addr; 1071 struct pxafb_mach_info *inf = dev->platform_data; 1072 struct pxafb_mode_info *mode = inf->modes; 1073 int i, smemlen; 1074 1075 /* Alloc the pxafb_info and pseudo_palette in one step */ 1076 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL); 1077 if (!fbi) 1078 return NULL; 1079 1080 memset(fbi, 0, sizeof(struct pxafb_info)); 1081 fbi->dev = dev; 1082 1083 strcpy(fbi->fb.fix.id, PXA_NAME); 1084 1085 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; 1086 fbi->fb.fix.type_aux = 0; 1087 fbi->fb.fix.xpanstep = 0; 1088 fbi->fb.fix.ypanstep = 0; 1089 fbi->fb.fix.ywrapstep = 0; 1090 fbi->fb.fix.accel = FB_ACCEL_NONE; 1091 1092 fbi->fb.var.nonstd = 0; 1093 fbi->fb.var.activate = FB_ACTIVATE_NOW; 1094 fbi->fb.var.height = -1; 1095 fbi->fb.var.width = -1; 1096 fbi->fb.var.accel_flags = 0; 1097 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; 1098 1099 fbi->fb.fbops = &pxafb_ops; 1100 fbi->fb.flags = FBINFO_DEFAULT; 1101 fbi->fb.node = -1; 1102 1103 addr = fbi; 1104 addr = addr + sizeof(struct pxafb_info); 1105 fbi->fb.pseudo_palette = addr; 1106 1107 pxafb_setmode(&fbi->fb.var, mode); 1108 1109 fbi->cmap_inverse = inf->cmap_inverse; 1110 fbi->cmap_static = inf->cmap_static; 1111 1112 fbi->lccr0 = inf->lccr0; 1113 fbi->lccr3 = inf->lccr3; 1114 fbi->state = C_STARTUP; 1115 fbi->task_state = (u_char)-1; 1116 1117 for (i = 0; i < inf->num_modes; i++) { 1118 smemlen = mode[i].xres * mode[i].yres * mode[i].bpp / 8; 1119 if (smemlen > fbi->fb.fix.smem_len) 1120 fbi->fb.fix.smem_len = smemlen; 1121 } 1122 1123 init_waitqueue_head(&fbi->ctrlr_wait); 1124 INIT_WORK(&fbi->task, pxafb_task); 1125 init_MUTEX(&fbi->ctrlr_sem); 1126 1127 return fbi; 1128} 1129 1130#ifdef CONFIG_FB_PXA_PARAMETERS 1131static int __init pxafb_parse_options(struct device *dev, char *options) 1132{ 1133 struct pxafb_mach_info *inf = dev->platform_data; 1134 char *this_opt; 1135 1136 if (!options || !*options) 1137 return 0; 1138 1139 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null"); 1140 1141 /* could be made table driven or similar?... */ 1142 while ((this_opt = strsep(&options, ",")) != NULL) { 1143 if (!strncmp(this_opt, "mode:", 5)) { 1144 const char *name = this_opt+5; 1145 unsigned int namelen = strlen(name); 1146 int res_specified = 0, bpp_specified = 0; 1147 unsigned int xres = 0, yres = 0, bpp = 0; 1148 int yres_specified = 0; 1149 int i; 1150 for (i = namelen-1; i >= 0; i--) { 1151 switch (name[i]) { 1152 case '-': 1153 namelen = i; 1154 if (!bpp_specified && !yres_specified) { 1155 bpp = simple_strtoul(&name[i+1], NULL, 0); 1156 bpp_specified = 1; 1157 } else 1158 goto done; 1159 break; 1160 case 'x': 1161 if (!yres_specified) { 1162 yres = simple_strtoul(&name[i+1], NULL, 0); 1163 yres_specified = 1; 1164 } else 1165 goto done; 1166 break; 1167 case '0' ... '9': 1168 break; 1169 default: 1170 goto done; 1171 } 1172 } 1173 if (i < 0 && yres_specified) { 1174 xres = simple_strtoul(name, NULL, 0); 1175 res_specified = 1; 1176 } 1177 done: 1178 if (res_specified) { 1179 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres); 1180 inf->modes[0].xres = xres; inf->modes[0].yres = yres; 1181 } 1182 if (bpp_specified) 1183 switch (bpp) { 1184 case 1: 1185 case 2: 1186 case 4: 1187 case 8: 1188 case 16: 1189 inf->modes[0].bpp = bpp; 1190 dev_info(dev, "overriding bit depth: %d\n", bpp); 1191 break; 1192 default: 1193 dev_err(dev, "Depth %d is not valid\n", bpp); 1194 } 1195 } else if (!strncmp(this_opt, "pixclock:", 9)) { 1196 inf->modes[0].pixclock = simple_strtoul(this_opt+9, NULL, 0); 1197 dev_info(dev, "override pixclock: %ld\n", inf->modes[0].pixclock); 1198 } else if (!strncmp(this_opt, "left:", 5)) { 1199 inf->modes[0].left_margin = simple_strtoul(this_opt+5, NULL, 0); 1200 dev_info(dev, "override left: %u\n", inf->modes[0].left_margin); 1201 } else if (!strncmp(this_opt, "right:", 6)) { 1202 inf->modes[0].right_margin = simple_strtoul(this_opt+6, NULL, 0); 1203 dev_info(dev, "override right: %u\n", inf->modes[0].right_margin); 1204 } else if (!strncmp(this_opt, "upper:", 6)) { 1205 inf->modes[0].upper_margin = simple_strtoul(this_opt+6, NULL, 0); 1206 dev_info(dev, "override upper: %u\n", inf->modes[0].upper_margin); 1207 } else if (!strncmp(this_opt, "lower:", 6)) { 1208 inf->modes[0].lower_margin = simple_strtoul(this_opt+6, NULL, 0); 1209 dev_info(dev, "override lower: %u\n", inf->modes[0].lower_margin); 1210 } else if (!strncmp(this_opt, "hsynclen:", 9)) { 1211 inf->modes[0].hsync_len = simple_strtoul(this_opt+9, NULL, 0); 1212 dev_info(dev, "override hsynclen: %u\n", inf->modes[0].hsync_len); 1213 } else if (!strncmp(this_opt, "vsynclen:", 9)) { 1214 inf->modes[0].vsync_len = simple_strtoul(this_opt+9, NULL, 0); 1215 dev_info(dev, "override vsynclen: %u\n", inf->modes[0].vsync_len); 1216 } else if (!strncmp(this_opt, "hsync:", 6)) { 1217 if (simple_strtoul(this_opt+6, NULL, 0) == 0) { 1218 dev_info(dev, "override hsync: Active Low\n"); 1219 inf->modes[0].sync &= ~FB_SYNC_HOR_HIGH_ACT; 1220 } else { 1221 dev_info(dev, "override hsync: Active High\n"); 1222 inf->modes[0].sync |= FB_SYNC_HOR_HIGH_ACT; 1223 } 1224 } else if (!strncmp(this_opt, "vsync:", 6)) { 1225 if (simple_strtoul(this_opt+6, NULL, 0) == 0) { 1226 dev_info(dev, "override vsync: Active Low\n"); 1227 inf->modes[0].sync &= ~FB_SYNC_VERT_HIGH_ACT; 1228 } else { 1229 dev_info(dev, "override vsync: Active High\n"); 1230 inf->modes[0].sync |= FB_SYNC_VERT_HIGH_ACT; 1231 } 1232 } else if (!strncmp(this_opt, "dpc:", 4)) { 1233 if (simple_strtoul(this_opt+4, NULL, 0) == 0) { 1234 dev_info(dev, "override double pixel clock: false\n"); 1235 inf->lccr3 &= ~LCCR3_DPC; 1236 } else { 1237 dev_info(dev, "override double pixel clock: true\n"); 1238 inf->lccr3 |= LCCR3_DPC; 1239 } 1240 } else if (!strncmp(this_opt, "outputen:", 9)) { 1241 if (simple_strtoul(this_opt+9, NULL, 0) == 0) { 1242 dev_info(dev, "override output enable: active low\n"); 1243 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL; 1244 } else { 1245 dev_info(dev, "override output enable: active high\n"); 1246 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH; 1247 } 1248 } else if (!strncmp(this_opt, "pixclockpol:", 12)) { 1249 if (simple_strtoul(this_opt+12, NULL, 0) == 0) { 1250 dev_info(dev, "override pixel clock polarity: falling edge\n"); 1251 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg; 1252 } else { 1253 dev_info(dev, "override pixel clock polarity: rising edge\n"); 1254 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg; 1255 } 1256 } else if (!strncmp(this_opt, "color", 5)) { 1257 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color; 1258 } else if (!strncmp(this_opt, "mono", 4)) { 1259 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono; 1260 } else if (!strncmp(this_opt, "active", 6)) { 1261 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act; 1262 } else if (!strncmp(this_opt, "passive", 7)) { 1263 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas; 1264 } else if (!strncmp(this_opt, "single", 6)) { 1265 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl; 1266 } else if (!strncmp(this_opt, "dual", 4)) { 1267 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual; 1268 } else if (!strncmp(this_opt, "4pix", 4)) { 1269 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono; 1270 } else if (!strncmp(this_opt, "8pix", 4)) { 1271 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono; 1272 } else { 1273 dev_err(dev, "unknown option: %s\n", this_opt); 1274 return -EINVAL; 1275 } 1276 } 1277 return 0; 1278 1279} 1280#endif 1281 1282int __init pxafb_probe(struct platform_device *dev) 1283{ 1284 struct pxafb_info *fbi; 1285 struct pxafb_mach_info *inf; 1286 int ret; 1287 1288 dev_dbg(&dev->dev, "pxafb_probe\n"); 1289 1290 inf = dev->dev.platform_data; 1291 ret = -ENOMEM; 1292 fbi = NULL; 1293 if (!inf) 1294 goto failed; 1295 1296#ifdef CONFIG_FB_PXA_PARAMETERS 1297 ret = pxafb_parse_options(&dev->dev, g_options); 1298 if (ret < 0) 1299 goto failed; 1300#endif 1301 1302#ifdef DEBUG_VAR 1303 /* Check for various illegal bit-combinations. Currently only 1304 * a warning is given. */ 1305 1306 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK) 1307 dev_warn(&dev->dev, "machine LCCR0 setting contains illegal bits: %08x\n", 1308 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK); 1309 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK) 1310 dev_warn(&dev->dev, "machine LCCR3 setting contains illegal bits: %08x\n", 1311 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK); 1312 if (inf->lccr0 & LCCR0_DPD && 1313 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas || 1314 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl || 1315 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono)) 1316 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is only valid in passive mono" 1317 " single panel mode\n"); 1318 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act && 1319 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual) 1320 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n"); 1321 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas && 1322 (inf->modes->upper_margin || inf->modes->lower_margin)) 1323 dev_warn(&dev->dev, "Upper and lower margins must be 0 in passive mode\n"); 1324#endif 1325 1326 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",inf->modes->xres, inf->modes->yres, inf->modes->bpp); 1327 if (inf->modes->xres == 0 || inf->modes->yres == 0 || inf->modes->bpp == 0) { 1328 dev_err(&dev->dev, "Invalid resolution or bit depth\n"); 1329 ret = -EINVAL; 1330 goto failed; 1331 } 1332 pxafb_backlight_power = inf->pxafb_backlight_power; 1333 pxafb_lcd_power = inf->pxafb_lcd_power; 1334 fbi = pxafb_init_fbinfo(&dev->dev); 1335 if (!fbi) { 1336 dev_err(&dev->dev, "Failed to initialize framebuffer device\n"); 1337 ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc 1338 goto failed; 1339 } 1340 1341 /* Initialize video memory */ 1342 ret = pxafb_map_video_memory(fbi); 1343 if (ret) { 1344 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret); 1345 ret = -ENOMEM; 1346 goto failed; 1347 } 1348 1349 ret = request_irq(IRQ_LCD, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi); 1350 if (ret) { 1351 dev_err(&dev->dev, "request_irq failed: %d\n", ret); 1352 ret = -EBUSY; 1353 goto failed; 1354 } 1355 1356 /* 1357 * This makes sure that our colour bitfield 1358 * descriptors are correctly initialised. 1359 */ 1360 pxafb_check_var(&fbi->fb.var, &fbi->fb); 1361 pxafb_set_par(&fbi->fb); 1362 1363 platform_set_drvdata(dev, fbi); 1364 1365 ret = register_framebuffer(&fbi->fb); 1366 if (ret < 0) { 1367 dev_err(&dev->dev, "Failed to register framebuffer device: %d\n", ret); 1368 goto failed; 1369 } 1370 1371#ifdef CONFIG_PM 1372 // TODO 1373#endif 1374 1375#ifdef CONFIG_CPU_FREQ 1376 fbi->freq_transition.notifier_call = pxafb_freq_transition; 1377 fbi->freq_policy.notifier_call = pxafb_freq_policy; 1378 cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); 1379 cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER); 1380#endif 1381 1382 /* 1383 * Ok, now enable the LCD controller 1384 */ 1385 set_ctrlr_state(fbi, C_ENABLE); 1386 1387 return 0; 1388 1389failed: 1390 platform_set_drvdata(dev, NULL); 1391 kfree(fbi); 1392 return ret; 1393} 1394 1395static struct platform_driver pxafb_driver = { 1396 .probe = pxafb_probe, 1397#ifdef CONFIG_PM 1398 .suspend = pxafb_suspend, 1399 .resume = pxafb_resume, 1400#endif 1401 .driver = { 1402 .name = "pxa2xx-fb", 1403 }, 1404}; 1405 1406#ifndef MODULE 1407int __devinit pxafb_setup(char *options) 1408{ 1409# ifdef CONFIG_FB_PXA_PARAMETERS 1410 if (options) 1411 strlcpy(g_options, options, sizeof(g_options)); 1412# endif 1413 return 0; 1414} 1415#else 1416# ifdef CONFIG_FB_PXA_PARAMETERS 1417module_param_string(options, g_options, sizeof(g_options), 0); 1418MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)"); 1419# endif 1420#endif 1421 1422int __devinit pxafb_init(void) 1423{ 1424#ifndef MODULE 1425 char *option = NULL; 1426 1427 if (fb_get_options("pxafb", &option)) 1428 return -ENODEV; 1429 pxafb_setup(option); 1430#endif 1431 return platform_driver_register(&pxafb_driver); 1432} 1433 1434module_init(pxafb_init); 1435 1436MODULE_DESCRIPTION("loadable framebuffer driver for PXA"); 1437MODULE_LICENSE("GPL"); 1438