1 2/* 3 * ATI Mach64 GX Support 4 */ 5 6#include <linux/delay.h> 7#include <linux/fb.h> 8 9#include <asm/io.h> 10 11#include <video/mach64.h> 12#include "atyfb.h" 13 14/* Definitions for the ICS 2595 == ATI 18818_1 Clockchip */ 15 16#define REF_FREQ_2595 1432 /* 14.33 MHz (exact 14.31818) */ 17#define REF_DIV_2595 46 /* really 43 on ICS 2595 !!! */ 18 /* ohne Prescaler */ 19#define MAX_FREQ_2595 15938 /* 159.38 MHz (really 170.486) */ 20#define MIN_FREQ_2595 8000 /* 80.00 MHz ( 85.565) */ 21 /* mit Prescaler 2, 4, 8 */ 22#define ABS_MIN_FREQ_2595 1000 /* 10.00 MHz (really 10.697) */ 23#define N_ADJ_2595 257 24 25#define STOP_BITS_2595 0x1800 26 27 28#define MIN_N_408 2 29 30#define MIN_N_1703 6 31 32#define MIN_M 2 33#define MAX_M 30 34#define MIN_N 35 35#define MAX_N 255-8 36 37 38 /* 39 * Support Functions 40 */ 41 42static void aty_dac_waste4(const struct atyfb_par *par) 43{ 44 (void) aty_ld_8(DAC_REGS, par); 45 46 (void) aty_ld_8(DAC_REGS + 2, par); 47 (void) aty_ld_8(DAC_REGS + 2, par); 48 (void) aty_ld_8(DAC_REGS + 2, par); 49 (void) aty_ld_8(DAC_REGS + 2, par); 50} 51 52static void aty_StrobeClock(const struct atyfb_par *par) 53{ 54 u8 tmp; 55 56 udelay(26); 57 58 tmp = aty_ld_8(CLOCK_CNTL, par); 59 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, tmp | CLOCK_STROBE, par); 60 return; 61} 62 63 64 /* 65 * IBM RGB514 DAC and Clock Chip 66 */ 67 68static void aty_st_514(int offset, u8 val, const struct atyfb_par *par) 69{ 70 aty_st_8(DAC_CNTL, 1, par); 71 /* right addr byte */ 72 aty_st_8(DAC_W_INDEX, offset & 0xff, par); 73 /* left addr byte */ 74 aty_st_8(DAC_DATA, (offset >> 8) & 0xff, par); 75 aty_st_8(DAC_MASK, val, par); 76 aty_st_8(DAC_CNTL, 0, par); 77} 78 79static int aty_set_dac_514(const struct fb_info *info, 80 const union aty_pll *pll, u32 bpp, u32 accel) 81{ 82 struct atyfb_par *par = (struct atyfb_par *) info->par; 83 static struct { 84 u8 pixel_dly; 85 u8 misc2_cntl; 86 u8 pixel_rep; 87 u8 pixel_cntl_index; 88 u8 pixel_cntl_v1; 89 } tab[3] = { 90 { 91 0, 0x41, 0x03, 0x71, 0x45}, /* 8 bpp */ 92 { 93 0, 0x45, 0x04, 0x0c, 0x01}, /* 555 */ 94 { 95 0, 0x45, 0x06, 0x0e, 0x00}, /* XRGB */ 96 }; 97 int i; 98 99 switch (bpp) { 100 case 8: 101 default: 102 i = 0; 103 break; 104 case 16: 105 i = 1; 106 break; 107 case 32: 108 i = 2; 109 break; 110 } 111 aty_st_514(0x90, 0x00, par); /* VRAM Mask Low */ 112 aty_st_514(0x04, tab[i].pixel_dly, par); /* Horizontal Sync Control */ 113 aty_st_514(0x05, 0x00, par); /* Power Management */ 114 aty_st_514(0x02, 0x01, par); /* Misc Clock Control */ 115 aty_st_514(0x71, tab[i].misc2_cntl, par); /* Misc Control 2 */ 116 aty_st_514(0x0a, tab[i].pixel_rep, par); /* Pixel Format */ 117 aty_st_514(tab[i].pixel_cntl_index, tab[i].pixel_cntl_v1, par); 118 /* Misc Control 2 / 16 BPP Control / 32 BPP Control */ 119 return 0; 120} 121 122static int aty_var_to_pll_514(const struct fb_info *info, u32 vclk_per, 123 u32 bpp, union aty_pll *pll) 124{ 125 static struct { 126 u32 limit; /* pixlock rounding limit (arbitrary) */ 127 u8 m; /* (df<<6) | vco_div_count */ 128 u8 n; /* ref_div_count */ 129 } RGB514_clocks[7] = { 130 { 131 8000, (3 << 6) | 20, 9}, /* 7395 ps / 135.2273 MHz */ 132 { 133 10000, (1 << 6) | 19, 3}, /* 9977 ps / 100.2273 MHz */ 134 { 135 13000, (1 << 6) | 2, 3}, /* 12509 ps / 79.9432 MHz */ 136 { 137 14000, (2 << 6) | 8, 7}, /* 13394 ps / 74.6591 MHz */ 138 { 139 16000, (1 << 6) | 44, 6}, /* 15378 ps / 65.0284 MHz */ 140 { 141 25000, (1 << 6) | 15, 5}, /* 17460 ps / 57.2727 MHz */ 142 { 143 50000, (0 << 6) | 53, 7}, /* 33145 ps / 30.1705 MHz */ 144 }; 145 int i; 146 147 for (i = 0; i < ARRAY_SIZE(RGB514_clocks); i++) 148 if (vclk_per <= RGB514_clocks[i].limit) { 149 pll->ibm514.m = RGB514_clocks[i].m; 150 pll->ibm514.n = RGB514_clocks[i].n; 151 return 0; 152 } 153 return -EINVAL; 154} 155 156static u32 aty_pll_514_to_var(const struct fb_info *info, 157 const union aty_pll *pll) 158{ 159 struct atyfb_par *par = (struct atyfb_par *) info->par; 160 u8 df, vco_div_count, ref_div_count; 161 162 df = pll->ibm514.m >> 6; 163 vco_div_count = pll->ibm514.m & 0x3f; 164 ref_div_count = pll->ibm514.n; 165 166 return ((par->ref_clk_per * ref_div_count) << (3 - df))/ 167 (vco_div_count + 65); 168} 169 170static void aty_set_pll_514(const struct fb_info *info, 171 const union aty_pll *pll) 172{ 173 struct atyfb_par *par = (struct atyfb_par *) info->par; 174 175 aty_st_514(0x06, 0x02, par); /* DAC Operation */ 176 aty_st_514(0x10, 0x01, par); /* PLL Control 1 */ 177 aty_st_514(0x70, 0x01, par); /* Misc Control 1 */ 178 aty_st_514(0x8f, 0x1f, par); /* PLL Ref. Divider Input */ 179 aty_st_514(0x03, 0x00, par); /* Sync Control */ 180 aty_st_514(0x05, 0x00, par); /* Power Management */ 181 aty_st_514(0x20, pll->ibm514.m, par); /* F0 / M0 */ 182 aty_st_514(0x21, pll->ibm514.n, par); /* F1 / N0 */ 183} 184 185const struct aty_dac_ops aty_dac_ibm514 = { 186 .set_dac = aty_set_dac_514, 187}; 188 189const struct aty_pll_ops aty_pll_ibm514 = { 190 .var_to_pll = aty_var_to_pll_514, 191 .pll_to_var = aty_pll_514_to_var, 192 .set_pll = aty_set_pll_514, 193}; 194 195 196 /* 197 * ATI 68860-B DAC 198 */ 199 200static int aty_set_dac_ATI68860_B(const struct fb_info *info, 201 const union aty_pll *pll, u32 bpp, 202 u32 accel) 203{ 204 struct atyfb_par *par = (struct atyfb_par *) info->par; 205 u32 gModeReg, devSetupRegA, temp, mask; 206 207 gModeReg = 0; 208 devSetupRegA = 0; 209 210 switch (bpp) { 211 case 8: 212 gModeReg = 0x83; 213 devSetupRegA = 214 0x60 | 0x00 /*(info->mach64DAC8Bit ? 0x00 : 0x01) */ ; 215 break; 216 case 15: 217 gModeReg = 0xA0; 218 devSetupRegA = 0x60; 219 break; 220 case 16: 221 gModeReg = 0xA1; 222 devSetupRegA = 0x60; 223 break; 224 case 24: 225 gModeReg = 0xC0; 226 devSetupRegA = 0x60; 227 break; 228 case 32: 229 gModeReg = 0xE3; 230 devSetupRegA = 0x60; 231 break; 232 } 233 234 if (!accel) { 235 gModeReg = 0x80; 236 devSetupRegA = 0x61; 237 } 238 239 temp = aty_ld_8(DAC_CNTL, par); 240 aty_st_8(DAC_CNTL, (temp & ~DAC_EXT_SEL_RS2) | DAC_EXT_SEL_RS3, 241 par); 242 243 aty_st_8(DAC_REGS + 2, 0x1D, par); 244 aty_st_8(DAC_REGS + 3, gModeReg, par); 245 aty_st_8(DAC_REGS, 0x02, par); 246 247 temp = aty_ld_8(DAC_CNTL, par); 248 aty_st_8(DAC_CNTL, temp | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3, par); 249 250 if (info->fix.smem_len < ONE_MB) 251 mask = 0x04; 252 else if (info->fix.smem_len == ONE_MB) 253 mask = 0x08; 254 else 255 mask = 0x0C; 256 257 /* The following assumes that the BIOS has correctly set R7 of the 258 * Device Setup Register A at boot time. 259 */ 260#define A860_DELAY_L 0x80 261 262 temp = aty_ld_8(DAC_REGS, par); 263 aty_st_8(DAC_REGS, (devSetupRegA | mask) | (temp & A860_DELAY_L), 264 par); 265 temp = aty_ld_8(DAC_CNTL, par); 266 aty_st_8(DAC_CNTL, (temp & ~(DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3)), 267 par); 268 269 aty_st_le32(BUS_CNTL, 0x890e20f1, par); 270 aty_st_le32(DAC_CNTL, 0x47052100, par); 271 return 0; 272} 273 274const struct aty_dac_ops aty_dac_ati68860b = { 275 .set_dac = aty_set_dac_ATI68860_B, 276}; 277 278 279 /* 280 * AT&T 21C498 DAC 281 */ 282 283static int aty_set_dac_ATT21C498(const struct fb_info *info, 284 const union aty_pll *pll, u32 bpp, 285 u32 accel) 286{ 287 struct atyfb_par *par = (struct atyfb_par *) info->par; 288 u32 dotClock; 289 int muxmode = 0; 290 int DACMask = 0; 291 292 dotClock = 100000000 / pll->ics2595.period_in_ps; 293 294 switch (bpp) { 295 case 8: 296 if (dotClock > 8000) { 297 DACMask = 0x24; 298 muxmode = 1; 299 } else 300 DACMask = 0x04; 301 break; 302 case 15: 303 DACMask = 0x16; 304 break; 305 case 16: 306 DACMask = 0x36; 307 break; 308 case 24: 309 DACMask = 0xE6; 310 break; 311 case 32: 312 DACMask = 0xE6; 313 break; 314 } 315 316 if (1 /* info->mach64DAC8Bit */ ) 317 DACMask |= 0x02; 318 319 aty_dac_waste4(par); 320 aty_st_8(DAC_REGS + 2, DACMask, par); 321 322 aty_st_le32(BUS_CNTL, 0x890e20f1, par); 323 aty_st_le32(DAC_CNTL, 0x00072000, par); 324 return muxmode; 325} 326 327const struct aty_dac_ops aty_dac_att21c498 = { 328 .set_dac = aty_set_dac_ATT21C498, 329}; 330 331 332 /* 333 * ATI 18818 / ICS 2595 Clock Chip 334 */ 335 336static int aty_var_to_pll_18818(const struct fb_info *info, u32 vclk_per, 337 u32 bpp, union aty_pll *pll) 338{ 339 u32 MHz100; /* in 0.01 MHz */ 340 u32 program_bits; 341 u32 post_divider; 342 343 /* Calculate the programming word */ 344 MHz100 = 100000000 / vclk_per; 345 346 program_bits = -1; 347 post_divider = 1; 348 349 if (MHz100 > MAX_FREQ_2595) { 350 MHz100 = MAX_FREQ_2595; 351 return -EINVAL; 352 } else if (MHz100 < ABS_MIN_FREQ_2595) { 353 program_bits = 0; /* MHz100 = 257 */ 354 return -EINVAL; 355 } else { 356 while (MHz100 < MIN_FREQ_2595) { 357 MHz100 *= 2; 358 post_divider *= 2; 359 } 360 } 361 MHz100 *= 1000; 362 MHz100 = (REF_DIV_2595 * MHz100) / REF_FREQ_2595; 363 364 MHz100 += 500; /* + 0.5 round */ 365 MHz100 /= 1000; 366 367 if (program_bits == -1) { 368 program_bits = MHz100 - N_ADJ_2595; 369 switch (post_divider) { 370 case 1: 371 program_bits |= 0x0600; 372 break; 373 case 2: 374 program_bits |= 0x0400; 375 break; 376 case 4: 377 program_bits |= 0x0200; 378 break; 379 case 8: 380 default: 381 break; 382 } 383 } 384 385 program_bits |= STOP_BITS_2595; 386 387 pll->ics2595.program_bits = program_bits; 388 pll->ics2595.locationAddr = 0; 389 pll->ics2595.post_divider = post_divider; 390 pll->ics2595.period_in_ps = vclk_per; 391 392 return 0; 393} 394 395static u32 aty_pll_18818_to_var(const struct fb_info *info, 396 const union aty_pll *pll) 397{ 398 return (pll->ics2595.period_in_ps); /* default for now */ 399} 400 401static void aty_ICS2595_put1bit(u8 data, const struct atyfb_par *par) 402{ 403 u8 tmp; 404 405 data &= 0x01; 406 tmp = aty_ld_8(CLOCK_CNTL, par); 407 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 408 (tmp & ~0x04) | (data << 2), par); 409 410 tmp = aty_ld_8(CLOCK_CNTL, par); 411 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (0 << 3), 412 par); 413 414 aty_StrobeClock(par); 415 416 tmp = aty_ld_8(CLOCK_CNTL, par); 417 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (1 << 3), 418 par); 419 420 aty_StrobeClock(par); 421 return; 422} 423 424static void aty_set_pll18818(const struct fb_info *info, 425 const union aty_pll *pll) 426{ 427 struct atyfb_par *par = (struct atyfb_par *) info->par; 428 u32 program_bits; 429 u32 locationAddr; 430 431 u32 i; 432 433 u8 old_clock_cntl; 434 u8 old_crtc_ext_disp; 435 436 old_clock_cntl = aty_ld_8(CLOCK_CNTL, par); 437 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 0, par); 438 439 old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par); 440 aty_st_8(CRTC_GEN_CNTL + 3, 441 old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par); 442 443 mdelay(15); /* delay for 50 (15) ms */ 444 445 program_bits = pll->ics2595.program_bits; 446 locationAddr = pll->ics2595.locationAddr; 447 448 /* Program the clock chip */ 449 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 0, par); /* Strobe = 0 */ 450 aty_StrobeClock(par); 451 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 1, par); /* Strobe = 0 */ 452 aty_StrobeClock(par); 453 454 aty_ICS2595_put1bit(1, par); /* Send start bits */ 455 aty_ICS2595_put1bit(0, par); /* Start bit */ 456 aty_ICS2595_put1bit(0, par); /* Read / ~Write */ 457 458 for (i = 0; i < 5; i++) { /* Location 0..4 */ 459 aty_ICS2595_put1bit(locationAddr & 1, par); 460 locationAddr >>= 1; 461 } 462 463 for (i = 0; i < 8 + 1 + 2 + 2; i++) { 464 aty_ICS2595_put1bit(program_bits & 1, par); 465 program_bits >>= 1; 466 } 467 468 mdelay(1); /* delay for 1 ms */ 469 470 (void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */ 471 aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par); 472 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 473 old_clock_cntl | CLOCK_STROBE, par); 474 475 mdelay(50); /* delay for 50 (15) ms */ 476 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 477 ((pll->ics2595.locationAddr & 0x0F) | CLOCK_STROBE), par); 478 return; 479} 480 481const struct aty_pll_ops aty_pll_ati18818_1 = { 482 .var_to_pll = aty_var_to_pll_18818, 483 .pll_to_var = aty_pll_18818_to_var, 484 .set_pll = aty_set_pll18818, 485}; 486 487 488 /* 489 * STG 1703 Clock Chip 490 */ 491 492static int aty_var_to_pll_1703(const struct fb_info *info, u32 vclk_per, 493 u32 bpp, union aty_pll *pll) 494{ 495 u32 mhz100; /* in 0.01 MHz */ 496 u32 program_bits; 497 /* u32 post_divider; */ 498 u32 mach64MinFreq, mach64MaxFreq, mach64RefFreq; 499 u32 temp, tempB; 500 u16 remainder, preRemainder; 501 short divider = 0, tempA; 502 503 /* Calculate the programming word */ 504 mhz100 = 100000000 / vclk_per; 505 mach64MinFreq = MIN_FREQ_2595; 506 mach64MaxFreq = MAX_FREQ_2595; 507 mach64RefFreq = REF_FREQ_2595; /* 14.32 MHz */ 508 509 /* Calculate program word */ 510 if (mhz100 == 0) 511 program_bits = 0xE0; 512 else { 513 if (mhz100 < mach64MinFreq) 514 mhz100 = mach64MinFreq; 515 if (mhz100 > mach64MaxFreq) 516 mhz100 = mach64MaxFreq; 517 518 divider = 0; 519 while (mhz100 < (mach64MinFreq << 3)) { 520 mhz100 <<= 1; 521 divider += 0x20; 522 } 523 524 temp = (unsigned int) (mhz100); 525 temp = (unsigned int) (temp * (MIN_N_1703 + 2)); 526 temp -= (short) (mach64RefFreq << 1); 527 528 tempA = MIN_N_1703; 529 preRemainder = 0xffff; 530 531 do { 532 tempB = temp; 533 remainder = tempB % mach64RefFreq; 534 tempB = tempB / mach64RefFreq; 535 536 if ((tempB & 0xffff) <= 127 537 && (remainder <= preRemainder)) { 538 preRemainder = remainder; 539 divider &= ~0x1f; 540 divider |= tempA; 541 divider = 542 (divider & 0x00ff) + 543 ((tempB & 0xff) << 8); 544 } 545 546 temp += mhz100; 547 tempA++; 548 } while (tempA <= (MIN_N_1703 << 1)); 549 550 program_bits = divider; 551 } 552 553 pll->ics2595.program_bits = program_bits; 554 pll->ics2595.locationAddr = 0; 555 pll->ics2595.post_divider = divider; /* fuer nix */ 556 pll->ics2595.period_in_ps = vclk_per; 557 558 return 0; 559} 560 561static u32 aty_pll_1703_to_var(const struct fb_info *info, 562 const union aty_pll *pll) 563{ 564 return (pll->ics2595.period_in_ps); /* default for now */ 565} 566 567static void aty_set_pll_1703(const struct fb_info *info, 568 const union aty_pll *pll) 569{ 570 struct atyfb_par *par = (struct atyfb_par *) info->par; 571 u32 program_bits; 572 u32 locationAddr; 573 574 char old_crtc_ext_disp; 575 576 old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par); 577 aty_st_8(CRTC_GEN_CNTL + 3, 578 old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par); 579 580 program_bits = pll->ics2595.program_bits; 581 locationAddr = pll->ics2595.locationAddr; 582 583 /* Program clock */ 584 aty_dac_waste4(par); 585 586 (void) aty_ld_8(DAC_REGS + 2, par); 587 aty_st_8(DAC_REGS + 2, (locationAddr << 1) + 0x20, par); 588 aty_st_8(DAC_REGS + 2, 0, par); 589 aty_st_8(DAC_REGS + 2, (program_bits & 0xFF00) >> 8, par); 590 aty_st_8(DAC_REGS + 2, (program_bits & 0xFF), par); 591 592 (void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */ 593 aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par); 594 return; 595} 596 597const struct aty_pll_ops aty_pll_stg1703 = { 598 .var_to_pll = aty_var_to_pll_1703, 599 .pll_to_var = aty_pll_1703_to_var, 600 .set_pll = aty_set_pll_1703, 601}; 602 603 604 /* 605 * Chrontel 8398 Clock Chip 606 */ 607 608static int aty_var_to_pll_8398(const struct fb_info *info, u32 vclk_per, 609 u32 bpp, union aty_pll *pll) 610{ 611 u32 tempA, tempB, fOut, longMHz100, diff, preDiff; 612 613 u32 mhz100; /* in 0.01 MHz */ 614 u32 program_bits; 615 /* u32 post_divider; */ 616 u32 mach64MinFreq, mach64MaxFreq, mach64RefFreq; 617 u16 m, n, k = 0, save_m, save_n, twoToKth; 618 619 /* Calculate the programming word */ 620 mhz100 = 100000000 / vclk_per; 621 mach64MinFreq = MIN_FREQ_2595; 622 mach64MaxFreq = MAX_FREQ_2595; 623 mach64RefFreq = REF_FREQ_2595; /* 14.32 MHz */ 624 625 save_m = 0; 626 save_n = 0; 627 628 /* Calculate program word */ 629 if (mhz100 == 0) 630 program_bits = 0xE0; 631 else { 632 if (mhz100 < mach64MinFreq) 633 mhz100 = mach64MinFreq; 634 if (mhz100 > mach64MaxFreq) 635 mhz100 = mach64MaxFreq; 636 637 longMHz100 = mhz100 * 256 / 100; /* 8 bit scale this */ 638 639 while (mhz100 < (mach64MinFreq << 3)) { 640 mhz100 <<= 1; 641 k++; 642 } 643 644 twoToKth = 1 << k; 645 diff = 0; 646 preDiff = 0xFFFFFFFF; 647 648 for (m = MIN_M; m <= MAX_M; m++) { 649 for (n = MIN_N; n <= MAX_N; n++) { 650 tempA = 938356; /* 14.31818 * 65536 */ 651 tempA *= (n + 8); /* 43..256 */ 652 tempB = twoToKth * 256; 653 tempB *= (m + 2); /* 4..32 */ 654 fOut = tempA / tempB; /* 8 bit scale */ 655 656 if (longMHz100 > fOut) 657 diff = longMHz100 - fOut; 658 else 659 diff = fOut - longMHz100; 660 661 if (diff < preDiff) { 662 save_m = m; 663 save_n = n; 664 preDiff = diff; 665 } 666 } 667 } 668 669 program_bits = (k << 6) + (save_m) + (save_n << 8); 670 } 671 672 pll->ics2595.program_bits = program_bits; 673 pll->ics2595.locationAddr = 0; 674 pll->ics2595.post_divider = 0; 675 pll->ics2595.period_in_ps = vclk_per; 676 677 return 0; 678} 679 680static u32 aty_pll_8398_to_var(const struct fb_info *info, 681 const union aty_pll *pll) 682{ 683 return (pll->ics2595.period_in_ps); /* default for now */ 684} 685 686static void aty_set_pll_8398(const struct fb_info *info, 687 const union aty_pll *pll) 688{ 689 struct atyfb_par *par = (struct atyfb_par *) info->par; 690 u32 program_bits; 691 u32 locationAddr; 692 693 char old_crtc_ext_disp; 694 char tmp; 695 696 old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par); 697 aty_st_8(CRTC_GEN_CNTL + 3, 698 old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par); 699 700 program_bits = pll->ics2595.program_bits; 701 locationAddr = pll->ics2595.locationAddr; 702 703 /* Program clock */ 704 tmp = aty_ld_8(DAC_CNTL, par); 705 aty_st_8(DAC_CNTL, tmp | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3, par); 706 707 aty_st_8(DAC_REGS, locationAddr, par); 708 aty_st_8(DAC_REGS + 1, (program_bits & 0xff00) >> 8, par); 709 aty_st_8(DAC_REGS + 1, (program_bits & 0xff), par); 710 711 tmp = aty_ld_8(DAC_CNTL, par); 712 aty_st_8(DAC_CNTL, (tmp & ~DAC_EXT_SEL_RS2) | DAC_EXT_SEL_RS3, 713 par); 714 715 (void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */ 716 aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par); 717 718 return; 719} 720 721const struct aty_pll_ops aty_pll_ch8398 = { 722 .var_to_pll = aty_var_to_pll_8398, 723 .pll_to_var = aty_pll_8398_to_var, 724 .set_pll = aty_set_pll_8398, 725}; 726 727 728 /* 729 * AT&T 20C408 Clock Chip 730 */ 731 732static int aty_var_to_pll_408(const struct fb_info *info, u32 vclk_per, 733 u32 bpp, union aty_pll *pll) 734{ 735 u32 mhz100; /* in 0.01 MHz */ 736 u32 program_bits; 737 /* u32 post_divider; */ 738 u32 mach64MinFreq, mach64MaxFreq, mach64RefFreq; 739 u32 temp, tempB; 740 u16 remainder, preRemainder; 741 short divider = 0, tempA; 742 743 /* Calculate the programming word */ 744 mhz100 = 100000000 / vclk_per; 745 mach64MinFreq = MIN_FREQ_2595; 746 mach64MaxFreq = MAX_FREQ_2595; 747 mach64RefFreq = REF_FREQ_2595; /* 14.32 MHz */ 748 749 /* Calculate program word */ 750 if (mhz100 == 0) 751 program_bits = 0xFF; 752 else { 753 if (mhz100 < mach64MinFreq) 754 mhz100 = mach64MinFreq; 755 if (mhz100 > mach64MaxFreq) 756 mhz100 = mach64MaxFreq; 757 758 while (mhz100 < (mach64MinFreq << 3)) { 759 mhz100 <<= 1; 760 divider += 0x40; 761 } 762 763 temp = (unsigned int) mhz100; 764 temp = (unsigned int) (temp * (MIN_N_408 + 2)); 765 temp -= ((short) (mach64RefFreq << 1)); 766 767 tempA = MIN_N_408; 768 preRemainder = 0xFFFF; 769 770 do { 771 tempB = temp; 772 remainder = tempB % mach64RefFreq; 773 tempB = tempB / mach64RefFreq; 774 if (((tempB & 0xFFFF) <= 255) 775 && (remainder <= preRemainder)) { 776 preRemainder = remainder; 777 divider &= ~0x3f; 778 divider |= tempA; 779 divider = 780 (divider & 0x00FF) + 781 ((tempB & 0xFF) << 8); 782 } 783 temp += mhz100; 784 tempA++; 785 } while (tempA <= 32); 786 787 program_bits = divider; 788 } 789 790 pll->ics2595.program_bits = program_bits; 791 pll->ics2595.locationAddr = 0; 792 pll->ics2595.post_divider = divider; /* fuer nix */ 793 pll->ics2595.period_in_ps = vclk_per; 794 795 return 0; 796} 797 798static u32 aty_pll_408_to_var(const struct fb_info *info, 799 const union aty_pll *pll) 800{ 801 return (pll->ics2595.period_in_ps); /* default for now */ 802} 803 804static void aty_set_pll_408(const struct fb_info *info, 805 const union aty_pll *pll) 806{ 807 struct atyfb_par *par = (struct atyfb_par *) info->par; 808 u32 program_bits; 809 u32 locationAddr; 810 811 u8 tmpA, tmpB, tmpC; 812 char old_crtc_ext_disp; 813 814 old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par); 815 aty_st_8(CRTC_GEN_CNTL + 3, 816 old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par); 817 818 program_bits = pll->ics2595.program_bits; 819 locationAddr = pll->ics2595.locationAddr; 820 821 /* Program clock */ 822 aty_dac_waste4(par); 823 tmpB = aty_ld_8(DAC_REGS + 2, par) | 1; 824 aty_dac_waste4(par); 825 aty_st_8(DAC_REGS + 2, tmpB, par); 826 827 tmpA = tmpB; 828 tmpC = tmpA; 829 tmpA |= 8; 830 tmpB = 1; 831 832 aty_st_8(DAC_REGS, tmpB, par); 833 aty_st_8(DAC_REGS + 2, tmpA, par); 834 835 udelay(400); /* delay for 400 us */ 836 837 locationAddr = (locationAddr << 2) + 0x40; 838 tmpB = locationAddr; 839 tmpA = program_bits >> 8; 840 841 aty_st_8(DAC_REGS, tmpB, par); 842 aty_st_8(DAC_REGS + 2, tmpA, par); 843 844 tmpB = locationAddr + 1; 845 tmpA = (u8) program_bits; 846 847 aty_st_8(DAC_REGS, tmpB, par); 848 aty_st_8(DAC_REGS + 2, tmpA, par); 849 850 tmpB = locationAddr + 2; 851 tmpA = 0x77; 852 853 aty_st_8(DAC_REGS, tmpB, par); 854 aty_st_8(DAC_REGS + 2, tmpA, par); 855 856 udelay(400); /* delay for 400 us */ 857 tmpA = tmpC & (~(1 | 8)); 858 tmpB = 1; 859 860 aty_st_8(DAC_REGS, tmpB, par); 861 aty_st_8(DAC_REGS + 2, tmpA, par); 862 863 (void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */ 864 aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par); 865 return; 866} 867 868const struct aty_pll_ops aty_pll_att20c408 = { 869 .var_to_pll = aty_var_to_pll_408, 870 .pll_to_var = aty_pll_408_to_var, 871 .set_pll = aty_set_pll_408, 872}; 873 874 875 /* 876 * Unsupported DAC and Clock Chip 877 */ 878 879static int aty_set_dac_unsupported(const struct fb_info *info, 880 const union aty_pll *pll, u32 bpp, 881 u32 accel) 882{ 883 struct atyfb_par *par = (struct atyfb_par *) info->par; 884 885 aty_st_le32(BUS_CNTL, 0x890e20f1, par); 886 aty_st_le32(DAC_CNTL, 0x47052100, par); 887 /* new in 2.2.3p1 from Geert. ???????? */ 888 aty_st_le32(BUS_CNTL, 0x590e10ff, par); 889 aty_st_le32(DAC_CNTL, 0x47012100, par); 890 return 0; 891} 892 893static int dummy(void) 894{ 895 return 0; 896} 897 898const struct aty_dac_ops aty_dac_unsupported = { 899 .set_dac = aty_set_dac_unsupported, 900}; 901 902const struct aty_pll_ops aty_pll_unsupported = { 903 .var_to_pll = (void *) dummy, 904 .pll_to_var = (void *) dummy, 905 .set_pll = (void *) dummy, 906}; 907